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REV. A

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

www.analog.com

Fax: 781/326-8703

ADV7310/ADV7311

Multiformat 216 MHz

Video Encoder with Six NSV

12-Bit DACs

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

FEATURES
High Definition Input Formats

8-/10-, 16-/20-, 24-/30-Bit (4:2:2, 4:4:4) Parallel YCrCb
Compliant with:

SMPTE 293M (525p)
BTA T-1004 EDTV2 (525p)
ITU-R BT.1358 (625p/525p)
ITU-R BT.1362 (625p/525p)
SMPTE 274M (1080i) at 30 Hz and 25 Hz
SMPTE 296M (720p)
RGB in 3 10-Bit 4:4:4 Input Format

HDTV RGB Supported:

RGB, RGBHV
Other High Definition Formats Using Async

Timing Mode

High Definition Output Formats

YPrPb Progressive Scan (EIA-770.1, EIA-770.2)
YPrPb HDTV (EIA 770.3)
RGB, RGBHV
CGMS-A (720p/1080i)
Macrovision Rev 1.1 (525p/625p)*
CGMS-A (525p)

Standard Definition Input Formats

CCIR-656 4:2:2 8-/10-/16-/20-Bit Parallel Input

Standard Definition Output Formats

Composite NTSC M/N
Composite PAL M/N/B/D/G/H/I, PAL-60
SMPTE 170M NTSC Compatible Composite Video
ITU-R BT.470 PAL Compatible Composite Video
S-Video (Y/C)
EuroScart RGB
Component YPrPb (Betacam, MII, SMPTE/EBU N10)
Macrovision Rev 7.1.L1*

CGMS/WSS
Closed Captioning

GENERAL FEATURES
Simultaneous SD and HD Inputs and Outputs
Oversampling up to 216 MHz
Programmable DAC Gain Control
Sync Outputs in All Modes
On-Board Voltage Reference

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

CLKIN_A
CLKIN_B

HSYNC

VSYNC

BLANK

Y9Y0

C9C0

S9S0

TIMING

GENERATOR

PLL

V
E
R
S
A

P
L

N
G

INTERFACE

D
E
M
U
X

STANDARD DEFINITION

CONTROL BLOCK

COLOR CONTROL

BRIGHTNESS

DNR

GAMMA

PROGRAMMABLE FILTERS

SD TEST PATTERN

HIGH DEFINITION

CONTROL BLOCK

HD TEST PATTERN

COLOR CONTROL

ADAPTIVE FILTER CTRL

SHARPNESS FILTER

PROGRAMMABLE

RGB MATRIX

12-BIT

DAC

12-BIT

DAC

12-BIT

DAC

12-BIT

DAC

12-BIT

DAC

12-BIT

DAC

ADV7310/
ADV7311

GENERAL DESCRIPTION

The ADV

7310/ADV7311 is a high speed, digital-to-analog

encoder on a single monolithic chip. It includes six high speed
NSV video D/A converters with TTL compatible inputs.

The ADV7310/ADV7311 has separate 8-/10-/16-/20-bit input
ports that accept data in high definition and/or standard definition
video format. For all standards, external horizontal, vertical,
and blanking signals or EAV/SAV timing codes control the
insertion of appropriate synchronization signals into the digi-
tal data stream and therefore the output signal.

Six 12-Bit NSV Precision Video DACs
2-Wire Serial I

Interface

Dual I/O Supply 2.5 V/3.3 V Operation
Analog and Digital Supply 2.5 V
On-Board PLL
64-Lead LQFP Package
Lead (Pb) Free Product

APPLICATIONS
High End DVD
High End PS DVD Recorders/Players
SD/Prog Scan/HDTV Display Devices
SD/HDTV Set Top Boxes
Professional Video Systems

*ADV7310 Only

Purchase of licensed I

C components of Analog Devices or one of its

sublicensed Associated Companies conveys a license for the purchaser under
the Philips I

C Patent Rights to use these components in an I

C system,

provided that the system conforms to the I

C Standard Specification as

defined by Philips.

REV. A

ADV7310/ADV7311

DETAILED FEATURES
High Definition Programmable Features (720p 1080i)

2 Oversampling (148.5 MHz)
Internal Test Pattern Generator

(Color Hatch, Black Bar, Flat Field/Frame)

Fully Programmable YCrCb to RGB Matrix
Gamma Correction
Programmable Adaptive Filter Control
Programmable Sharpness Filter Control
CGMS-A (720p/1080i)

High Definition Programmable Features (525p/625p)

8 Oversampling (216 MHz Output)
Internal Test Pattern Generator

(Color Hatch, Black Bar, Flat Frame)

Individual Y and PrPb Output Delay
Gamma Correction
Programmable Adaptive Filter Control
Fully Programmable YCrCb to RGB Matrix
Undershoot Limiter
Macrovision Rev 1.1 (525p/625p)*
CGMS-A (525p)

Standard Definition Programmable Features

16 Oversampling (216 MHz)
Internal Test Pattern Generator (Color Bars, Black Bar)

*ADV7310 Only

Controlled Edge Rates for Sync, Active Video
Individual Y and PrPb Output Delay
Gamma Correction
Digital Noise Reduction (DNR)
Multiple Chroma and Luma Filters
Luma-SSAFTM Filter with Programmable

Gain/Attenuation

PrPb SSAFTM
Separate Pedestal Control on Component and
Composite/S-Video Output
VCR FF/RW Sync Mode
Macrovision Rev 7.1.L1*
CGMS/WSS
Closed Captioning

Standards Directly Supported

Frame

Clk

Resolution

Rate (Hz)

Input (MHz)

Standard

720 480

29.97

ITU-R BT.656

720 576

ITU-R BT.656

720 483

59.94

SMPTE 293M

720 480

59.94

BTA T-1004

720 576

ITU-R BT.1362

1280 720

74.25

SMPTE 296M

1920 1080

74.25

SMPTE 274M

1920 1080

74.25

SMPTE 274M

Other standards are supported in Async Timing Mode.
*SMPTE 274M-1998: System no. 6

DETAILED FUNCTIONAL BLOCK DIAGRAM

CLKIN_A

P_BLANK

P_HSYNC

P_VSYNC

S_BLANK

S_HSYNC

S_VSYNC

CLKIN_B

HD PIXEL

INPUT

SD PIXEL

INPUT

DE-

INTER-

LEAVE

TEST

PATTERN

SHARPNESS

AND

ADAPTIVE

FILTER

CONT

LUMA

AND

CHROMA

FILTERS

ROL

Y COLOR

CR COLOR
CB COLOR

4:2:2

4:4:4

TIMING

GENERATOR

TIMING

GENERATOR

DE-

INTER-

LEAVE

TEST

PATTERN

DNR

GAMMA

COLOR

CONTROL

SYNC

INSERTION

CLOCK

CONTROL

AND PLL

UV SSAF

PS 8

HDTV 2

RGB

MATRIX

SD 16

OVER-

SAMPLING

DAC

MODULATION

CGMS

WSS

TERMINOLOGY

Standard Definition Video, conforming to
ITU-R BT.601/ITU-R BT.656.

High Definition Video, i.e., Progressive Scan or HDTV.

Progressive Scan Video, conforming to SMPTE 293M,
ITU-R BT.1358, BTAT-1004EDTV2, or BTA1362.

HDTV

High Definition Television Video, conforming to
SMPTE 274M or SMPTE 296M.

YCrCb

SD, PS, or HD Component Digital Video.

YPrPb

SD, PS, or HD Component Analog Video.

REV. A

ADV7310/ADV7311

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
DETAILED FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
DETAILED FUNCTIONAL BLOCK DIAGRAM . . . . . . . 2
TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
DYNAMIC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . 5
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 6
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 14
THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . 14
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 15
MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 16
REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Subaddress Register (SR7SR0) . . . . . . . . . . . . . . . . . . . 17

INPUT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . 30

Standard Definition Only . . . . . . . . . . . . . . . . . . . . . . . . . 30
Progressive Scan Only or HDTV Only . . . . . . . . . . . . . . . 30
Simultaneous Standard Definition and Progressive Scan

or HDTV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Progressive Scan at 27 MHz (Dual Edge) or 54 MHz . . . 31

OUTPUT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . 33
TIMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

HD Async Timing Mode . . . . . . . . . . . . . . . . . . . . . . . . . 34

HD TIMING RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

SD Real-Time Control, Subcarrier Reset,

and Timing Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
SD VCR FF/RW Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Vertical Blanking Interval . . . . . . . . . . . . . . . . . . . . . . . . . 38
Subcarrier Frequency Registers . . . . . . . . . . . . . . . . . . . . 38
Square Pixel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

FILTER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

HD Sinc Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SD Internal Filter Response . . . . . . . . . . . . . . . . . . . . . . . 40

Typical Performance Characteristics . . . . . . . . . . . . . . . . . . 41
COLOR CONTROLS AND RGB MATRIX . . . . . . . . . . . 45

HD Y Level, HD Cr Level, HD Cb Level . . . . . . . . . . . . 45
HD RGB Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Programming the RGB Matrix . . . . . . . . . . . . . . . . . . . . . 45
SD Luma and Color Control . . . . . . . . . . . . . . . . . . . . . . 45
SD Hue Adjust Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SD Brightness Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SD Brightness Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Double Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

CONTENTS

PROGRAMMABLE DAC GAIN CONTROL . . . . . . . . . . 47

Gamma Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

HD SHARPNESS FILTER CONTROL AND ADAPTIVE

FILTER CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
HD Sharpness Filter Mode . . . . . . . . . . . . . . . . . . . . . . . 49
HD Adaptive Filter Mode . . . . . . . . . . . . . . . . . . . . . . . . 49
HD Sharpness Filter and Adaptive Filter Application

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

SD Digital Noise Reduction . . . . . . . . . . . . . . . . . . . . . . . 52
Coring Gain Border . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Coring Gain Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
DNR Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Border Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Block Size Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
DNR Input Select Control . . . . . . . . . . . . . . . . . . . . . . . . 53
DNR Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Block Offset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

SD ACTIVE VIDEO EDGE . . . . . . . . . . . . . . . . . . . . . . . . 54

SAV/EAV Step Edge Control . . . . . . . . . . . . . . . . . . . . . . 54

BOARD DESIGN AND LAYOUT CONSIDERATIONS . 55

DAC Termination and Layout Considerations . . . . . . . . 55
Video Output Buffer and Optional Output Filter . . . . . . . 55
PCB Board Layout Considerations . . . . . . . . . . . . . . . . . 57
Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . 57
Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . 57

APPENDIX 1--COPY GENERATION MANAGEMENT

SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
PS CGMS Data Registers 20 . . . . . . . . . . . . . . . . . . . . . 59
SD CGMS Data Registers 20 . . . . . . . . . . . . . . . . . . . . . 59
HD/PS CGMS [Address 12h, Bit 6] . . . . . . . . . . . . . . . . 59
Function of CGMS Bits . . . . . . . . . . . . . . . . . . . . . . . . . . 59
CGMS Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

APPENDIX 2--SD WIDE SCREEN SIGNALING . . . . . . 61
APPENDIX 3--SD CLOSED CAPTIONING . . . . . . . . . . 62
APPENDIX 4--TEST PATTERNS . . . . . . . . . . . . . . . . . . 63
APPENDIX 5--SD TIMING MODES . . . . . . . . . . . . . . . 66

Mode 0 (CCIR-656)--Slave Option . . . . . . . . . . . . . . . . 66
Mode 0 (CCIR-656)--Master Option . . . . . . . . . . . . . . . 67
Mode 1--Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Mode 1--Master Option . . . . . . . . . . . . . . . . . . . . . . . . . 69
Mode 2--Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Mode 2--Master Option . . . . . . . . . . . . . . . . . . . . . . . . . 71
Mode 3--Master/Slave Option . . . . . . . . . . . . . . . . . . . . . 72

APPENDIX 6--HD TIMING . . . . . . . . . . . . . . . . . . . . . . 73
APPENDIX 7--VIDEO OUTPUT LEVELS . . . . . . . . . . . 74

HD YPrPb Output Levels . . . . . . . . . . . . . . . . . . . . . . . . 74
RGB Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
YUV Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

APPENDIX 8--VIDEO STANDARDS . . . . . . . . . . . . . . . 80
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 82
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

REV. A

ADV7310/ADV7311SPECIFICATIONS

= 2.375 V2.625 V, V

= 2.375 V2.625 V;

DD_IO

= 2.3753.6 V, V

REF

= 1.235 V, R

SET

= 3040 , R

LOAD

= 300 . All specifications T

MIN

to T

MAX

(0 C to 70 C), unless otherwise noted.)

Parameter

Min

Typ

Max

Unit

Test Conditions

STATIC PERFORMANCE

Resolution

Bits

Integral Nonlinearity

1.5

LSB

Differential Nonlinearity

, +ve

0.25

LSB

Differential Nonlinearity

, ve

1.5

LSB

DIGITAL OUTPUTS

Output Low Voltage, V

0.4 [0.4]

SINK

= 3.2 mA

Output High Voltage, V

2.4[2.0]

SOURCE

= 400

µA

Three-State Leakage Current

±1.0

µA

= 0.4 V, 2.4 V

Three-State Output Capacitance

DIGITAL AND CONTROL INPUTS

Input High Voltage, V

Input Low Voltage, V

0.8

Input Leakage Current

µA

= 2.4 V

Input Capacitance, C

ANALOG OUTPUTS

Full-Scale Output Current

4.1

4.33

4.6

Output Current Range

4.1

4.33

4.6

DAC-to-DAC Matching

1.0

Output Compliance Range, V

1.0

1.4

Output Capacitance, C

OUT

VOLTAGE REFERENCE

Internal Reference Range, V

REF

1.15

1.235

1.3

External Reference Range, V

REF

1.15

1.235

1.3

REF

Current

±10

µA

POWER REQUIREMENTS

Normal Power Mode

170

SD Only [16 ]

110

PS Only [8 ]

HDTV Only [2 ]

172

190

SD[16 , 10-bit] + PS[8 , 20-bit]

DD_IO

1.0

6, 7

Sleep Mode

200

µA

DD_IO

250

µA

POWER SUPPLY REJECTION RATIO

0.01

% / %

NOTES

Oversampling disabled. Static DAC performance will be improved with increased oversampling ratios.

DNL measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for ve DNL,
the actual step value lies below the ideal step value.

Value in brackets for V

DD_IO

= 2.375 V2.75 V.

External current required to overdrive internal V

REF

, the circuit current, is the continuous current required to drive the digital core.

is the total current required to supply all DACs including the V

REF

circuitry and the PLL circuitry.

All DACs on.

Guaranteed maximum by characterization.

Specifications subject to change without notice.

Part Number ADV7310

Document Outline