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FUNCTIONAL BLOCK DIAGRAM

EXTERNAL

ADDRESS

BUS

DATA

MEMORY

PROGRAM

MEMORY

EXTERNAL

DATA

BUS

ADSP-2100 CORE

ARITHMETIC UNITS

SHIFTER

MAC

ALU

MEMORY

SERIAL PORTS

SPORT 0

SPORT 1

DATA ADDRESS

GENERATORS

DAG 1

DAG 2

PROGRAM

SEQUENCER

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

TIMER

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

Low Cost DSP Microcomputers

ADSP-2104/ADSP-2109

SUMMARY
16-Bit Fixed-Point DSP Microprocessors with

On-Chip Memory

Enhanced Harvard Architecture for Three-Bus

Performance: Instruction Bus & Dual Data Buses

Independent Computation Units: ALU, Multiplier/

Accumulator, and Shifter

Single-Cycle Instruction Execution & Multifunction

Instructions

On-Chip Program Memory RAM or ROM

& Data Memory RAM

Integrated I/O Peripherals: Serial Ports and Timer

FEATURES
20 MIPS, 50 ns Maximum Instruction Rate
Separate On-Chip Buses for Program and Data Memory
Program Memory Stores Both Instructions and Data

(Three-Bus Performance)

Dual Data Address Generators with Modulo and

Bit-Reverse Addressing

Efficient Program Sequencing with Zero-Overhead

Looping: Single-Cycle Loop Setup

Automatic Booting of On-Chip Program Memory from

Byte-Wide External Memory (e.g., EPROM )

Double-Buffered Serial Ports with Companding Hardware,

Automatic Data Buffering, and Multichannel Operation

Three Edge- or Level-Sensitive Interrupts
Low Power IDLE Instruction
PLCC Package

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700

Fax: 617/326-8703

GENERAL DESCRIPTION

The ADSP-2104 and ADSP-2109 processors are single-chip
microcomputers optimized for digital signal processing (DSP)
and other high speed numeric processing applications. The
ADSP-2104/ADSP-2109 processors are built upon a common
core. Each processor combines the core DSP architecture--
computation units, data address generators, and program
sequencer--with differentiating features such as on-chip
program and data memory RAM (ADSP-2109 contains 4K
words of program ROM), a programmable timer, and two
serial ports.

Fabricated in a high speed, submicron, double-layer metal
CMOS process, the ADSP-2104/ADSP-2109 operates at
20 MIPS with a 50 ns instruction cycle time. The ADSP-2104L
and ADSP-2109L are 3.3 volt versions which operate at
13.824 MIPS with a 72.3 ns instruction cycle time. Every
instruction can execute in a single cycle. Fabrication in CMOS
results in low power dissipation.

The ADSP-2100 Family's flexible architecture and compre-
hensive instruction set support a high degree of parallelism.
In one cycle the ADSP-2104/ADSP-2109 can perform all
of the following operations:

Generate the next program address

Fetch the next instruction

Perform one or two data moves

Update one or two data address pointers

Perform a computation

Receive and transmit data via one or two serial ports

The ADSP-2104 contains 512 words of program RAM, 256
words of data RAM, an interval timer, and two serial ports.
The ADSP-2104L is a 3.3 volt power supply version of the
ADSP-2104; it is identical to the ADSP-2104 in all other
characteristics.

The ADSP-2109 contains 4K words of program ROM and
256 words of data RAM, an interval timer, and two serial ports.

The ADSP-2109L is a 3.3 volt power supply version of the
ADSP-2109; it is identical to the ADSP-2109 in all other
characteristics.

ADSP-2104/ADSP-2109

REV. 0

The ADSP-2109 is a memory-variant version of the ADSP-
2104 and contains factory-programmed on-chip ROM program
memory.

The ADSP-2109 eliminates the need for an external boot EPROM
in your system, and can also eliminate the need for any external
program memory by fitting the entire application program in
on-chip ROM. This device provides an excellent option for
volume applications where board space and system cost constraints
are of critical concern.

Development Tools

The ADSP-2104/ADSP-2109 processors are supported by a
complete set of tools for system development. The ADSP-2100
Family Development Software includes C and assembly
language tools that allow programmers to write code for any
ADSP-21xx processor. The ANSI C compiler generates ADSP-
21xx assembly source code, while the runtime C library provides
ANSI-standard and custom DSP library routines. The ADSP-
21xx assembler produces object code modules which the linker
combines into an executable file. The processor simulators provide
an interactive instruction-level simulation with a reconfigurable,

windowed user interface. A PROM splitter utility generates
PROM programmer compatible files.

EZ-ICE

in-circuit emulators allow debugging of ADSP-2104

systems by providing a full range of emulation functions such as
modification of memory and register values and execution
breakpoints. EZ-LAB

demonstration boards are complete DSP

systems that execute EPROM-based programs.

The EZ-Kit Lite is a very low cost evaluation/development
platform that contains both the hardware and software needed
to evaluate the ADSP-21xx architecture.

Additional details and ordering information is available in the
ADSP-2100 Family Software & Hardware Development Tools data
sheet (ADDS-21xx-TOOLS). This data sheet can be requested
from any Analog Devices sales office or distributor.

Additional Information

This data sheet provides a general overview of ADSP-2104/
ADSP-2109 processor functionality. For detailed design
information on the architecture and instruction set, refer to the
ADSP-2100 Family User's Manual, available from Analog
Devices.

SPECIFICATIONS (ADSP-2104L/ADSP-2109L) . . . . . . 16
Recommended Operating Conditions . . . . . . . . . . . . . . . . 16
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Supply Current & Power . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . . 18
Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 18
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

TIMING PARAMETERS (ADSP-2104/ADSP-2109) . . . . . 20
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Interrupts & Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Bus RequestBus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

TIMING PARAMETERS (ADSP-2104L/ADSP-2109L) . . 27
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Interrupts & Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Bus RequestBus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

PIN CONFIGURATIONS
68-Lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

PACKAGE OUTLINE DIMENSIONS
68-Lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.

TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 1
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . 3
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Program Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . 6
Program Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Boot Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Low Power IDLE Instruction . . . . . . . . . . . . . . . . . . . . . . . 8
ADSP-2109 Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Procedure for ADSP-2109 ROM Processors . . . . 9
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SPECIFICATIONS (ADSP-2104/ADSP-2109) . . . . . . . . 12
Recommended Operating Conditions . . . . . . . . . . . . . . . . 12
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Supply Current & Power . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . . 14
Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 14
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

ADSP-2104/ADSP-2109

REV. 0

ARCHITECTURE OVERVIEW

Figure 1 shows a block diagram of the ADSP-2104/ADSP-2109
architecture. The processor contains three independent compu-
tational units: the ALU, the multiplier/accumulator (MAC), and
the shifter. The computational units process 16-bit data directly
and have provisions to support multiprecision computations.
The ALU performs a standard set of arithmetic and logic
operations; division primitives are also supported. The MAC
performs single-cycle multiply, multiply/add, and multiply/
subtract operations. The shifter performs logical and arithmetic
shifts, normalization, denormalization, and derive exponent
operations. The shifter can be used to efficiently implement
numeric format control including multiword floating-point
representations.

The internal result (R) bus directly connects the computational
units so that the output of any unit may be used as the input of
any unit on the next cycle.

A powerful program sequencer and two dedicated data address
generators ensure efficient use of these computational units.
The sequencer supports conditional jumps, subroutine calls,
and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-2104/ADSP-2109 executes looped code
with zero overhead--no explicit jump instructions are required
to maintain the loop. Nested loops are also supported.

Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for

circular buffers. The circular buffering feature is also used by
the serial ports for automatic data transfers to (and from) on-
chip memory.

Efficient data transfer is achieved with the use of five internal
buses:

· Program Memory Address (PMA) Bus
· Program Memory Data (PMD) Bus
· Data Memory Address (DMA) Bus
· Data Memory Data (DMD) Bus
· Result (R) Bus

The two address buses (PMA, DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD, DMD) share a single external data bus.
The BMS, DMS, and PMS signals indicate which memory
space is using the external buses.

Program memory can store both instructions and data, permit-
ting the ADSP-2104/ADSP-2109 to fetch two operands in a
single cycle, one from program memory and one from data
memory. The processor can fetch an operand from on-chip
program memory and the next instruction in the same cycle.

The memory interface supports slow memories and memory-
mapped peripherals with programmable wait state generation.
External devices can gain control of the processor's buses with
the use of the bus request/grant signals (BR, BG).

One bus grant execution mode (GO Mode) allows the ADSP-
2104/ADSP-2109 to continue running from internal memory.
A second execution mode requires the processor to halt while
buses are granted.

Figure 1. ADSP-2104/ADSP-2109 Block Diagram

R Bus

DMD BUS

PMD BUS

DMA BUS

PMA BUS

EXTERNAL
ADDRESS
BUS

EXTERNAL
DATA
BUS

BOOT

ADDRESS

GENERATOR

TIMER

BUS

EXCHANGE

COMPANDING

CIRCUITRY

DMA BUS

PMA BUS

DMD BUS

PMD BUS

PROGRAM

SEQUENCER

INSTRUCTION

REGISTER

PROGRAM

MEMORY

SRAM

or ROM

DATA

MEMORY

SRAM

DATA

ADDRESS

GENERATOR

DATA

ADDRESS

GENERATOR

INPUT REGS

OUTPUT REGS

SHIFTER

INPUT REGS

OUTPUT REGS

MAC

INPUT REGS

OUTPUT REGS

ALU

RECEIVE REG

TRANSMIT REG

SERIAL
PORT 0

MUX

RECEIVE REG

TRANSMIT REG

SERIAL
PORT 1

ADSP-2104/ADSP-2109

REV. 0

The ADSP-2104/ADSP-2109 can respond to several different
interrupts. There can be up to three external interrupts,
configured as edge- or level-sensitive. Internal interrupts can be
generated by the timer and serial ports. There is also a master
RESET

signal.

Booting circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After reset,
three wait states are automatically generated. This allows, for
example, the ADSP-2104 to use a 150 ns EPROM as external
boot memory. Multiple programs can be selected and loaded
from the EPROM with no additional hardware.

The data receive and transmit pins on SPORT1 (Serial Port 1)
can be alternatively configured as a general-purpose input flag
and output flag. You can use these pins for event signalling to
and from an external device.

A programmable interval timer can generate periodic interrupts.
A 16-bit count register (TCOUNT) is decremented every n
cycles, where n1 is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).

Serial Ports

The ADSP-2104/ADSP-2109 processor includes two synchro-
nous serial ports ("SPORTs") for serial communications and
multiprocessor communication.

The serial ports provide a complete synchronous serial interface
with optional companding in hardware. A wide variety of
framed or frameless data transmit and receive modes of opera-
tion are available. Each SPORT can generate an internal
programmable serial clock or accept an external serial clock.

Each serial port has a 5-pin interface consisting of the following
signals:

Signal Name

Function

SCLK

Serial Clock (I/O)

RFS

Receive Frame Synchronization (I/O)

TFS

Transmit Frame Synchronization (I/O)

Serial Data Receive

Serial Data Transmit

The serial ports offer the following capabilities:

Bidirectional--Each SPORT has a separate, double-buffered
transmit and receive function.

Flexible Clocking--Each SPORT can use an external serial
clock or generate its own clock internally.

Flexible Framing--The SPORTs have independent framing
for the transmit and receive functions; each function can run in
a frameless mode or with frame synchronization signals inter-
nally generated or externally generated; frame sync signals may
be active high or inverted, with either of two pulse widths and
timings.

Different Word Lengths--Each SPORT supports serial data
word lengths from 3 to 16 bits.

Companding in Hardware--Each SPORT provides optional
A-law and

-law companding according to CCITT recommen-

dation G.711.

Flexible Interrupt Scheme--Receive and transmit functions
can generate a unique interrupt upon completion of a data word
transfer.

Autobuffering with Single-Cycle Overhead--Each SPORT
can automatically receive or transmit the contents of an entire
circular data buffer with only one overhead cycle per data word;
an interrupt is generated after the transfer of the entire buffer is
completed.

Multichannel Capability (SPORT0 Only)--SPORT0
provides a multichannel interface to selectively receive or
transmit a 24-word or 32-word, time-division multiplexed serial
bit stream; this feature is especially useful for T1 or CEPT
interfaces, or as a network communication scheme for multiple
processors.

Alternate Configuration--SPORT1 can be alternatively
configured as two external interrupt inputs (IRQ0, IRQ1) and
the Flag In and Flag Out signals (FI, FO).

Interrupts

The interrupt controller lets the processor respond to interrupts
with a minimum of overhead. Up to three external interrupt
input pins, IRQ0, IRQ1, and IRQ2, are provided. IRQ2 is
always available as a dedicated pin; IRQ1 and IRQ0 may be
alternately configured as part of Serial Port 1. The ADSP-2104/
ADSP-2109 also supports internal interrupts from the timer,
and serial ports. The interrupts are internally prioritized and
individually maskable (except for RESET which is nonmaskable).
The IRQx input pins can be programmed for either level- or
edge-sensitivity. The interrupt priorities are shown in Table I.

Table I. Interrupt Vector Addresses & Priority

ADSP-2104/ADSP-2109
Interrupt

Interrupt

Source

Vector Address

RESET

Startup

0x0000

IRQ2

0x0004 (High Priority)

SPORT0 Transmit

0x0008

SPORT0 Receive

0x000C

SPORT1 Transmit or IRQ1

0x0010

SPORT1 Receive or IRQ0

0x0014

Timer

0x0018 (Low Priority)

The ADSP-2104/ADSP-2109 uses a vectored interrupt scheme:
when an interrupt is acknowledged, the processor shifts program
control to the interrupt vector address corresponding to the
interrupt received. Interrupts can be optionally nested so that a
higher priority interrupt can preempt the currently executing
interrupt service routine. Each interrupt vector location is four
instructions in length so that simple service routines can be
coded entirely in this space. Longer service routines require an
additional JUMP or CALL instruction.

Individual interrupt requests are logically ANDed with the bits
in the IMASK register; the highest-priority unmasked interrupt
is then selected.

ADSP-2104/ADSP-2109

REV. 0

The interrupt control register, ICNTL, allows the external
interrupts to be set as either edge- or level-sensitive. Depending
on bit 4 in ICNTL, interrupt service routines can either be
nested (with higher priority interrupts taking precedence) or be
processed sequentially (with only one interrupt service active at
a time).

The interrupt force and clear register, IFC, is a write-only register
that contains a force bit and a clear bit for each interrupt.

When responding to an interrupt, the ASTAT, MSTAT, and
IMASK status registers are pushed onto the status stack and
the PC counter is loaded with the appropriate vector address.
The status stack is seven levels deep to allow interrupt nesting.
The stack is automatically popped when a return from the
interrupt instruction is executed.

Pin Definitions

Table II shows pin definitions for the ADSP-2104/ADSP-2109
processors. Any inputs not used must be tied to V

SYSTEM INTERFACE

Figure 3 shows a typical system for the ADSP-2104/ADSP-2109,
with two serial I/O devices, a boot EPROM, and optional external
program and data memory. A total of 14.25K words of data
memory and 14.5K words of program memory is addressable.

Programmable wait-state generation allows the processors to
easily interface to slow external memories.

The ADSP-2104/ADSP-2109 also provides either: one external
interrupt (IRQ2) and two serial ports (SPORT0, SPORT1), or
three external interrupts (IRQ2, IRQ1, IRQ0) and one serial
port (SPORT0).

Clock Signals

The ADSP-2104/ADSP-2109's CLKIN input may be driven by
a crystal or by a TTL-compatible external clock signal. The
CLKIN input may not be halted or changed in frequency during
operation, nor operated below the specified low frequency limit.

If an external clock is used, it should be a TTL-compatible
signal running at the instruction rate. The signal should be
connected to the processor's CLKIN input; in this case, the
XTAL input must be left unconnected.

Because the processor includes an on-chip oscillator circuit, an
external crystal may also be used. The crystal should be con-
nected across the CLKIN and XTAL pins, with two capacitors
connected as shown in Figure 2. A parallel-resonant, fundamen-
tal frequency, microprocessor-grade crystal should be used.

Table II. ADSP-2104/ADSP-2109 Pin Definitions

Pin

# of

Input /

Name(s)

Pins

Output

Function

Address

Address outputs for program, data and boot memory.

Data

I/O

Data I/O pins for program and data memories. Input only for
boot memory, with two MSBs used for boot memory addresses.
Unused data lines may be left floating.

RESET

Processor Reset Input

IRQ2

External Interrupt Request #2

External Bus Request Input

External Bus Grant Output

PMS

External Program Memory Select

DMS

External Data Memory Select

BMS

Boot Memory Select

External Memory Read Enable

External Memory Write Enable

MMAP

Memory Map Select Input

CLKIN, XTAL

External Clock or Quartz Crystal Input

CLKOUT

Processor Clock Output

Power Supply Pins

GND

Ground Pins

SPORT0

I/O

Serial Port 0 Pins (TFS0, RFS0, DT0, DR0, SCLK0)

SPORT1

I/O

Serial Port 1 Pins (TFS1, RFS1, DT1, DR1, SCLK1)

or Interrupts & Flags:

IRQ0

(RFS1)

External Interrupt Request #0

IRQ1

(TFS1)

External Interrupt Request #1

FI (DR1)

Flag Input Pin

FO (DT1)

Flag Output Pin

NOTES

Unused data bus lines may be left floating.

must be tied high (to V

) if not used.

ADSP-2104/ADSP-2109

REV. 0

CLKIN

CLKOUT

XTAL

ADSP-2104/

ADSP-2109

Figure 2. External Crystal Connections

A clock output signal (CLKOUT) is generated by the processor,
synchronized to the processor's internal cycles.

Reset

The RESET

signal initiates a complete reset of the processor.

The RESET signal must be asserted when the chip is powered
up to assure proper initialization. If the RESET signal is applied
during initial power-up, it must be held long enough to allow
the processor's internal clock to stabilize. If RESET is activated
at any time after power-up and the input clock frequency does
not change, the processor's internal clock continues and does
not require this stabilization time.

The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V

applied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 t

cycles will ensure that the PLL has locked (this does

not, however, include the crystal oscillator start-up time).
During this power-up sequence the RESET signal should be
held low. On any subsequent resets, the RESET signal must
meet the minimum pulse width specification, t

RSP

To generate the RESET signal, use either an RC circuit with an
external Schmidt trigger or a commercially available reset IC.
(Do not use only an RC circuit.)

The RESET input resets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MSTAT
register. When RESET is released, the boot loading sequence is
performed (provided there is no pending bus request and the
chip is configured for booting, with MMAP = 0). The first
instruction is then fetched from internal program memory
location 0x0000.

Program Memory Interface

The on-chip program memory address bus (PMA) and on-chip
program memory data bus (PMD) are multiplexed with the on-
chip data memory buses (DMA, DMD), creating a single
external data bus and a single external address bus. The external
data bus is bidirectional and is 24 bits wide to allow instruction
fetches from external program memory. Program memory may
contain code and data.

The external address bus is 14 bits wide.

The data lines are bidirectional. The program memory select
(PMS) signal indicates accesses to program memory and can be
used as a chip select signal. The write (WR) signal indicates a
write operation and is used as a write strobe. The read (RD)
signal indicates a read operation and is used as a read strobe or
output enable signal.

The processor writes data from the 16-bit registers to 24-bit
program memory using the PX register to provide the lower
eight bits. When the processor reads 16-bit data from 24-bit
program memory to a 16-bit data register, the lower eight bits
are placed in the PX register.

The program memory interface can generate 0 to 7 wait states
for external memory devices; default is to 7 wait states after
RESET

Figure 3. ADSP-2104/ADSP-2109 System

CLKIN

RESET

IRQ2

BMS

ADSP-2104

ADSP-2109

CLKOUT

ADDR

DATA

(OPTIONAL)

1x CLOCK

CRYSTAL

PMS

DMS

ADDR

13-0

DATA

23-0

ADDR

DATA

(OPTIONAL)

ADDR

DATA

BOOT

MEMORY

e.g. EPROM

2764

27128
27256
27512

PROGRAM

MEMORY

DATA

MEMORY

PERIPHERALS

D23-22

A13-0

15-8

23-0

23-8

13-0

XTAL

MMAP

SERIAL
DEVICE

(OPTIONAL)

SCLK1
RFS1

or IRQ0

TFS1

or IRQ1

DT1

or FO

DR1

or FI

SCLK0
RFS0
TFS0
DT0
DR0

SPORT 1

SPORT 0

SERIAL
DEVICE

(OPTIONAL)

THE TWO MSBs OF THE DATA BUS (D

23-22

) ARE USED TO SUPPLY THE TWO MSBs OF THE

BOOT MEMORY EPROM ADDRESS. THIS IS ONLY REQUIRED FOR THE 27256 AND 27512.

ADSP-2104/ADSP-2109

REV. 0

Program Memory Maps

Program memory can be mapped in two ways, depending on
the state of the MMAP pin. Figure 4 shows the ADSP-2104
program memory maps. Figure 5 shows the program memory
maps for the ADSP-2109.

INTERNAL RAM

LOADED FROM

EXTERNAL

BOOT MEMORY

EXTERNAL

0x01FF
0x0200

0x3FFF

0x0000

EXTERNAL

0x39FF
0x3A00

0x3FFF

0x0000

MMAP=0

MMAP=1

No Booting

0x37FF
0x3800

0x07FF
0x0800

512 WORDS

14K

INTERNAL RAM

512 WORDS

1.5K

RESERVED

1.5K

RESERVED

Figure 4. ADSP-2104 Program Memory Maps

INTERNAL

ROM

12K

EXTERNAL

0x3FFF

0x0000

EXTERNAL

0x3FFF

0x0000

MMAP=0

MMAP=1

0x37FF
0x3800

INTERNAL

ROM

INTERNAL

ROM

10K

EXTERNAL

0x07FF
0x0800

0x0FF0

0x0FFF
0x1000

0x0FF0

0x0FFF
0x1000

RESERVED

Figure 5. ADSP-2109 Program Memory Maps

ADSP-2104

When MMAP = 0, on-chip program memory RAM occupies
512 words beginning at address 0x0000. Off-chip program
memory uses the remaining 14K words beginning at address
0x0800. In this configurationwhen MMAP = 0the boot
loading sequence (described below in "Boot Memory Inter-
face") is automatically initiated when RESET is released.

When MMAP = 1, 14K words of off-chip program memory
begin at address 0x0000 and on-chip program memory RAM is
located in the 512 words between addresses 0x38000x39FF. In
this configuration, program memory is not booted although it
can be written to and read under program control.

Data Memory Interface

The data memory address bus (DMA) is 14 bits wide. The
bidirectional external data bus is 24 bits wide, with the upper 16
bits used for data memory data (DMD) transfers.

The data memory select (DMS) signal indicates access to data
memory and can be used as a chip select signal. The write (WR)
signal indicates a write operation and can be used as a write
strobe. The read (RD) signal indicates a read operation and can
be used as a read strobe or output enable signal.

The ADSP-2104/ADSP-2109 processors support memory-
mapped I/O, with the peripherals memory-mapped into the data
memory address space and accessed by the processor in the
same manner as data memory.

Data Memory Map
ADSP-2104

On-chip data memory RAM resides in the 256 words beginning
at address 0x3800, also shown in Figure 6. Data memory
locations from 0x3900 to the end of data memory at 0x3FFF
are reserved. Control and status registers for the system, timer,
wait-state configuration, and serial port operations are located in
this region of memory.

0x3900

0x0400

0x0000

1K EXTERNAL

DWAIT0

1K EXTERNAL

DWAIT1

10K EXTERNAL

DWAIT2

1K EXTERNAL

DWAIT3

0x0800

0x3000

256 WORDS

0x3C00

0x3FFF

1K EXTERNAL

DWAIT4

0x3400

0x3800

MEMORY-MAPPED

CONTROL REGISTERS

& RESERVED

EXTERNAL

RAM

INTERNAL

RAM

Figure 6. Data Memory Map

The remaining 14K of data memory is located off-chip. This
external data memory is divided into five zones, each associated
with its own wait-state generator. This allows slower peripherals
to be memory-mapped into data memory for which wait states
are specified. By mapping peripherals into different zones, you
can accommodate peripherals with different wait-state require-
ments. All zones default to seven wait states after RESET.

ADSP-2104/ADSP-2109

REV. 0

Boot Memory Interface

Boot memory is an external 16K by 8 space, divided into eight
separate 2K by 8 pages. The 8-bit bytes are automatically
packed into 24-bit instruction words by the processor, for
loading into on-chip program memory.

Three bits in the processors' System Control Register select
which page is loaded by the boot memory interface. Another bit
in the System Control Register allows the forcing of a boot
loading sequence under software control. Boot loading from
Page 0 after RESET is initiated automatically if MMAP = 0.

The boot memory interface can generate zero to seven wait
states; it defaults to three wait states after RESET. This allows
the ADSP-2104 to boot from a single low cost EPROM such as
a 27C256. Program memory is booted one byte at a time and
converted to 24-bit program memory words.

The BMS and RD signals are used to select and to strobe the
boot memory interface. Only 8-bit data is read over the data
bus, on pins D8-D15. To accommodate up to eight pages of
boot memory, the two MSBs of the data bus are used in the
boot memory interface as the two MSBs of the boot memory
address: D23, D22, and A13 supply the boot page number.

The ADSP-2100 Family Assembler and Linker allow the
creation of programs and data structures requiring multiple boot
pages during execution.

The BR signal is recognized during the booting sequence. The
bus is granted after loading the current byte is completed. BR
during booting may be used to implement booting under control
of a host processor.

Bus Interface

The ADSP-2104/ADSP-2109 can relinquish control of their
data and address buses to an external device. When the external
device requires control of the buses, it asserts the bus request
signal (BR). If the processor is not performing an external
memory access, it responds to the active BR input in the next
cycle by:

Three-stating the data and address buses and the PMS,

DMS, BMS, RD, WR output drivers,

Asserting the bus grant (BG) signal,

and halting program execution.

If the Go mode is set, however, the ADSP-2104/ADSP-2109
will not halt program execution until it encounters an instruc-
tion that requires an external memory access.

If the processor is performing an external memory access when
the external device asserts the BR signal, it will not three-state
the memory interfaces or assert the BG signal until the cycle
after the access completes (up to eight cycles later depending on

the number of wait states). The instruction does not need to be
completed when the bus is granted; the processor will grant the
bus in between two memory accesses if an instruction requires
more than one external memory access.

When the BR signal is released, the processor releases the BG
signal, re-enables the output drivers and continues program
execution from the point where it stopped.

The bus request feature operates at all times, including when
the processor is booting and when RESET is active. If this
feature is not used, the BR input should be tied high (to V

Low Power IDLE Instruction

The IDLE instruction places the processor in low power state in
which it waits for an interrupt. When an interrupt occurs, it is
serviced and execution continues with instruction following
IDLE. Typically this next instruction will be a JUMP back to
the IDLE instruction. This implements a low-power standby
loop.

The IDLE n instruction is a special version of IDLE that slows
the processor's internal clock signal to further reduce power
consumption. The reduced clock frequency, a programmable
fraction of the normal clock rate, is specified by a selectable
divisor, n, given in the IDLE instruction. The syntax of the
instruction is:

IDLE n;

where n = 16, 32, 64, or 128.

The instruction leaves the chip in an idle state, operating at the
slower rate. While it is in this state, the processor's other
internal clock signals, such as SCLK, CLKOUT, and the timer
clock, are reduced by the same ratio. Upon receipt of an
enabled interrupt, the processor will stay in the IDLE state for
up to a maximum of n CLKIN cycles, where n is the divisor
specified in the instruction, before resuming normal operation.

When the IDLE n instruction is used, it slows the processor's
internal clock and thus its response time to incoming interrupts
the 1-cycle response time of the standard IDLE state is in-
creased by n, the clock divisor. When an enabled interrupt is
received, the ADSP-21xx will remain in the IDLE state for up
to a maximum of n CLKIN cycles (where n = 16, 32, 64, or
128) before resuming normal operation.

When the IDLE n instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor's reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the IDLE state (a maximum of n
CLKIN cycles).

ADSP-2104/ADSP-2109

REV. 0

ADSP-2109 Prototyping

You can prototype your ADSP-2109 system with the ADSP-
2104 RAM-based processor. When code is fully developed and
debugged, it can be submitted to Analog Devices for conversion
into a ADSP-2109 ROM product.

The ADSP-2101 EZ-ICE emulator can be used for develop-
ment of ADSP-2109 systems. For the 3.3 V ADSP-2109, a
voltage converter interface board provides 3.3 V emulation.

Additional overlay memory is used for emulation of ADSP-2109
systems. It should be noted that due to the use of off-chip
overlay memory to emulate the ADSP-2109, a performance loss
may be experienced when both executing instructions and
fetching program memory data from the off-chip overlay
memory in the same cycle. This can be overcome by locating
program memory data in on-chip memory.

Ordering Procedure for ADSP-2109 ROM Processor

To place an order for a custom ROM-coded ADSP-2109, you
must:

1. Complete the following forms contained in the ADSP ROM

Ordering Package, available from your Analog Devices sales
representative:

ADSP-2109 ROM Specification Form
ROM Release Agreement
ROM NRE Agreement & Minimum Quantity Order (MQO)
Acceptance Agreement for Pre-Production ROM Products

2. Return the forms to Analog Devices along with two copies of

the Memory Image File (.EXE file) of your ROM code. The
files must be supplied on two 3.5" or 5.25" floppy disks for
the IBM PC (DOS 2.01 or higher).

3. Place a purchase order with Analog Devices for nonrecurring

engineering changes (NRE) associated with ROM product
development.

After this information is received, it is entered into Analog
Devices' ROM Manager System which assigns a custom ROM
model number to the product. This model number will be
branded on all prototype and production units manufactured to
these specifications.

To minimize the risk of code being altered during this process,
Analog Devices verifies that the .EXE files on both floppy disks
are identical, and recalculates the checksums for the .EXE file
entered into the ROM Manager System. The checksum data, in
the form of a ROM Memory Map, a hard copy of the .EXE file,
and a ROM Data Verification form are returned to you for
inspection.

A signed ROM Verification Form and a purchase order for
production units are required prior to any product being
manufactured. Prototype units may be applied toward the
minimum order quantity.

Upon completion of prototype manufacture, Analog Devices
will ship prototype units and a delivery schedule update for
production units. An invoice against your purchase order for the
NRE charges is issued at this time.

There is a charge for each ROM mask generated and a mini-
mum order quantity. Consult your sales representative for
details. A separate order must be placed for parts of a specific
package type, temperature range, and speed grade.

ADSP-2104/ADSP-2109

REV. 0

Instruction Set

The ADSP-2104/ADSP-2109 assembly language uses an algebraic
syntax for ease of coding and readability. The sources and
destinations of computations and data movements are written
explicitly in each assembly statement, eliminating cryptic
assembler mnemonics.

Every instruction assembles into a single 24-bit word and
executes in a single cycle. The instructions encompass a wide
variety of instruction types along with a high degree of

operational parallelism. There are five basic categories of
instructions: data move instructions, computational instruc-
tions, multifunction instructions, program flow control instruc-
tions and miscellaneous instructions. Multifunction instructions
perform one or two data moves and a computation.

The instruction set is summarized below. The ADSP-2100
Family Users Manual contains a complete reference to the
instruction set.

ALU Instructions

[IF cond]

AR|AF

xop + yop [+ C] ;

Add/Add with Carry

xop yop [+ C 1] ;

Subtract X Y/Subtract X Y with Borrow

yop xop [+ C 1] ;

Subtract Y X/Subtract Y X with Borrow

xop AND yop ;

AND

xop OR yop ;

xop XOR yop ;

XOR

PASS xop ;

Pass, Clear

xop ;

Negate

NOT xop ;

NOT

ABS xop ;

Absolute Value

yop + 1 ;

Increment

yop 1 ;

Decrement

DIVS yop, xop ;

Divide

DIVQ xop ;

MAC Instructions

[IF cond]

MR|MF =

xop * yop ;

Multiply

MR + xop * yop ;

Multiply/Accumulate

MR xop * yop ;

Multiply/Subtract

MR ;

Transfer MR

0 ;

Clear

IF MV SAT MR ;

Conditional MR Saturation

Shifter Instructions

[IF cond]

SR = [SR OR] ASHIFT xop ;

Arithmetic Shift

[IF cond]

SR = [SR OR] LSHIFT xop ;

Logical Shift

SR = [SR OR] ASHIFT xop BY <exp>;

Arithmetic Shift Immediate

SR = [SR OR] LSHIFT xop BY <exp>;

Logical Shift Immediate

[IF cond]

SE = EXP xop ;

Derive Exponent

[IF cond]

SB = EXPADJ xop ;

Block Exponent Adjust

[IF cond]

SR = [SR OR] NORM xop ;

Normalize

Data Move Instructions

reg = reg ;

Register-to-Register Move

reg = <data> ;

Load Register Immediate

reg = DM (<addr>) ;

Data Memory Read (Direct Address)

dreg = DM (Ix , My) ;

Data Memory Read (Indirect Address)

dreg = PM (Ix , My) ;

Program Memory Read (Indirect Address)

DM (<addr>) = reg ;

Data Memory Write (Direct Address)

DM (Ix , My) = dreg ;

Data Memory Write (Indirect Address)

PM (Ix , My) = dreg ;

Program Memory Write (Indirect Address)

Multifunction Instructions

<ALU>|<MAC>|<SHIFT> , dreg = dreg ;

Computation with Register-to-Register Move

<ALU>|<MAC>|<SHIFT> , dreg = DM (Ix , My) ;

Computation with Memory Read

<ALU>|<MAC>|<SHIFT> , dreg = PM (Ix , My) ;

Computation with Memory Read

DM (Ix , My) = dreg , <ALU>|<MAC>|<SHIFT> ;

Computation with Memory Write

PM (Ix , My) = dreg , <ALU>|<MAC>|<SHIFT> ;

Computation with Memory Write

dreg = DM (Ix , My) , dreg = PM (Ix , My) ;

Data & Program Memory Read

<ALU>|<MAC> , dreg = DM (Ix , My) , dreg = PM (Ix , My) ;

ALU/MAC with Data & Program Memory Read

ADSP-2104/ADSP-2109

REV. 0

Program Flow Instructions

DO <addr> [UNTIL term] ;

Do Until Loop

[IF cond] JUMP (Ix) ;

Jump

[IF cond] JUMP <addr>;
[IF cond] CALL (Ix) ;

Call Subroutine

[IF cond] CALL <addr>;
IF [NOT ] FLAG_IN

JUMP <addr>;

Jump/Call on Flag In Pin

IF [NOT ] FLAG_IN

CALL <addr>;

[IF cond] SET|RESET|TOGGLE FLAG_OUT [, ...] ;

Modify Flag Out Pin

[IF cond] RTS ;

Return from Subroutine

[IF cond] RTI ;

Return from Interrupt Service Routine

IDLE [(n)] ;

Idle

Miscellaneous Instructions

NOP ;

No Operation

MODIFY (Ix , My);

Modify Address Register

[PUSH STS] [, POP CNTR] [, POP PC] [, POP LOOP] ;

Stack Control

ENA|DIS

SEC_REG [, ...] ;

Mode Control

BIT_REV
AV_LATCH
AR_SAT
M_MODE
TIMER
G_MODE

Notation Conventions

Index registers for indirect addressing

Modify registers for indirect addressing

<data>

Immediate data value

<addr>

Immediate address value

<exp>

Exponent (shift value) in shift immediate instructions (8-bit signed number)

<ALU>

Any ALU instruction (except divide)

<MAC>

Any multiply-accumulate instruction

<SHIFT>

Any shift instruction (except shift immediate)

cond

Condition code for conditional instruction

term

Termination code for DO UNTIL loop

dreg

Data register (of ALU, MAC, or Shifter)

reg

Any register (including dregs)

;

A semicolon terminates the instruction

Commas separate multiple operations of a single instruction

[ ]

Optional part of instruction

[, ...]

Optional, multiple operations of an instruction

option1 | option2

List of options; choose one.

Assembly Code Example

The following example is a code fragment that performs the filter tap update for an adaptive filter based on a least-mean-squared
algorithm. Notice that the computations in the instructions are written like algebraic equations.

MF=MX0* M Y1 ( RND), MX0=DM(I2,M1);

{ M F=error * b eta}

MR=MX0* M F ( RND), AY0=PM(I6,M5);

DO adapt UNTIL CE;

AR=MR1+AY0, MX0=DM(I2,M1), AY0=PM(I6,M7);

adapt:

PM(I6,M6)= A R, MR=MX0* MF ( RND);

MODIFY(I2,M3);

{Point to oldest data}

MODIFY(I6,M7);

{Point to start of data}

RECOMMENDED OPERATING CONDITIONS

K Grade

Parameter

Min

Max

Unit

Supply Voltage

4.50

5.50

AMB

Ambient Operating Temperature

+70

See "Environmental Conditions" for information on thermal specifications.

ELECTRICAL CHARACTERISTICS

Parameter

Test Conditions

Min

Max

Unit

Hi-Level Input Voltage

3, 5

@ V

= max

2.0

Hi-Level CLKIN Voltage

@ V

= max

2.2

Lo-Level Input Voltage

1, 3

@ V

= min

0.8

Hi-Level Output Voltage

2, 3, 7

@ V

= min, I

= 0.5 mA

2.4

@ V

= min, I

= 100

0.3

Lo-Level Output Voltage

2, 3, 7

@ V

= min, I

= 2 mA

0.4

Hi-Level Input Current

@ V

= max, V

= V

max

Lo-Level Input Current

@ V

= max, V

= 0 V

OZH

Three-State Leakage Current

@ V

= max, V

= V

max

OZL

Three-State Leakage Current

@ V

= max, V

= 0 V

Input Pin Capacitance

1, 8, 9

@ V

= 2.5 V, f

= 1.0 MHz, T

AMB

= 25

Output Pin Capacitance

4, 8, 9, 10

@ V

= 2.5 V, f

= 1.0 MHz, T

AMB

= 25

NOTES

Input-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0.

Output pins: BG, PMS, DMS, BMS, RD, WR, A0A13, CLKOUT, DT1, DT0.

Bidirectional pins: D0D23, SCLK1, RFS1, TFS1, SCLK0, RFS0, TFS0.

Three-state pins: A0A13, D0D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RSF1, TFS1, DT0, SCLK0, RFS0, TFS0.

Input-only pins: RESET, IRQ2, BR, MMAP, DR1, DR0.

0 V on BR, CLKIN Active (to force three-state condition).

Although specified for TTL outputs, all ADSP-2104/ADSP-2109 outputs are CMOS-compatible and will drive to V

and GND, assuming no dc loads.

Guaranteed but not tested.

Applies to PGA, PLCC, PQFP package types.

Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

ADSP-2104/ADSP-2109SPECIFICATIONS

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-2104/ADSP-2109 processor features proprietary ESD protection circuitry to dissipate
high energy electrostatic discharges (Human Body Model), permanent damage may occur to devices
subjected to such discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality. Unused devices must be stored in conductive foam
or shunts, and the foam should be discharged to the destination socket before the devices are
removed. Per method 3015 of MIL-STD-883, the ADSP-2104/ADSP-2109 processor has been
classified as Class 1 device.

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . 0.3 V to V

+ 0.3 V

Output Voltage Swing . . . . . . . . . . . . . . 0.3 V to V

+ 0.3 V

Operating Temperature Range (Ambient) . . . 55ºC to +125

Storage Temperature Range . . . . . . . . . . . . . 65

C to +125

Lead Temperature (10 sec) PGA . . . . . . . . . . . . . . . . . +300

Lead Temperature (5 sec) PLCC, PQFP, TQFP . . . . +280

*Stresses greater than those listed above may cause permanent damage to the

device. These are stress ratings only, and functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

WARNING!

ESD SENSITIVE DEVICE

REV. 0

ADSP-2104/ADSP-2109

REV. 0

SPECIFICATIONS (ADSP-2104/ADSP-2109)

SUPPLY CURRENT & POWER

Parameter

Test Conditions

Min

Max

Unit

Supply Current (Dynamic)

@ V

= max, t

= 50 ns

@ V

= max, t

= 72.3 ns

Supply Current (Idle)

1, 3

@ V

= max, t

= 50 ns

@ V

= max, t

= 72.3 ns

NOTES

Current reflects device operating with no output loads.

= 0.4 V and 2.4 V.

Idle refers to ADSP-2104/ADSP-2109 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V

or GND.

For typical supply current (internal power dissipation) figures, see Figure 7.

Figure 7. ADSP-2104/ADSP-2109 Power (Typical) vs. Frequency

POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

IDLE REFERS TO ADSP-2104/ADSP-2109 OPERATION DURING EXECUTION OF IDLE INSTRUCTION.

DEASSERTED PINS ARE DRIVEN TO EITHER V

OR GND.

MAXIMUM POWER DISSIPATION AT V

5.5V DURING EXECUTION OF

IDLE n INSTRUCTION.

POWER mW

30.00

20.00

13.83

10.00

25.00

IDLE 128

IDD IDLE

IDLE 16

55mW

41mW

40mW

60mW

42mW

41mW

FREQUENCY

 MHz

IDD IDLE n MODES

POWER mW

30.00

20.00

13.83

10.00

25.00

140

100

120

160

200

180

220

129mW

100mW

74mW

170mW

128mW

95mW

FREQUENCY

 MHz

IDD DYNAMIC

5.5V

5.0V

4.5V

POWER mW

30.00

20.00

13.83

10.00

25.00

55mW

38mW

28mW

60mW

42mW

31mW

FREQUENCY

 MHz

IDD IDLE

1, 2

5.5V

5.0V

4.5V

ADSP-2104/ADSP-2109

REV. 0

POWER DISSIPATION EXAMPLE

To determine total power dissipation in a specific application,
the following equation should be applied for each output:

C = load capacitance, f = output switching frequency.

Example:

In an ADSP-2104 application where external data memory is
used and no other outputs are active, power dissipation is
calculated as follows:

Assumptions:

External data memory is accessed every cycle with 50% of the
address pins switching.

External data memory writes occur every other cycle with
50% of the data pins switching.

Each address and data pin has a 10 pF total load at the pin.

The application operates at V

= 5.0 V and t

= 50 ns.

Total Power Dissipation = P

INT

+ (C

f )

INT

= internal power dissipation (from Figure 7).

f ) is calculated for each output:

# of

Output

Pins

Address, DMS 8

10 pF

20 MHz = 40.0 mW

Data, WR

10 pF

10 MHz = 22.5 mW

10 pF

10 MHz = 2.5 mW

CLKOUT

10 pF

20 MHz = 5.0 mW

70.0 mW

Total power dissipation for this example = P

INT

+ 70.0 mW.

ENVIRONMENTAL CONDITIONS

Ambient Temperature Rating:

AMB

= T

CASE

(PD

)

CASE

= Case Temperature in

PD = Power Dissipation in W

= Thermal Resistance (Case-to-Ambient)

= Thermal Resistance (Junction-to-Ambient)

= Thermal Resistance (Junction-to-Case)

Package

PLCC

C/W

SPECIFICATIONS (ADSP-2104/ADSP-2109)

CAPACITIVE LOADING

Figures 8 and 9 show capacitive loading characteristics.

Figure 8. Typical Output Rise Time vs. Load Capacitance, C

(at Maximum Ambient Operating Temperature)

Figure 9. Typical Output Valid Delay or Hold vs. Load
Capacitance, C

(at Maximum Ambient Operating Temperature)

 pF

150

125

100

RISE TIME (0.8V - 2.0V) ns

= 4.5V

175

 pF

100

125

150

VALID OUTPUT DELAY OR HOLD ns

= 4.5V

175

ADSP-2104/ADSP-2109

REV. 0

TEST CONDITIONS

Figure 10 shows voltage reference levels for ac measurements.

3.0V
1.5V
0.0V

2.0V
1.5V
0.8V

INPUT

OUTPUT

Figure 10. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)

Output Disable Time

Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The
output disable time (t

DIS

) is the difference of t

MEASURED

and

DECAY

, as shown in Figure 11. The time t

MEASURED

is the

interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage.

The decay time, t

DECAY

, is dependent on the capacitative load,

, and the current load, i

, on the output pin. It can be

approximated by the following equation:

DECAY

0.5 V

from which

DIS

= t

MEASURED

DECAY

is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.

Output Enable Time

Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (t

E NA

) is the interval from

when a reference signal reaches a high or low voltage level to
when the output has reached a specified high or low trip point,
as shown in Figure 11. If multiple pins (such as the data bus)
are enabled, the measurement value is that of the first pin to
start driving.

SPECIFICATIONS (ADSP-2104/ADSP-2109)

Figure 12. Equivalent Device Loading for AC Measurements
(Except Output Enable/Disable)

2.0V

1.0V

ENA

REFERENCE

SIGNAL

OUTPUT

DECAY

(MEASURED)

OUTPUT STOPS

DRIVING

OUTPUT STARTS

DRIVING

DIS

MEASURED

(MEASURED)

(MEASURED) 0.5V

(MEASURED) +0.5V

HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE
APPROXIMATELY 1.5V.

(MEASURED)

Figure 11. Output Enable/Disable

OUTPUT

PIN

50pF

+1.5V

RECOMMENDED OPERATING CONDITIONS

K Grade

Parameter

Min

Max

Unit

Supply Voltage

3.00

3.60

AMB

Ambient Operating Temperature

+70

See "Environmental Conditions" for information on thermal specifications.

ELECTRICAL CHARACTERISTICS

Parameter

Test Conditions

Min

Max

Unit

Hi-Level Input Voltage

1, 3

@ V

= max

2.0

Lo-Level Input Voltage

1, 3

@ V

= min

0.4

Hi-Level Output Voltage

2, 3, 6

@ V

= min, I

= 0.5 mA

2.4

Lo-Level Output Voltage

2, 3, 6

@ V

= min, I

= 2 mA

0.4

Hi-Level Input Current

@ V

= max, V

= V

max

Lo-Level Input Current

@ V

= max, V

= 0 V

OZH

Three-State Leakage Current

@ V

= max, V

= V

max

OZL

Three-State Leakage Current

@ V

= max, V

= 0 V

Input Pin Capacitance

1, 7, 8

@ V

= 2.5 V, f

= 1.0 MHz, T

AMB

= 25

Output Pin Capacitance

4, 7, 8, 9

@ V

= 2.5 V, f

= 1.0 MHz, T

AMB

= 25

NOTES

Input-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0.

Output pins: BG, PMS, DMS, BMS, RD, WR, A0A13, CLKOUT, DT1, DT0.

Bidirectional pins: D0D23, SCLK1, RFS1, TFS1, SCLK0, RFS0, TFS0.

Three-stateable pins: A0A13, D0D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RSF1, TFS1, DT0, SCLK0, RFS0, TFS0.

0 V on BR, CLKIN Active (to force three-state condition).

All outputs are CMOS and will drive to V

and GND with no dc loads.

Guaranteed but not tested.

Applies to PLCC package type.

Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

ADSP-2104L/ADSP-2109LSPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +4.5 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . 0.3 V to V

+ 0.3 V

Output Voltage Swing . . . . . . . . . . . . . . 0.3 V to V

+ 0.3 V

Operating Temperature Range (Ambient) . . . . 40

C to +85

Storage Temperature Range . . . . . . . . . . . . . 65

C to +150

Lead Temperature (5 sec) PLCC . . . . . . . . . . . . . . . . +280

*Stresses greater than those listed above may cause permanent damage to the

REV. 0

ADSP-2104/ADSP-2109

REV. 0

SPECIFICATIONS (ADSP-2104L /ADSP-2109L)

SUPPLY CURRENT & POWER (ADSP-2104L /ADSP-2109L)

Parameter

Test Conditions

Min

Max

Unit

Supply Current (Dynamic)

@ V

= max, t

= 72.3 ns

Supply Current (Idle)

1, 3

@ V

= max, t

= 72.3 ns

NOTES

Current reflects device operating with no output loads.

= 0.4 V and 2.4 V.

Idle refers to ADSP-2104L/ADSP-2109L state of operation during execution of IDLE instruction. Deasserted pins are driven to either V

or GND.

For typical supply current (internal power dissipation) figures, see Figure 13.

Figure 13. ADSP-2104L/ADSP-2109L Power (Typical) vs. Frequency

POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

IDLE REFERS TO ADSP-2104L/ADSP-2109L OPERATION DURING EXECUTION OF IDLE INSTRUCTION.

DEASSERTED PINS ARE DRIVEN TO EITHER V

OR GND.

MAXIMUM POWER DISSIPATION AT V

= 3.6V DURING EXECUTION OF

IDLE n INSTRUCTION.

15.00

13.83

10.00

7.00

5.00

POWER mW

IDD IDLE

FREQUENCY

 MHz

9mW

6mW

5mW

13mW

10mW

8mW

3.6V

3.30V

3.0V

POWER mW

IDLE DYNAMIC

1,2

FREQUENCY

 MHz

48mW

37mW

29mW

15mW

15.00

13.83

10.00

7.00

5.00

24mW

19mW

3.6V

3.30V

3.0V

15.00

13.83

10.00

7.00

5.00

POWER mW

FREQUENCY

 MHz

IDLE 128

IDLE 16

IDD IDLE

9mW

5mW

4mW

13mW

7mW

6mW

IDD IDLE n MODES

ADSP-2104/ADSP-2109

REV. 0

SPECIFICATIONS (ADSP-2104L /ADSP-2109L)

CAPACITIVE LOADING

Figures 14 and 15 show capacitive loading characteristics.

POWER DISSIPATION EXAMPLE

To determine total power dissipation in a specific application,
the following equation should be applied for each output:

C = load capacitance, f = output switching frequency.

Example:

In an ADSP-2104L application where external data memory is
used and no other outputs are active, power dissipation is
calculated as follows:

Assumptions:

External data memory is accessed every cycle with 50% of the
address pins switching.

External data memory writes occur every other cycle with
50% of the data pins switching.

Each address and data pin has a 10 pF total load at the pin.

The application operates at V

= 3.3 V and t

= 100 ns.

Total Power Dissipation = P

INT

+ (C

f )

INT

= internal power dissipation (from Figure 13).

f ) is calculated for each output:

# of

Output

Pins

Address, DMS 8

10 pF

3.3

10 MHz = 8.71 mW

Data, WR

10 pF

3.3

5 MHz

= 4.90 mW

10 pF

3.3

5 MHz

= 0.55 mW

CLKOUT

10 pF

3.3

10 MHz = 1.09 mW

15.25 mW

Total power dissipation for this example = P

INT

+ 15.25 mW.

ENVIRONMENTAL CONDITIONS

Ambient Temperature Rating:

AMB

= T

CASE

(PD

)

CASE

= Case Temperature in

PD = Power Dissipation in W

= Thermal Resistance (Case-to-Ambient)

= Thermal Resistance (Junction-to-Ambient)

= Thermal Resistance (Junction-to-Case)

Package

PLCC

C/W

Figure 14. Typical Output Rise Time vs. Load Capacitance, C

(at Maximum Ambient Operating Temperature)

Figure 15. Typical Output Valid Delay or Hold vs. Load
Capacitance, C

(at Maximum Ambient Operating Temperature)

150

125

100

 pF

RISE TIME (0.8V-2.0V) ns

= 3.0V

VALID OUTPUT DELAY OR HOLD ns

NOMINAL

150

125

100

= 3.0V

 pF

ADSP-2104/ADSP-2109

REV. 0

TEST CONDITIONS

Figure 16 shows voltage reference levels for ac measurements.

INPUT

OUTPUT

Figure 16. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)

Output Disable Time

Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The
output disable time (t

DIS

) is the difference of t

MEASURED

and

DECAY

, as shown in Figure 17. The time t

MEASURED

is the

interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage.

SPECIFICATIONS (ADSP-2104L/ADSP-2109L)

The decay time, t

DECAY

, is dependent on the capacitative load,

, and the current load, i

, on the output pin. It can be

approximated by the following equation:

DECAY

0.5 V

from which

DIS

= t

MEASURED

DECAY

is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.

Output Enable Time

Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (t

E NA

) is the interval from

when a reference signal reaches a high or low voltage level to
when the output has reached a specified high or low trip point,
as shown in Figure 17. If multiple pins (such as the data bus)
are enabled, the measurement value is that of the first pin to
start driving.

Figure 17. Output Enable/Disable

2.0V

1.0V

ENA

REFERENCE

SIGNAL

OUTPUT

DECAY

(MEASURED)

OUTPUT STOPS

DRIVING

OUTPUT STARTS

DRIVING

DIS

MEASURED

(MEASURED)

(MEASURED) 0.5V

(MEASURED) +0.5V

HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE
APPROXIMATELY 1.5V.

(MEASURED)

Figure 18. Equivalent Device Loading for AC Measurements
(Except Output Enable/Disable)

OUTPUT

PIN

50pF

ADSP-2104/ADSP-2109

REV. 0

GENERAL NOTES

Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.

TIMING NOTES

Switching characteristics specify how the processor changes its
signals. You have no control over this timing--circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use

TIMING PARAMETERS (ADSP-2104/ADSP-2109)

switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.

Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the
processor operates correctly with other devices.

MEMORY REQUIREMENTS

The table below shows common memory device specifications
and the corresponding ADSP-2104/ADSP-2109 timing
parameters, for your convenience.

Memory

ADSP-2104/ADSP-2109

Timing

Device

Timing

Parameter

Specification

Parameter

Definition

Address Setup to Write Start

ASW

A0A13, DMS, PMS Setup before WR Low

Address Setup to Write End

A0A13, DMS, PMS Setup before WR Deasserted

Address Hold Time

WRA

A0A13, DMS, PMS Hold after WR Deasserted

Data Setup Time

Data Setup before WR High

Data Hold Time

Data Hold after WR High

OE to Data Valid

RDD

RD Low to Data Valid

Address Access Time

A0A13, DMS, PMS, BMS to Data Valid

ADSP-2104/ADSP-2109

REV. 0

20 MHz

Parameter

Min

Max

Unit

Timing Requirement:
t

RDD

RD Low to Data Valid

A0A13, PMS, DMS, BMS to Data Valid

19.5

RDH

Data Hold from RD High

Switching Characteristic:

RD Pulse Width

CRD

CLKOUT High to RD Low

7.5

22.5

ASR

A0A13, PMS, DMS, BMS Setup before

2.5

RD Low

RDA

A0A13, PMS, DMS, BMS Hold after RD

3.5

Deasserted

RWR

RD High to RD or WR Low

Frequency Dependency

(CLKIN

20 MHz)

Parameter

Min

Max

Unit

Timing Requirement:
t

RDD

RD Low to Data Valid

0.5t

13 + w

A0A13, PMS, DMS, BMS to Data Valid

0.75t

18 + w

RDH

Data Hold from RD High

Switching Characteristic:
t

RD Pulse Width

0.5t

8 + w

CRD

CLKOUT High to RD Low

0.25t

+ 10

ASR

A0A13, PMS, DMS, BMS Setup before
RD Low

0.25t

RDA

A0A13, PMS, DMS, BMS Hold after RD
Deasserted

0.25t

RWR

RD High to RD or WR Low

0.5t

NOTE
w = wait states

CK.

TIMING PARAMETERS (ADSP-2104/ADSP-2109)

MEMORY READ

Figure 22. Memory Read

CLKOUT

A0 A13

DMS, PMS

BMS

RDH

RWR

ASR

CRD

RDD

RDA

ADSP-2104/ADSP-2109

REV. 0

Frequency Dependency

(CLKIN

20 MHz)

Parameter

Min

Max

Unit

Switching Characteristic:
t

Data Setup before WR High

0.5t

13 + w

Data Hold after WR High

0.25t

WR Pulse Width

0.5t

8 + w

WDE

WR Low to Data Enabled

ASW

A0A13, DMS, PMS Setup before WR Low

0.25t

DDR

Data Disable before WR or RD Low

0.25t

CWR

CLKOUT High to WR Low

0.25t

+ 10

A0A13, DMS, PMS, Setup before WR
Deasserted

0.75t

22 + w

WRA

A0A13, DMS, PMS Hold after WR
Deasserted

0.25t

WWR

WR High to RD or WR Low

0.5t

TIMING PARAMETERS (ADSP-2104/ADSP-2109)

MEMORY WRITE

20 MHz

Parameter

Min

Max

Unit

Switching Characteristic:
t

Data Setup before WR High

Data Hold after WR High

2.5

WR Pulse Width

WDE

WR Low to Data Enabled

ASW

A0A13, DMS, PMS Setup before

2.5

WR Low

DDR

Data Disable before WR or RD Low

2.5

CWR

CLKOUT High to WR Low

7.5

22.5

A0A13, DMS, PMS, Setup before WR

15.5

Deasserted

WRA

A0A13, DMS, PMS Hold after WR

3.5

Deasserted

WWR

WR High to RD or WR Low

Figure 23. Memory Write

CLKOUT

A0 A13

DMS, PMS

WDE

DDR

WWR

WRA

CWR

ASW

ADSP-2104/ADSP-2109

REV. 0

Frequency

13.824 MHz*

Dependency

Parameter

Min

Max

Min

Max

Unit

Timing Requirement:
t

SCK

SCLK Period

72.3

SCS

DR/TFS/RFS Setup before SCLK Low

SCH

DR/TFS/RFS Hold after SCLK Low

SCP

SCLK

Width

Switching Characteristic:
t

CLKOUT High to SCLK

OUT

18.1

33.1

0.25t

+ 15

SCDE

SCLK High to DT Enable

SCDV

SCLK High to DT Valid

TFS/RFS

OUT

Hold after SCLK High

TFS/RFS

OUT

Delay from SCLK High

SCDH

DT Hold after SCLK High

TDE

TFS (Alt) to DT Enable

TDV

TFS (Alt) to DT Valid

SCDD

SCLK High to DT Disable

RDV

RFS

(Multichannel, Frame Delay Zero)

to DT Valid

*Maximum serial port operating frequency is 13.824 MHz.

TIMING PARAMETERS (ADSP-2104/ADSP-2109)

SERIAL PORTS

Figure 24. Serial Ports

CLKOUT

SCLK

TFS

RFS

TFS

( ALTERNATE

FRAME MODE )

SCS

SCH

RFS

OUT

TFS

OUT

SCDV

SCDE

SCDH

SCDD

TDE

TDV

( MULTICHANNEL MODE,

FRAME DELAY 0 {MFD = 0} )

RDV

SCK

SCP

ADSP-2104/ADSP-2109

REV. 0

TIMING PARAMETERS (ADSP-2104L/ADSP-2109L)

MEMORY REQUIREMENTS

The table below shows common memory device specifications
and the corresponding ADSP-2104L/ADSP-2109L timing
parameters, for your convenience.

GENERAL NOTES

TIMING NOTES

ADSP-2104L/ADSP-2109L

Memory Specification

Timing Parameter

Timing Parameter Definition

Address Setup to Write Start

ASW

A0A13, DMS, PMS Setup before WR Low

Address Setup to Write End

A0A13, DMS, PMS Setup before WR Deasserted

Address Hold Time

WRA

A0A13, DMS, PMS Hold after WR Deasserted

Data Setup Time

Data Setup before WR High

Data Hold Time

Data Hold after WR High

OE to Data Valid

RDD

RD Low to Data Valid

Address Access Time

A0A13, DMS, PMS, BMS to Data Valid

ADSP-2104/ADSP-2109

REV. 0

TIMING PARAMETERS (ADSP-2104L/ADSP-2109L)

SERIAL PORTS

Frequency

13.824 MHz

Dependency

Parameter

Min

Max

Min

Max

Unit

Timing Requirement:
t

SCK

SCLK Period

72.3

SCS

DR/TFS/RFS Setup before SCLK Low

SCH

DR/TFS/RFS Hold after SCLK Low

SCP

SCLK

Width

Switching Characteristic:
t

CLKOUT High to SCLK

out

18.1

33.1

0.25t

+ 15

SCDE

SCLK High to DT Enable

SCDV

SCLK High to DT Valid

TFS/RFS

out

Hold after SCLK High

TFS/RFS

out

Delay from SCLK High

SCDH

DT Hold after SCLK High

TDE

TFS (alt) to DT Enable

TDV

TFS (alt) to DT Valid

SCDD

SCLK High to DT Disable

RDV

RFS

(Multichannel, Frame Delay Zero)

to DT Valid

CLKOUT

SCLK

TFS

RFS

TFS

( ALTERNATE

FRAME MODE )

SCS

SCH

RFS

OUT

TFS

OUT

SCDV

SCDE

SCDH

SCDD

TDE

TDV

( MULTICHANNEL MODE,

FRAME DELAY 0 {MFD = 0} )

RDV

SCK

SCP

Figure 30. Serial Ports

ADSP-2104/ADSP-2109

REV. 0

PIN CONFIGURATIONS

68-Lead PLCC

PLCC

Pin

Number Name

A12

A13

PMS

DMS

BMS

XTAL

CLKIN

CLKOUT

DT0

TFS0

RFS0

GND

DR0

SCLK0

PLCC

Pin

Number Name

IRQ2

RESET

GND

A10

A11

PLCC

Pin

Number Name

D11

GND

D12

D13

D14

D15

D16

D17

D18

GND

D19

D20

D21

D22

D23

MMAP

PLCC

Pin

Number Name

(DT1)

IRQ1

(TFS1)

IRQ0

(RFS1)

(DR1)

SCLK1

D10

23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

GND

D18

D15

D14

D12

D17

D10

D11

68 67 66 65 64 63 62

PIN 1
IDENTIFIER

TOP VIEW

(PINS DOWN)

SCLK1

(DR1)

IRQ0

(RFS1)

GND

D19

D20

D21

D22

D23

MMAP

IRQ2

RESET

IRQ1

(TFS1)

(DT1)

SCLK0

DR0

ADSP-2104
ADSP-2104L
ADSP-2109
ADSP-2109L

GND

RFS0

TFS0

DT0

GND

A10

A11

A12

A13

PMS

D13

D16

DMS

XTAL

CLKIN

CLKOUT

BMS

Part Number ADSP2104