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Part Number ADP3405

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REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
ADP3405
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site:www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
FEATURES
Handles all GSM Baseband Power Management
Functions
Four LDOs Optimized for Specific GSM Subsystems
Charges Li-Mn Coin Cell for Real-Time Clock
Charge Pump and Logic Level Translators for 3 V and 5 V
GSM SIM Modules
Narrow Body 4.4 mm 28-Lead TSSOP Package
APPLICATIONS
GSM/DCS/PCS Handsets
TeleMatic Systems
ICO/Iridium Terminals
GSM Power Management System
FUNCTIONAL BLOCK DIAGRAM
DIGITAL
LDO
VCC
VRTC
VTCXO
PWRONKEY
ROWX
PWRONIN
RESET
ANALOGON
POWER-UP
SEQUENCING
AND
PROTECTION
LOGIC
ADP3405
VBAT
REFOUT
AGND
VCCA
RESCAP
CHRON
SIMBAT
CAP+
CAP
SIMPROG
SIMON
SIMGND
RESETIN
CLKIN
DATAIO
CHARGE
PUMP
LOGIC LEVEL
TRANSLATION
BUFFER
REF
+
I/O
RST
CLK
VSIM
RTC LDO
XTAL OSC
LDO
ANALOG
LDO
DGND
GENERAL DESCRIPTION
The ADP3405 is a multifunction power management system IC
optimized for GSM cell phones. The wide input voltage range of
3.0 V to 7.0 V makes the ADP3405 ideal for both single cell Li-Ion
and three cell NiMH designs. The current consumption of the
ADP3405 has been optimized for maximum battery life, featuring
a ground current of only 150
µA when the phone is in standby
(digital LDO, and SIM card supply active). An undervoltage lock-
out (UVLO) prevents the startup when there is not enough energy
in the battery. All four integrated LDOs are optimized to power
one of the critical sub-blocks of the phone. Their novel anyCAP
®
architecture requires only very small output capacitors for stability,
and the LDOs are insensitive to the capacitors' equivalent series
resistance (ESR). This makes them stable with any capacitor,
including ceramic (MLCC) types for space-restricted applications.
A step-up converter is implemented to supply both the SIM
module and the level translation circuitry to adapt logic signals
for 3 V and 5 V SIM modules. Sophisticated controls are avail-
able for power-up during battery charging, keypad interface, and
charging of an auxiliary backup battery for the real-time clock.
These allow an easy interface between ADP3405, GSM proces-
sor, charger, and keypad. Furthermore, a reset circuit and a
thermal shutdown function have been implemented to support
reliable system design.
anyCAP is a registered trademark of Analog Devices, Inc.
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ADP3405­SPECIFICATIONS
(­20 C
T
A
+85 C, VBAT = 3 V to 7 V, C
VBAT
= C
SIMBAT
= C
VSIM
= 10 F, C
VCC
= C
VCCA
= 2.2 F,
C
VRTC
= 0.1 F, C
VTCXO
= 0.22 F, C
VCAP
= 0.1 F, min. loads applied on all outputs, unless
otherwise noted.)
ELECTRICAL CHARACTERISTICS
1
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SHUTDOWN SUPPLY CURRENT
I
BAT
VBAT = Low (UVLO Low)
VBAT = 2.7 V
3
20
µA
VBAT = High (UVLO High)
VBAT
= 3.6 V, VRTC On
12
30
µA
OPERATING GROUND CURRENT
I
GND
VCC and VRTC On
Minimum Loads, VBAT
= 3.6 V
100
140
µA
VCC, VRTC and VSIM On
Minimum Loads, VBAT
= 3.6 V
150
240
µA
All LDOs and VSIM On
Minimum Loads, VBAT
= 3.6 V
260
400
µA
All LDOs and VSIM On
Maximum Loads, VBAT
= 3.6 V
15
mA
UVLO CHARACTERISTICS
UVLO On Threshold
VBAT
UVLO
3.2
3.3
V
UVLO Hysteresis
200
mV
INPUT CHARACTERISTICS
Input High Voltage
V
IH
PWRONIN and ANALOGON
2
V
PWRONKEY
0.7 VBAT
V
Input Low Voltage
V
IL
PWRONIN and ANALOGON
0.4
V
PWRONKEY
0.3 VBAT
V
PWRONKEY INPUT PULL-UP
RESISTANCE TO VBAT
15
20
25
k
CHRON CHARACTERISTICS
CHRON Threshold
V
T
2.38
2.48
2.58
V
CHRON Hysteresis Resistance
R
IN
2.38 < CHRON < V
T
108
125
138
k
CHRON Input Bias Current
I
B
CHRON > V
T
0.5
µA
ROWX CHARACTERISTICS
ROWX Output Low Voltage
V
OL
PWRONKEY = Low
0.4
V
I
OL
= 200
µA
ROWX Output High Leakage
I
IH
PWRONKEY = High
1
µA
Current
V(ROWX) = 5 V
SHUTDOWN
Thermal Shutdown Threshold
2
Junction Temperature
160
ºC
Thermal Shutdown Hysteresis
Junction Temperature
35
ºC
DIGITAL LDO (VCC)
Output Voltage
VCC
Line, Load, Temp
2.710
2.765 2.820
V
Line Regulation
DVCC
3 V < VBAT < 7 V, Min Load
2
mV
Load Regulation
DVCC
50
µA < I
LOAD
< 100 mA,
15
mV
VBAT = 3.6 V
Output Capacitor
3
C
O
2.2
µF
Dropout Voltage
V
DO
V
O
= V
INITIAL
­ 100 mV
215
mV
I
LOAD
= 100 mA
ANALOG LDO (VCCA)
Output Voltage
VCCA
Line, Load, Temp
2.710
2.765 2.820
V
Line Regulation
DVCCA
3 V < VBAT < 7 V, Min Load
2
mV
Load Regulation
DVCCA
200
µA < I
LOAD
< 130 mA,
15
mV
VBAT = 3.6 V
Output Capacitor
3
C
O
2.2
µF
Dropout Voltage
V
DO
V
O
= V
INITIAL
­ 100 mV
215
mV
I
LOAD
= 130 mA
Ripple Rejection
DVBAT/
f = 217 Hz (t = 4.6 ms)
65
70
dB
DVCCA
VBAT = 3.6 V
Output Noise Voltage
V
NOISE
f = 10 Hz to 100 kHz
75
µV rms
I
LOAD
= 130 mA, VBAT = 3.6 V
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ADP3405
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
CRYSTAL OSCILLATOR LDO (VTCXO)
Output Voltage
VTCXO
Line, Load, Temp
2.710
2.765
2.820
V
Line Regulation
VTCXO
3 V < VBAT < 7 V, Min Load
2
mV
Load Regulation
VTCXO
100
µA < I
LOAD
< 5 mA,
1
mV
VBAT = 3.6 V
Output Capacitor
3
C
O
0.22
µF
Dropout Voltage
V
DO
V
O
= V
INITIAL
­ 100 mV
150
mV
I
LOAD
= 5 mA
Ripple Rejection
VBAT/
f = 217 Hz (t = 4.6 ms),
65
72
dB
VTCXO
VBAT = 3.6 V
Output Noise Voltage
V
NOISE
f = 10 Hz to 100 kHz
80
µV rms
I
LOAD
= 5 mA, VBAT = 3.6 V
VOLTAGE REFERENCE (REFOUT)
Output Voltage
V
REFOUT
Line, Load, Temp
1.192
1.210
1.228
V
Line Regulation
V
REFOUT
3 V < VBAT < 7 V, Min Load
2
mV
Load Regulation
V
REFOUT
0
µA < I
LOAD
< 50
µA,
0.5
mV
VBAT = 3.6 V
Ripple Rejection
VBAT/
f = 217 Hz (t = 4.6 ms),
65
75
dB
V
REFOUT
VBAT = 3.6 V
Maximum Capacitive Load
C
O
100
pF
Output Noise Voltage
V
NOISE
f = 10 Hz to 100 kHz
40
µV rms
VBAT = 3.6 V
REAL-TIME CLOCK LDO/
BATTERY CHARGER (VRTC)
Maximum Output Voltage
VRTC
I
LOAD
10 µA
2.810
2.850
2.890
V
Current Limit
I
MAX
3.050 V < VBAT < 7 V
175
µA
Off Reverse Leakage Current
I
L
2.0 V < VBAT < UVLO
1
µA
Dropout Voltage
V
DO
V
O
= V
INITIAL
­ 10 mV
170
mV
I
LOAD
= 10
µA
SIM CHARGE PUMP (VSIM)
Output Voltage for 5 V SIM Modules
VSIM
0 mA
I
LOAD
10 mA
4.70
5.00
5.30
V
SIMPROG = High
Output Voltage for 3 V SIM Modules
VSIM
0 mA
I
LOAD
6 mA
2.82
3.00
3.18
V
SIMPROG = Low
GSM/SIM LOGIC TRANSLATION
(GSM INTERFACE)
Input High Voltage (SIMPROG, SIMON,
V
IH
VCC ­ 0.6
V
RESETIN, CLKIN)
Input Low Voltage (SIMPROG, SIMON,
V
IL
0.6
V
RESETIN, CLKIN)
DATAIO
V
IL
V
OL
(I/O) = 0.4 V,
0.230
V
I
OL
(I/O) = 1 mA
V
OL
(I/O) = 0.4 V,
0.335
V
I
OL
(I/O ) = 0 mA
V
IH
, V
OH
I
IH
, I
OH
=
±10 µA
VCC
­ 0.4
V
I
IL
V
IL
= 0 V
­0.9
mA
V
OL
V
IL
(I/O) = 0.4 V
0.420
V
DATAIO Pull-Up Resistance to VCC
R
IN
16
20
24
k
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ADP3405
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Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SIM INTERFACE
VSIM = 5 V
RST
V
OL
I = +200
µA
0.6
V
RST
V
OH
I = ­20
µA
VSIM
­ 0.7
V
CLK
V
OL
I = +200
µA
0.5
V
CLK
V
OH
I = ­20
µA
0.7
VSIM
V
I/O
V
IL
0.4
V
I/O
V
IH
, V
OH
I
IH
, I
OH
=
±20 µA
VSIM ­ 0.4
V
I/O
I
IL
V
IL
= 0 V
­0.9
mA
I/O
V
OL
I
OL
= +1 mA
0.4
V
DATAIO
0.23 V
VSIM = 3 V
RST
V
OL
I = +200
µA
0.2
VSIM
V
RST
V
OH
I = ­20
µA
0.8
VSIM
V
CLK
V
OL
I = +20
µA
0.2 VSIM
V
CLK
V
OH
I = ­20
µA
0.7
VSIM
V
I/O
V
IL
0.4
V
I/O
V
IH
, V
OH
I
IH
, I
OH
=
±20 µA
VSIM ­ 0.4
V
I/O
I
IL
V
IL
= 0 V
­0.9
mA
I/O
V
OL
I
OL
= 1 mA
0.4
V
DATAIO
0.23 V
I/O Pull-Up Resistance to VSIM
R
IN
8
10
12
k
Max Frequency (CLK)
f
MAX
C
L
= 30 pF
5
MHz
Prop Delay (CLK)
t
D
30
50
ns
Output Rise/Fall Times (CLK)
t
R
, t
F
C
L
= 30 pF
9
18
ns
Output Rise/Fall Times (I/O, RST)
t
R
, t
F
C
L
= 30 pF
1
µs
Duty Cycle (CLK)
D
D CLKIN = 50%
47
53
%
f = 5 MHz
RESET GENERATOR (RESET)
Output High Voltage
V
OH
I
OH
= ­15
µA
VCC ­ 0.3
V
Output Low Voltage
V
OL
I
OL
= ­15
µA
0.3
V
Delay Time Per Unit Capacitance
t
D
1.0
ms/nF
Applied to RESCAP Pin
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods .
2
This feature is intended to protect against catastrophic failure of the device. Maximum allowed operating junction temperature is 125
°C. Operation beyond 125°C
could cause permanent damage to the device.
3
Required for stability.
Specifications subject to change without notice.
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ADP3405
­5­
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ABSOLUTE MAXIMUM RATINGS
*
Voltage on Any Pin with Respect
to Any GND Pin . . . . . . . . . . . . . . . . . . . . . . ­0.3 V, +10 V
Voltage on Any Pin May Not Exceed VBAT,
with the Following Exceptions: VRTC, VSIM,
CAP+, PWRONIN, I/O, CLK, RST
Storage Temperature Range . . . . . . . . . . . . ­65
°
C to +150
°
C
Operating Temperature Range . . . . . . . . . . . ­20
°
C to +85
°
C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125
°
C
JA
, Thermal Impedance (TSSOP-28) . . 4-Layer Board 68
°
C/W
JA
, Thermal Impedance (TSSOP-28) . . 6-Layer Board 62
°
C/W
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300
°
C
*This is a stress rating only, operation beyond these limits can cause the device to
be permanently damaged.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3405 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ADP3405
CHRON
ROWX
PWRONIN
ANALOGON
PWRONKEY
VCC
VBAT
RESCAP
DGND
VTCXO
RESET
AGND
VCCA
REFOUT
VRTC
CAP­
SIMBAT
DATAIO
RESETIN
CLKIN
SIMGND
CAP+
VSIM
CLK
SIMON
I/O
RST
SIMPROG
TSSOP-28
(Not To Scale)
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Function
1
RESCAP
Reset Delay Timing Cap
2
DGND
Digital Ground
3
VTCXO
Crystal Oscillator Low Dropout
Regulator
4
RESET
Main Reset
5
REFOUT
Reference Output
6
VCCA
Analog Low Dropout Regulator
7
AGND
Analog Ground
8
VBAT
Battery Input Voltage
9
VCC
Digital Low Dropout Regulator
10
PWRONKEY
Power-On/-Off Key
11
ANALOGON
VTCXO Enable
12
PWRONIN
Power-On/-Off Signal from
Microprocessor
13
ROWX
Microprocessor Keyboard Output
14
CHRON
Charger On/Off Input
15
VRTC
Real-Time Clock Supply/Coin
Cell Battery Charger
16
CAP­
Negative Side of Boost Capacitor
17
SIMBAT
Battery Input for the SIM
Charge Pump
18
DATAIO
Non-Level-Shifted Bidirectional
Data I/O
19
RESETIN
Non-Level-Shifted SIM Reset
20
CLKIN
Non-Level-Shifted Clock
21
SIMGND
Charge Pump Ground
22
I/O
Level-Shifted Bidirectional SIM
Data Input/Output
23
RST
Level-Shifted SIM Reset
24
SIMPROG
VSIM Programming:
Low = 3 V, High = 5 V
25
SIMON
VSIM Enable
26
CLK
Level-Shifted SIM Clock
27
VSIM
SIM Supply
28
CAP+
Positive Side of Boost Capacitor
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Option
ADP3405ARU ­20
°
C to +85
°
C
28-Lead TSSOP
RU-28
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ADP3405
­6­
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Table I. LDO Control Logic
Inputs
Outputs
UVLO
CHRON
PWRONKEY
PWRONIN
ANALOGON
VRTC
VCC
VCCA
REFOUT
VTCXO
L
X
X
X
X
Off
Off
Off
Off
Off
H
H
X
X
X
On
On
On
On
On
H
X
L
X
X
On
On
On
On
On
H
L
H
L
X
On
Off
Off
Off
Off
H
L
H
H
L
On
On
Off
Off
Off
H
L
H
H
H
On
On
On
On
On
X = Don't care
Bold denotes the active control signal.
CHARGER
ON
THRESHOLD
OVER
TEMP
EN
REF
BUFFER
VBAT
VREF
EN
GND
PG
OUT
DIGITAL LDO
VCC
2.45V
DGND
VRTC
2.45V
VBAT
EN
GND
OUT
VBAT
VREF
EN
GND
OUT
POWER GOOD
RTC LDO
XTAL OSC LDO
ANALOG LDO
VBAT
VREF
EN
GND
OUT
REFOUT
AGND
VCCA
2.765V
VTCXO
2.765V
+
1.210V
UVLO
ADJ
UVLO
VBAT
PWRONKEY
ROWX
PWRONIN
RESCAP
RESET
CHRON
ANALOGON
SIMBAT
CAP+
CAP­
SIMPROG
SIMON
SIMGND
RESETIN
CLKIN
DATAIO
CHARGE
PUMP
LOGIC
LEVEL
TRANSLATION
VSIM
RST
CLK
I/O
EN
3V/5V
20k
EN
ADP3405
RESET
GENERATOR
GND
Figure 1. Functional Block Diagram
Table II. VSIM Control Logic
Inputs
Outputs
VCC
RESET
SIMON
SIMPROG
VSIM
Off
L
X
X
Off
On
L
X
X
Off
On
H
L
X
Off
On
H
H
L
3 V
On
H
H
H
5 V
X = Don't care
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ADP3405
­7­
REV. 0
VBAT ­ V
350
300
50
3
7
4
I
GND

­
A
5
6
250
200
150
PWRONIN, SIMON, AND ANALOGON
PWRONIN AND SIMON
PWRONIN
100
TPC 1. Ground Current vs. Battery Voltage
LOAD CURRENT ­ mA
0
140
20
40
60
80
100
120
0
DROPOUT VOLTAGE
­
mV
140
80
60
40
20
120
100
VCC
VCCA
TPC 2. VCC, VCCA Dropout Voltage vs. Load Current
LOAD CURRENT ­ mA
70
0
DROPOUT VOLTAGE
­
mV
40
30
20
10
60
50
0
1
2
3
4
5
TPC 3. VTCXO Dropout Voltage vs. Load Current
+25 C
20 C
VRTC ­ V
300
0
0
3
0.5
I
RTC

­
A
1.0
1.5
2.0
2.5
150
100
50
250
200
+85 C
TPC 4. RTC I/V Characteristic
VOLTAGE
TIME ­ 100 s/DIV
VBAT 100mV/DIV
3.2
3.0
MLCC CAPS
VCC 10mV/DIV
VCCA 10mV/DIV
VTCXO 10mV/DIV
TPC 5. Line Transient Response, Maximum Loads
VOLTAGE
TIME ­ 100 s/DIV
3.2
3.0
MLCC CAPS
VBAT (100mV/DIV)
VCC (10mV/DIV)
VCCA (10mV/DIV)
VTCXO (10mV/DIV)
TPC 6. Line Transient Response, Minimum Loads
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ADP3405
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VOLTAGE
­
20mV/DIV
TIME ­ 200 s/DIV
I
LOAD
I = 100mA
MLCC CAPS
VCC
I = 200 A
TPC 7. VCC Load Step
VOLTAGE
­
20mV/DIV
TIME ­ 100 s/DIV
I = 50 A
I
LOAD
I = 130mA
MLCC CAPS
VCCA
TPC 8. VCCA Load Step
VOLTAGE
TIME ­ 50 s/DIV
PWRONIN AND ANALOGON (2V/DIV)
VCCA (100mV/DIV)
VTCXO (100mV/DIV)
VCC (100mV/DIV)
TPC 9. Turn-On Transients, Minimum Loads
VOLTAGE
TIME ­ 50 s/DIV
PWRONIN AND ANALOGON (2V/DIV)
VCCA (100mV/DIV)
REFOUT (100mV/DIV)
VCC (100mV/DIV)
VTCXO (100mV/DIV)
TPC 10. Turn-On Transients, Maximum Loads
FREQUENCY ­ Hz
80
70
0
4
100k
10
RIPPLE REJECTION
­
dB
100
1k
10k
60
50
10
40
30
20
VTCXO
VCCA
VCC
REFOUT
MLCC OUTPUT CAPS
VBAT = 3.2V, FULL LOADS
TPC 11. Ripple Rejection vs. Frequency
VBAT ­ V
80
0
2.5
3.3
2.6
RIPPLE REJECTION
­
dB
2.7
2.8
2.9
3.0
3.1
3.2
70
40
30
20
10
60
50
FREQUENCY = 217Hz
MAX LOADS
VTCXO
VCCA
REFOUT
VCC
TPC 12. Ripple Rejection vs. Battery Voltage
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ADP3405
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
CHRON
ROWX
PWRONIN
ANALOGON
VCC
VBAT
VTCXO
RESET
AGND
VCCA
REFOUT
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADP3405
VRTC
CAP­
PWRONKEY
RESCAP
DGND
TSSOP-28
DIGITAL AND
SIM GND
ANALOG GND
SIM PINS
OF
GSM PROCESSOR
GSM
PROCESSOR
RST TO SIM CARD
I/O TO SIM CARD
CLK TO SIM CARD
10 F
100nF
BACK-UP
COIN CELL
100nF
GSM
PROCESSOR
CHARGER
INPUT
1 LI-ION
OR
3 NIMH
10 F
100nF
100nF
2.2 F
0.22 F
10
2.2 F
R1
R2
10 F
SIMBAT
DATAIO
RESETIN
CLKIN
SIMGND
CAP+
VSIM
CLK
SIMON
I/O
RST
SIMPROG
Figure 2. Typical Application Circuit
FREQUENCY ­ Hz
600
500
0
10
100k
100
VOLTAGE SPECTRAL NOISE DENSITY
­
nV/ Hz
1k
10k
400
300
200
100
FULL LOAD
MLCC CAPS
VCCA
TCXO
REF
TPC 13. Output Noise Density
THEORY OF OPERATION
The ADP3405 is a power management chip optimized for use with
the AD20msp425 GSM baseband chipsets in handset applications.
Figure 1 shows a functional block diagram of the ADP3405.
The ADP3405 contains several blocks:
· Four Low Dropout Regulators (Digital, Analog, Crystal
Oscillator, Real-Time Clock)
· Reset Generator
· Buffered Precision Reference
· SIM Interface Logic Level Translation (3 V/5 V)
· SIM Voltage Supply
· Power-On/-Off Logic
· Undervoltage Lockout
These functions have traditionally been done as either a discrete
implementation or a custom ASIC design. ADP3405 combines
the benefits of both worlds by providing an integrated standard
product solution where every block is optimized to operate in a
GSM environment while maintaining a cost-competitive solution.
Figure 2 shows the external circuitry associated with the ADP3405.
Only a few support components, mainly decoupling capacitors,
are required.
Input Voltage
The input voltage range for ADP3405 is 3 V to 7 V and optimized
for a single Li-Ion cell or three NiMH/NiCd cells. The thermal
impedance (
JA
) of the ADP3405 is 62
°
C/W for 6-layer boards.
The charging voltage for a high capacity NiMH cell can be as high
as 5.5 V. Power dissipation should be calculated at maximum
ambient temperatures and battery voltage in order not to exceed
the 125
°
C maximum allowable junction temperature. Figure 3
shows the maximum total LDO output current as a function of
ambient temperature and battery voltage.
However, high battery voltages normally occur only when the
battery is being charged and the handset is not in conversation
mode. In this mode there is a relatively light load on the LDOs.
A fully charged Li-Ion battery is 4.25 V, where the LDOs deliver
the maximum 240 mA up to the max 85
°
C ambient temperature.
background image
ADP3405
­10­
REV. 0
AMBIENT TEMPERATURE ­ C
300
0
20
0
TOTAL LDO CURRENT
­
mA
20
40
60
80
250
200
150
100
50
85
VBAT = 5.5V
VBAT = 7V
VBAT = 6V
VBAT = 5V
6-LAYER BOARD
JA
= 62 C/W
Figure 3. Total LDO Load Current vs. Temperature and VBAT
Low Dropout Regulators (LDOs)
The ADP3405 high-performance LDOs are optimized for
their given functions by balancing quiescent current, dropout
voltage, line/load regulation, ripple rejection, and output
noise. 2.2
µF tantalum or MLCC ceramic capacitors are
recommended for use with the digital and analog LDOs, and
0.22
µF for the TCXO LDO.
Digital LDO (VCC)
The digital LDO (VCC) supplies all the digital circuitry in the
handset (baseband processor, baseband converter, external
memory, display, etc.). The LDO has been optimized for very
low quiescent current (30
µA maximum) at light loads as this
LDO is on at all times. This is due to both the structure of GSM
and a new clocking scheme used in the AD20msp425. Figure 4
shows how the digital current varies as a function of time.
TIME
POWER
~50mA
MICROPROCESSOR
START
MICROPROCESSOR
STOP
~2ms
~200 A
0.5s TO 2s
Figure 4. Digital Power as a Function of Time
Analog LDO (VCCA)
This LDO has the same features as the digital LDO. It has further-
more been optimized for good low frequency ripple rejection for use
with analog sections in order to reject the ripple coming from the RF
power amplifier. VCCA is rated to 130 mA load which is sufficient
to supply the complete analog section of a baseband converter such
as the AD6421/AD6425, including a 32
earpiece. The analog
LDO and the TCXO LDO can be controlled by ANALOGON.
TCXO LDO (VTCXO)
The TCXO LDO is intended as a supply for the temperature-
compensated crystal oscillator, which needs its own ultralow noise
supply. The output current is rated to 5 mA for the TCXO LDO.
RTC LDO (VRTC)
The RTC LDO charges a rechargable coin cell to run the real-
time clock module. It has been targeted to charge Manganese
Lithium batteries such as the ML series (ML621/ML1220)
from Sanyo. The ML621 has a small physical size (6.8 mm
diameter) and a nominal capacity of 2.5 mAh, which yields
about 250 hours of backup time.
Figure 5 shows the use of VRTC with the Enhanced GSM
Processor which is a part of the AD20msp425 chipset.
ADP3405
ENHANCED
GSM PROCESSOR
(AD20msp425)
VRTC
PWRON
PWRONIN
COIN
CELL
VRTC
RTC
MODULE
Figure 5. Connecting VRTC and PWRONIN to the
AD20msp425 Chipset
The ADP3405 supplies current both for charging the coin cell and
for the RTC module when the digital supply is off. The nominal
charging voltage of 2.85 V ensures charging down to a main
battery voltage of 3.0 V. The inherent current limit of VRTC
ensures long cell life while the precise output voltage regulation
charges the cell to more than 90% of its capacity. In addition, it
features a very low quiescent current (10
µA) since this LDO is
running all the time, even when the handset is switched off. It also
has reverse current protection with low leakage which is needed
when the main battery is removed and the coin cell supplies the
RTC module.
The RTC module has a built-in alarm which, when it expires,
will pull PWRONIN high, allowing an alarm function even if
the handset is switched off.
Reference Output (REFOUT)
The reference output is a low-noise, high-precision reference
with a guaranteed accuracy of 1.5% over temperature. The
reference can be fed to the baseband converter, such as the
AD6425, improving the absolute accuracy of the converters
from 5% to 1.5%. This significantly reduces calibration time
needed for the baseband converter during production.
SIM Interface
The SIM interface generates the needed SIM voltage--either 3 V
or 5 V, dependent on SIM type, and also performs the needed
logic level translation. Quiescent current is low, as the SIM card
will be powered all the time. Note that DATAIO and I/O have
integrated pull-up resistors as shown in Figure 6. See Table II for
the control logic of the charge pump output, VSIM.
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ADP3405
­11­
REV. 0
RESETIN
CLKIN
DATAIO
RST
CLK
I/O
LEVEL
SHIFT
VCC
VSIM
ADP3405
LEVEL
SHIFT
VCC
VCC
VSIM
VSIM
Figure 6. Schematic for Level Translators
Power-On/-Off
ADP3405 handles all issues regarding power-on/-off of the hand-
set. It is possible to turn on the ADP3405 in three different ways:
· Pulling PWRONKEY low
· Pulling PWRONIN high
· CHRON exceeds threshold
Pulling PWRONKEY key low is the normal way of turning on the
handset. This will turn on all the LDOs as long as PWRONKEY is
held low. The microprocessor then starts and pulls PWRONIN
high after which PWRONKEY can be released. PWRONIN going
high will also turn on the handset. This is the case when the alarm
in the RTC module expires.
An external charger can also turn on the phone. The turn-on
threshold and hysteresis can be programmed via external resistors
to allow full flexibility with any external charger and battery chem-
istry. These resistors are referred to as R1 and R2 in Figure 2.
Undervoltage Lockout (UVLO)
The UVLO function in the ADP3405 prevents startup when the
initial voltage of the main battery is below the 3.0 V threshold.
If the battery is this low with no load, there will be little or no
capacity left. When the battery is greater than 3.0 V, as with the
insertion of a fresh battery, the UVLO comparator trips, the
RTC LDO is enabled, and the threshold is reduced to 2.9 V.
This allows the handset to start normally until the battery volt-
age decays to 2.9 V open circuit. Once the 3.0 V threshold is
exceeded, the RTC LDO is enabled. If, however, the backup
coin cell is not connected, or is damaged or discharged below
1.5 V, the RTC LDO will not start on its own. In this situation,
the RTC LDO will be started by enabling the VCC LDO.
Once the system is started, i.e., the phone is turned on and the
VCC LDO is up and running, the UVLO function is entirely
disabled. The ADP3405 is then allowed to run down to very low
battery voltages, typically around 2 V. The battery voltage is
normally monitored by the microprocessor and usually shuts the
phone off at around 3.0 V.
If the phone is off, i.e., the VCC LDO is off, and the battery
voltage drops below 2.9 V, the UVLO circuit disables startup
and the RTC LDO. This is implemented with very low quies-
cent current, typically 3
µA, to protect the main battery against
any damage. NiMH batteries can reverse polarity if the 3-cell
battery voltage drops below 3.0 V and a current of more than
about 40
µA continues to flow. Lithium ion batteries will lose
their capacity, although the built-in safety circuits normally
present in these cells will most likely prevent any damage.
RESET
ADP3405 contains reset circuitry that is active both at power-up
and at power-down. RESET is held low at power-up. An inter-
nal power-good signal starts the reset delay. The delay is set by
an external capacitor on RESCAP:
t
ms
nF
C
RESET
RESCAP
=
×
1 0
.
A 100 nF capacitor will produce a 100 ms reset time. At power-off,
RESET will be kept low to prevent any spurious microprocessor
starts. The current capability of RESET is low (a few hundred nA)
when VCC is off, to minimize power consumption. Therefore,
RESET should only be used to drive a single CMOS input. When
VCC is on, RESET will drive about 15
µA.
Overtemperature Protection
The maximum die temperature for ADP3405 is 125
°
C. If the die
temperature exceeds 160
°C, the ADP3405 will disable all the
LDOs except the RTC LDO, which has very limited current capa-
bilities. The LDOs will not be re-enabled before the die tempera-
ture is below 125
°
C, regardless of the state of PWRONKEY,
PWRONIN, and CHRON. This ensures that the handset will
always power-off before the ADP3405 exceeds its absolute maxi-
mum thermal ratings.
APPLICATIONS INFORMATION
Input Capacitor Selection
For the input voltage, VBAT, of the ADP3405, a local bypass
capacitor is recommended. Use a 5
µF to 10 µF, low ESR capaci-
tor. Multilayer ceramic chip capacitors provide the best combina-
tion of low ESR and small size, but may not be cost-effective. A
lower cost alternative may be to use a 5
µF to 10 µF tantalum
capacitor with a small (1
µF to 2 µF) ceramic in parallel.
LDO Capacitor Selection
The performance of any LDO is a function of the output capaci-
tor. The digital and analog LDOs require a 2.2
µF capacitor and
the TCXO LDO requires a 0.22
µF capacitor. Larger values
may be used, but the overshoot at startup will increase slightly.
If a larger output capacitor is desired, be sure to check that the
overshoot and settling time are acceptable for the application.
All the LDOs are stable with a wide range of capacitor types and
ESR due to Analog Devices' anyCAP technology. The ADP3405
is stable with extremely low ESR capacitors (ESR ~ 0), such as
multilayer ceramic capacitors, but care should be taken in their
selection. Note that the capacitance of some capacitor types shows
wide variations over temperature or with dc voltage. A good quality
dielectric, X7R or better, is recommended.
The RTC LDO has a rechargeable coin cell or an electric double-
layer capacitor as a load, but an additional 0.1
µF ceramic capaci-
tor is recommended for stability and best performance.
Charge Pump Capacitor Selection
For the input (SIMBAT) and output (VSIM) of the SIM charge
pump, use 10
µF low ESR capacitors. The use of low ESR capaci-
tors improves the noise and efficiency of the SIM charge pump.
Multilayer ceramic chip capacitors provide the best combination of
low ESR and small size but may not be cost-effective. A lower cost
alternative may be to use a 10
µF tantalum capacitor with a small
(1
µF to 2 µF) ceramic capacitor in parallel.
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­12­
REV. 0
C02376­2.5­4/01(0)
PRINTED IN U.S.A.
ADP3405
For the lowest ripple and best efficiency, use a 0.1
µF, ceramic
capacitor for the charge pump flying capacitor (CAP+ and CAP­).
A good quality dielectric, such as X7R is recommended.
Setting the Charger Turn-On Threshold
The ADP3405 can be turned on when the charger input exceeds
a programmable threshold voltage. The charger's threshold and
hysteresis are set by selecting the values for R1 and R2 shown in
Figure 2.
The turn-on threshold for the charger is calculated using:
V
R
R
R
R
R
V
CHR
HYS
HYS
T
=
+
×
×




+
×
2
2
1
1
Where V
T
is the CHRON threshold voltage and R
HYS
is the
CHRON hysteresis resistance.
The hysteresis is determined using:
V
V
R
R
HYS
T
HYS
=
× 1
Combining the above equations and solving for R1 and R2 gives
the following formulas:
R
R
V
V
HYS
T
HYS
1
=
×
R
R
R
V
V
R
R
HYS
CHR
T
HYS
2
1
1
1
=
×
-




×
-
Example: R1 = 10 k
and R2 = 30.2 k gives a charger thresh-
old (not counting the drop in the power Schottky diode) of
3.5 V
± 160 mV with a 200 mV ± 30 mV hysteresis.
Charger Diode Selection
The diode shown in Figure 2 is used to prevent the battery from
discharging into the charger turn-on setting resistors, R1 and R2.
A Schottky diode is recommended to minimize the voltage differ-
ence from the charger to the battery and the power dissipation.
Choose a diode with a current rating high enough to handle both
the battery charging current and the current the ADP3405 will
draw if powered up during charging. The battery charging current
is dependent on the battery chemistry and the charger circuit.
The ADP3405 current will be dependent on the loading.
Printed Circuit Board Layout Considerations
Use the following general guidelines when designing printed
circuit boards:
1. Split the battery connection to the VBAT and SIMBAT
pins of the ADP3405. Use separate traces for each connection
and locate the input capacitors as close to the pins as possible.
2. SIM input and output capacitors should be returned to the
SIMGND and kept as close as possible to the ADP3405 to
minimize noise. Traces to the SIM charge pump capacitor
should be kept as short as possible to minimize noise.
3. VCCA and VTCXO capacitors should be returned to AGND.
4. VCC and VRTC capacitors should be returned to DGND.
5. Split the ground connections. Use separate traces or planes
for the analog, digital, and power grounds, and tie them
together at a single point, preferably close to the battery return.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Thin Shrink Small Outline (TSSOP)
(RU-28)
0.177 (4.50)
0.169 (4.30)
28
15
14
1
0.386 (9.80)
0.378 (9.60)
0.256 (6.50)
0.246 (6.25)
PIN 1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
0.0433 (1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8
0

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