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Part Number ADN2841

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REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
ADN2841
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
Dual-Loop 50 Mbps­2.7 Gbps
FUNCTIONAL BLOCK DIAGRAM
CONTROL
DATAP
DATAN
CLKP
CLKN
IMODP
IBIAS
LD
V
CC
GND
ASET
I
MOD
I
BIAS
GND
GND
GND
GND
GND
LBWSET
IDTONE
PAVCAP
ERCAP
ERSET
PSET
IMPD2
IMPD
V
CC
MPD
IBMON
IMMON
IMPDMON
IMPDMON2
ALS
F
AIL
DEGRADE
CLKSEL
V
CC
GND
V
CC
ADN2841
IMODN
FEATURES
50 Mbps to 2.7 Gbps Operation
Typical Rise/Fall Time 80 ps
Bias Current Range 2 to 100 mA
Modulation Current Range 5 to 80 mA
Monitor Photodiode Current 50 A to 1200 A
Closed-Loop Control of Power and Extinction Ratio
Laser Fail and Laser Degrade Alarms
Automatic Laser Shutdown, ALS
Dual MPD Functionality for DWDM
Optional Clocked Data
Full Current Parameter Monitoring
5 V Operation
48-Lead LFCSP Package
32-Lead LFCSP Package (Reduced Functionality)
APPLICATIONS
DWDM Dual MPD Wavelength Fixing
SONET OC-1/3/12/48
SDH STM-1/4/16
Fiber Channel
Gigabit Ethernet
GENERAL DESCRIPTION
The ADN2841 uses a unique control algorithm to control both
average power and extinction ratio of the laser diode (LD) after
initial factory set up. External component count and PCB area are
low as both power and extinction ratio control are fully integrated.
Programmable alarms are provided for laser fail (end of life) and
laser degrade (impending fail).
The ADN2841 has circuitry for a second monitor photodiode
which enables DWDM wavelength control.
Laser Diode Driver
REV. 0
­2­
ADN2841­SPECIFICATIONS
(V
CC
= 5 V 10%. All specifications T
MIN
to T
MAX
unless otherwise noted
1
. Typical
values as specified at 25 C.)
Parameter
Min
Typ
Max
Unit
Conditions/Comments
LASER BIAS (BIAS)
Output Current I
BIAS
2
100
mA
Compliance Voltage
1.2
V
CC
V
I
BIAS
during ALS
0.1
mA
ALS Response Time
10
µs
CCBIAS Compliance Voltage
1.2
V
MODULATION CURRENT (IMODP, IMODN)
Output Current I
MOD
5
80
mA
Compliance Voltage
1.8
V
CC
V
I
MOD
during ALS
0.1
mA
Rise Time
80
120
ps
Fall Time
80
120
ps
Jitter
20
ps p-p
Pulsewidth Distortion
18
ps
MONITOR PD (MPD, MPD2)
Current
50
1200
µA
Average Current
Input Voltage
1.6
V
POWER SET INPUT (PSET)
Capacitance
80
pF
Input Current
50
1200
µA
Average Current
Voltage
1.15
1.23
1.35
V
EXTINCTION RATIO SET INPUT (ERSET)
Allowable Resistance Range
1.2
25
k
Voltage
1.15
1.23
1.35
V
ALARM SET (ASET)
Allowable Resistance Range
1.2
25
k
Voltage
1.15
1.23
1.35
V
Hysteresis
5
%
CONTROL LOOP
Time Constant
0.22
sec
(LBWSET = GND)
2.25
sec
(LBWSET = V
CC
)
DATA INPUTS (DATAP, DATAN, CLKP, CLKN)
AC-Coupled
2
V p-p (Single-Ended peak-to-peak)
100
500
mV
Input Impedance
50
t
SETUP
3
150
95
ps
t
HOLD
3
0
­70
ps
LOGIC INPUTS (ALS, LBWSET, CLKSEL)
V
IH
2.4
V
V
IL
0.8
V
ALARM OUTPUTS (Internal 30 k
Pull-up)
V
OH
2.4
V
V
OL
0.8
V
IDTONE
Compliance Voltage
V
CC
­ 1.5
V
User to Supply Current
Sink in the range 50
µA
to 4 mA
2
f
IN
4
0.01
1
MHz
I
I
RATIO
OUT
IN




REV. 0
­3­
ADN2841
Parameter
Min
Typ
Max
Unit
Conditions/Comments
IBMON, IMMON, IMPDMON, IMPDMON2
IBMON, IMMON Division Ratio
100
A/A
IMPDMON, IMPDMON2
1
A/A
IMPDMON to IMPDMON2 Matching
1
%
IMPD = 1200
µA
Compliance Voltage
0
V
CC
­ 1.2
V
SUPPLY
I
CC
5
0.05
A
I
BIAS
= I
MOD
= 0
V
CC
6
4.5
5.0
5.5
V
NOTES
1
Temperature Range: ­40
°C to +85°C
2
When the voltage on DATAP is greater than the voltage on DATAN, the modulation current flows in the IMODP pin.
3
Guaranteed by design and characterization. Not production tested.
4
IDTONE may cause eye distortion.
5
I
CC
for power calculation is the typical I
CC
given.
6
All V
CCS
should be shorted together.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25
°C unless otherwise noted.)
V
CC
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating Temperature Range
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . ­40
°C to +85°C
Storage Temperature Range . . . . . . . . . . ­65
°C to +150°C
Junction Temperature (T
J
MAX
) . . . . . . . . . . . . . . . . . . 150
°C
48-Lead LFCSP Package
Power Dissipation . . . . . . . . . . . . . . . (T
J
MAX
­ T
A
)/
JA
mW
JA
Thermal Impedance
2
. . . . . . . . . . . . . . . . . . . . 25
°C/W
Lead Temperature (Soldering for 10 sec) . . . . . . . . 300
°C
ORDERING GUIDE
Model
Temperature Range
Package Description
ADN2841ACP-32
­40
°C to +85°C
32-Lead LFCSP
ADN2841ACP-48
­40
°C to +85°C
48-Lead LFCSP
ADN2841ACP-32-RL
­40
°C to +85°C
32-Lead LFCSP
ADN2841ACP-32-RL7
­40
°C to +85°C
32-Lead LFCSP
ADN2841ACP-48-RL
­40
°C to +85°C
48-Lead LFCSP
32-Lead LFCSP Package
Power Dissipation . . . . . . . . . . . . . . . (T
J MAX
­ T
A
)/
JA
mW
JA
Thermal Impedance
2
. . . . . . . . . . . . . . . . . . . . 32
°C/W
Lead Temperature (Soldering for 10 sec) . . . . . . . . . 300
°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Transient currents of
up to 100 mA will not cause SCR latch-up.
2
JA
is defined when the part is soldered onto a four-layer board.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADN2841 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
SETUP
t
S
HOLD
t
H
DATAP/N
CLKP
Figure 1. Setup and Hold Time
REV. 0
ADN2841
­4­
PIN FUNCTION DESCRIPTIONS
Pin No.
48-Lead
32-Lead
Mnemonic
Function
1
GND
Supply Ground
2
1
LBWSET
Select Low Loop Bandwidth (Active = V
CC
)
3
2
ASET
Alarm Current Threshold Setting Pin
4
3
ERSET
Extinction Ratio Set Pin
5
4
PSET
Average Optical Power Set Pin
6
GND
Ground
7
5
IMPD
Monitor Photodiode Input
8
6
IMPDMON
Mirrored Current from Monitor Photodiode
9
IMPDMON2
Mirrored Current from Monitor Photodiode 2 (for use with two MPDs)
10
IMPD2
Monitor Photodiode Input 2­ (for use with two MPDs)
11
7
GND4
Supply Ground
12
8
VCC4
Supply Voltage
13
9
ERCAP
Extinction Ratio Loop Capacitor
14
10
PAVCAP
Average Power Loop Capacitor
15
GND
Ground
16
11
VCC1
Supply Voltage
17
GND1
Supply Ground
18
12
DATAN
Data, Negative Differential Terminal
19
13
DATAP
Data, Positive Differential Terminal
20
14
GND1
Supply Ground
21
15
CLKP
Data Clock Positive Differential Terminal, used if CLKSEL = V
CC
22
16
CLKN
Data Clock Negative Differential Terminal, used if CLKSEL = V
CC
23
GND
Ground
24
GND
Ground
25
GND
Ground
26
17
CLKSEL
Clock Select (Active = V
CC
), used if data is clocked into chip
27
18
DEGRADE
DEGRADE Alarm Output
28
19
FAIL
FAIL Alarm Output
29
20
ALS
Automatic Laser Shutdown
30
21
VCC3
Supply Voltage
31
22
GND3
Supply Ground
32
23
IMMON
Modulation Current Mirror Output
33
24
IBMON
Bias Current Mirror Output
34
GND2
Supply Ground
35
IDTONE
IDTONE (Requires external current sink to ground)
36
GND2
Supply Ground
PIN CONFIGURATIONS
48-Lead LFCSP
PIN 1
INDICATOR
ADN2841
TOP VIEW
(Not to Scale)
GND2 37
VCC2 38
IMODN 39
IMODN 40
GND2 41
IMODP 42
IMODP 43
GND2 44
GND2 45
IBIAS 46
IBIAS 47
CCBIAS 48
GND 1
LBWSET 2
ASET 3
ERSET 4
PSET 5
GND 6
IMPD 7
IMPDMON 8
IMPDMON2 9
IMPD2 10
GND4 11
VCC4 12
24 GND
23 GND
22 CLKN
21 CLKP
20 GND1
19 DATAP
18 DATAN
17 GND1
16 VCC1
15 GND
14 PAVCAP
13 ERCAP
36 GND2
35 IDT
ONE
34 GND2
33 IBMON
32 IMMON
31 GND3
30 VCC3
29 ALS
28 F
AIL
27 DEGRADE
26 CLKSEL
25 GND
32-Lead LFCSP
PIN 1
INDICATOR
TOP VIEW
(Not to Scale)
LBWSET 1
ASET 2
ERSET 3
32 CCBIAS
ERCAP 9
P
A
VCAP 10
VCC1 11
DA
T
A
N
1
2
DA
T
A
P
1
3
GND1 1
4
CLKP 15
CLKN 16
PSET 4
IMPD 5
IMPDMON 6
GND4 7
VCC4 8
31 IBIAS
30 GND2
29 GND2
28 IMODP
27 GND2
26 IMODN
25 VCC2
ADN2841
24 IBMON
23 IMMON
22 GND3
21 VCC3
20 ALS
19 FAIL
18 DEGRADE
17 CLKSEL
REV. 0
­5­
ADN2841
PIN FUNCTION DESCRIPTIONS (continued)
Pin No.
48-Lead
32-Lead
Mnemonic
Function
37
GND2
Supply Ground
38
25
VCC2
Supply Voltage
39
26
IMODN
Modulation Current Negative Output, connect to 25
40
IMODN
Modulation Current Negative Output, connect to 25
41
27
GND2
Supply Ground
42
28
IMODP
Modulation Current Positive Output, connect to laser diode
43
IMODP
Modulation Current Positive Output, connect to laser diode
44
29
GND2
Supply Ground
45
30
GND2
Supply Ground
46
31
IBIAS
Laser Diode Bias Current
47
IBIAS
Laser Diode Bias Current
48
32
CCBIAS
Extra Laser Diode Bias when AC-Coupled
REV. 0
ADN2841
­6­
LOOP BANDWIDTH SELECTION
For anyrate operation the user should hardwire the LBWSET
pin high and use 1
µF capacitors to set the actual loop band-
width. These capacitors are placed between the PAVCAP and
ERCAP pins and ground. It is important that these capacitors
be low-leakage multilayer ceramics with an insulation resistance
greater than 100 G
or a time constant of 1000 sec, whichever
is less. The ADN2841 may be optimized for 2.7 Gbps operation
by keeping the LBWSET pin low. This results in a much shorter
loop time constant (a 10 reduction). The value of PAVCAP
and ERCAP capacitors required for 2.5 Gbps operation is 22 nF.
ALARMS
The ADN2841 alarms are designed to allow interface compliance
to ITU-T-G958 (11/94) section 10.3.1.1.2 (transmitter fail) and
section 10.3.1.1.3 (transmitter degrade). The ADN2841 has
two active high alarms, DEGRADE and FAIL. A resistor between
ground and the ASET pin is used to set the current at which
these alarms are raised. The current through the ASET resistor is
a ratio of 100:1 to the FAIL alarm threshold. The DEGRADE
alarm will be raised at 90% of this level.
Example:
I
mA
I
mA
FAIL
DEGRADE
=
=
50
45
I
I
mA
A
ASET
BIASTRIP
=
=
=
µ
100
50
100
500
R
V
I
V
A
k
ASET
ASET
=
=
=
1 23
1 23
500
2 46
.
.
.
µ
NOTE: The smallest value for R
ASET
is 1.2 k
, as this corre-
sponds to the I
BIAS
maximum of 100 mA.
The laser degrade alarm, DEGRADE, gives a warning of imminent
laser failure if the laser diode degrades further or environmental
conditions continue to stress the LD, e.g., increasing temperature.
The laser fail alarm, FAIL, is activated when the transmitter can
no longer be guaranteed to be SONET/SDH-compliant. This
occurs when one of the following conditions arises:
· The ASET threshold is reached.
· The ALS pin is set high. This shuts off the modulation and
bias currents to the LD, resulting in the MPD current dropping
to zero. This gives closed-loop feedback to the system in which
ALS has been enabled.
DEGRADE will only be raised when the bias current exceeds
90% of ASET current.
MONITOR CURRENTS
IBMON, IMMON, and IMPDMON and IMPDMON2 are
current controlled current sources from V
CC
. They mirror the
bias, modulation, and MPD current for increased monitoring
functionality. An external resistor to GND gives a voltage pro-
portional to the current monitored.
DUAL MPD DWDM FUNCTION (48-PIN LFCSP ONLY)
The ADN2841 has circuitry for an optional second monitor
photodiode, MPD2.
GENERAL
Laser diodes have current-in to light-out transfer functions as shown
in Figure 2. Two key characteristics of this transfer function are the
threshold current, I
TH
, and slope in the linear region beyond the
threshold current, referred to as slope efficiency, LI.
ER =
P
AV
=
P1
P0
P1 + P0
2
P
I
LI =
P
I
I
TH
CURRENT
P1
P
AV
P0
OPTICAL PO
WER
Figure 2. Laser Transfer Function
CONTROL
A monitor photodiode (MPD) is required to control the LD. The
MPD current is fed into the ADN2841 to control the optical
power and extinction ratio, continuously adjusting the bias current
and modulation current in response to the laser's changing
threshold current and light-to-current (LI) slope (slope efficiency).
The ADN2841 uses automatic power control (APC) to main-
tain a constant power over time and temperature.
The ADN2841 uses closed-loop extinction ratio control to allow
optimum setting of extinction ratio for every device. Hence
SONET/SDH interface standards can be met over device varia-
tion, temperature, and time. Closed-loop modulation control
eliminates the need to either overmodulate the LD or include
external components for temperature compensation. This reduces
research and development time and second-sourcing issues
caused by characterizing LDs.
Average Power and Extinction Ratio are set using the PSET and
ERSET pins, respectively. Potentiometers are connected between
these pins and ground. The potentiometer,
R
PSET
, is used to
change the average power. The potentiometer,
R
ERSET
, is used
to adjust the extinction ratio. Both PSET and ERSET are
kept 1.23 V above GND.
R
PSET
and R
ERSET
can be calculated using the following formulas:
R
V
I
PSET
AV
=
1 23
.
where
I
AV
is average MPD current.
R
V
I
P
ER
ER
P
ERSET
MPD
CW
CW
AV
=
×
-
+
×
×
1 23
1
1
0 2
.
.
_
where
P
CW
is the dc optical power specified on the laser data
sheet,
I
MPD_CW
is MPD current at that specified
P
CW
, and
P
AV
is
the required average power.
Note that I
ERSET
and I
PSET
will change from device to device.
However, the control loops will determine actual values. It is not
required to know exact values for LI or MPD optical coupling.
REV. 0
ADN2841
­7­
The second photodiode current is mirrored to IMPDMON2
for wavelength control purposes and is summed internally for
the power control loop.
For single MPD circuits the MPD2 pin
is tied to GND.
This enables the system designer to use the two currents to
control the wavelength of the laser diode using various optical
filtering techniques inside the laser module.
If the monitor current functions IMPDMON and IMPDMON2
are not required, the IMPD and IMPD2 pins can be grounded
and the monitor photodiode output can be connected di-
rectly to PSET.
IDTONE (48-PIN LFCSP ONLY)
The IDTONE pin is supplied for fiber identification/supervisory
channels or control purposes in WDM. This pin modulates the
optical one level over a possible range of 2% of minimum IMOD
to 10% of maximum IMOD. The level of modulation is set by
connecting an external current sink between the IDTONE pin and
ground. There is a gain of two from this pin to the IMOD current.
Figure 3 shows how an AD9850/AD9851 DDS may be used
with the ADN2841 to allow fiber identification.
Note that using IDTONE during transmission may cause opti-
cal eye degradation.
DATA, CLOCK INPUTS
Data and Clock inputs are ac-coupled (10 nF recommended)
and terminated via a 100
internal resistor between DATAP
and DATAN, and also between CLKP and CLKN pins. There
is a high-impedance circuit to set the common-mode voltage
that is designed to change over temperature. It is recommended
that ac coupling be used to eliminate the need for matching
between common-mode voltages.
Figure 4. AC Coupling of Data Inputs
CCBIAS
CCBIAS should be connected to the BIAS pin if the laser diode is
connected to the ADN2841 using a capacitor. CCBIAS is a
current sink to GND.
AUTOMATIC LASER SHUTDOWN
The ADN2841 ALS allows compliance to ITU-T-G958
(11/94), section 9.7.
When ALS is logic high, both bias and modulation currents are
turned off.
Correct operation of ALS can be confirmed by the fail alarm
being raised when ALS is asserted. Note this is the only time
that DEGRADE will be low while FAIL is high.
Figure 3. Circuitry to Allow Fiber Identification
REF CLOCK
20MHz­
180MHz
CLKIN
AD9850/AD9851
DDS
R
SET
I
OUT
1.25mA­20mA
I
OUT
50
50
LP FILTER
(DC-COUPLED)
AD8602
10kHz­1MHz
0.125mA­2mA
BC550
500
50 A­800 A
1000
1300
BC550
37.5 A­600 A
IDTONE
ADN2841
IMMON
CONTROLLER
1/2
AD8602
1/2
ADN2841
R = 2.5k , DATA
R = 3k , CLK
TO FLIP-FLOPS
400 A TYP
DATAP
DATAN
V
REG
R
50
50
REV. 0
ADN2841
­8­
ADN2841
37
48
1
12
24
13
36 25
FU-445SDF-WM1
V
CC
V
CC
GND2
V
CC
V
CC
FAIL
DEGRADE
DATAP
DATAN
CLKN
CLKP
GND
VC
C
4
GND4
1.5k
V
CC
CCBIAS
V
CC
GND2
IDT
ONE
GND2
IBMON
IMMON
GND3
VCC3
ALS
F
AIL
DEGRADE
CLKSEL
GND
GND
VCC2
GND
IMODN
CLKN
IMODN
CLKP
GND2
GND1
IMODP
DATAP
IMODP
DATAN
GND2
GND1
GND2
VCC1
I
BIAS
GND
I
BIAS
PAVCAP
ERCAP
IMPD2
IMPDMON2
IMPDMON
IMPD
GND
PSET
ERSET
ASET
LBWSET
GND
100nF
100nF
100nF
100nF
10 F
V
CC
GND
NOTE
V
CC
s SHOULD HAVE BYPASS CAPACITORS AS CLOSE AS POSSIBLE TO THE
ACTUAL SUPPLY PINS ON THE ADN2841 AND THE LASER DIODE USED.
25
Figure 6. 2.7 Gbps Test Circuit, DC-Coupled, Data Not Clocked, Fast Loop Time Constant Selected
ALARM INTERFACES
A 30 k
internal pull-up resistor is employed to pull the digital
high value of the alarm outputs to V
CC
. However, the ADN2841
has a feature that allows the user to externally wire resistors in
parallel with the 30 k
pull-up resistors thus enabling the user
to interface to non-V
CC
levels.
Non-V
CC
alarm output levels must
be below the V
CC
used for the ADN2841.
POWER CONSUMPTION
The ADN2841 die temperature must be kept below 125
°C.
The
JA
for the 48-lead LFCSP is 25
°C/W and the 32-lead
LFCSP is 32
°C/W when soldered in a four-layered board. Both
LFCSP packages have an exposed paddle and as such need to
be soldered to the PCB to achieve this thermal performance.
T
T
P
DIE
AMBIENT
A
=
+
×
J
I
I
I
CC
CCMIN
MOD
=
+ 0 3
.
P
V
I
I
V
I
V
CC
CC
BIAS
BIAS
PIN
MOD
MOD
PIN
=
×
+
×
(
)
+
×
(
)
_
_
Hence the maximum combination of
I
BIAS
+
I
MOD
must be
calculated.
ADN2841
ADN2850
PSET
ERSET
DA
T
A
P
DA
T
A
N
IDT
ONE
IMODP
I
BIAS
DAC1
DAC2
SDI
SDO
CLK
CS
TX
RX
CLK
CS
V
CC
DATAP
DATAN
IDTONE
V
CC
V
CC
IMPD
Figure 5. Application Using Optical Supervisor ADN2850
as a Dual 10-Bit Digital Potentiometer Using Thin-Film
Resistor Technology to Give Very Low Temperature
Coefficients
REV. 0
ADN2841
­9­
ADN2841
37
48
1
12
24
13
36
25
GND2
V
CC
V
CC
FAIL
DEGRADE
DATAP
DATAN
CLKN
CLKP
GND
VC
C
4
GND4
1.5k
CCBIAS
25
V
CC
GND2
IDT
ONE
GND2
IBMON
IMMON
GND3
VCC3
ALS
F
AIL
DEGRADE
CLKSEL
GND
GND
VCC2
GND
IMODN
CLKN
IMODN
CLKP
GND2
GND1
IMODP
DATAP
IMODP
DATAN
GND2
GND1
GND2
VCC1
I
BIAS
GND
I
BIAS
PAVCAP
ERCAP
IMPD2
IMPDMON2
IMPDMON
IMPD
GND
PSET
ERSET
ASET
LBWSET
GND
100nF
100nF
100nF
100nF
10 F
V
CC
GND
V
CC
V
CC
V
CC
V
CC
V
CC
NOTE
V
CC
s SHOULD HAVE BYPASS CAPACITORS AS CLOSE AS POSSIBLE TO THE
ACTUAL SUPPLY PINS ON THE ADN2841 AND THE LASER DIODE USED.
Figure 7. Any Rate Test Circuit, Capacitively Coupled, Data Clocked, Slow Loop Time Constant Selected
REV. 0
ADN2841
­10­
ADN2841
12
24
48
36
CCBIAS
GND
BIAS
BIAS
GND2
GND2
IMODP
IMODP
GND2
IMODN
IMODN
VC
C
2
GND2
GND2
LBWSET
IDTONE
ASET
GND2
ERSET
IBMON
PSET
IMMON
GND
GND3
IMPD
VCC3
IMPDMON
ALS
IMPDMON2
FAIL
IMPD2
DEGRADE
GND4
CLKSEL
GND
CLKN
CLKP
GND1
DA
T
A
P
DA
T
A
N
GND1
VC
C
1
GND
P
A
VCAP
ERCAP
NOTES
1. V
CC
s SHOULD HAVE BYPASS CAPACITORS
AS CLOSE AS POSSIBLE TO THE ACTUAL
SUPPLY PINS ON THE ADN2841 AND THE
LASER DIODE USED.
2. THE OP293 HAS BEEN SELECTED BECAUSE
OF ITS GAIN BANDWIDTH PRODUCT AND
SHOULD BE USED IN THIS APPLICATION.
GND
EA MODULATOR
V
CC
V
CC
V
CC
V
CC
V
CC
50
50
V
CC
V
CC
1
V
CC
V
CC
V
CC
1k
1k
DAC
DAC
V
CC
V
CC
8
2
3
1
1/2 OP293
1/2 OP293
6
5
7
­V
CC
V
CC
VCC4
V
CC
Figure 9. Unfiltered 2.5 Gbps Optical Eye. Average
Power = ­3 dBm, Extinction Ratio = 9.5 dB. Eye
obtained using a Mitsubishi FU-445-SDF.
Figure 8. EA Modulator Application
Figure 10. Filtered 2.5 Gbps Optical Eye. Average
Power = ­3 dBm, Extinction Ratio = 9 dB. Eye
obtained using a Mitsubishi FU-445-SDF.
REV. 0
­11­
ADN2841
OUTLINE DIMENSIONS
Dimensions shown in millimeters and (inches).
48-Lead (7 7) LFCSP (Exposed Paddle)
(CP-48)
PIN 1
INDICATOR
TOP
VIEW
6.75 (0.266)
BSC SQ
7.00 (0.276)
BSC SQ
1
48
12
13
37
36
24
25
BOTTOM
VIEW
5.25 (0.207)
5.10 (0.201) SQ
4.95 (0.195)
0.60 (0.024)
0.42 (0.017)
0.24 (0.009)
0.50 (0.020)
0.40 (0.016)
0.30 (0.012)
0.30 (0.012)
0.23 (0.009)
0.18 (0.007)
0.50 (0.0197)
BSC
12
MAX
0.20 (0.0079)
REF
0.70 (0.028) MAX
0.65 (0.026) NOM
0.90 (0.035) MAX
0.85 (0.033) NOM
0.05 (0.0020)
0.01 (0.0004)
0.00 (0.0000)
5.50 (0.217)
REF
0.60 (0.024)
0.42 (0.017)
0.24 (0.009)
NOTE
EXPOSED PADDLE SHOULD BE SOLDERED TO THE MOST
NEGATIVE SUPPLY OF THE ADN2841
32-Lead (5 5) LFCSP (Exposed Paddle)
(CP-32)
1
32
8
9
25
24
16
17
BOTTOM
VIEW
3.25 (0.128)
3.10 (0.122)
2.95 (0.116)
REF SQ
0.50 (0.020)
0.40 (0.016)
0.30 (0.012)
0.30 (0.0118)
0.23 (0.0091)
0.18 (0.0071)
5.60 (0.220 )
REF
0.50 (0.0197)
BSC
12
MAX
0.20 (0.0079)
REF
0.70 (0.028) MAX
0.65 (0.026) NOM
PIN 1
INDICATOR
TOP
VIEW
5.00 (0.197)
BSC SQ
4.75 (0.187)
BSC SQ
0.90 (0.035) MAX
0.85 (0.033) NOM
0.05 (0.0020)
0.01 (0.0004)
0.00 (0.0000)
0.60 (0.024)
0.42 (0.017)
0.24 (0.009)
NOTES
1. DIMENSIONS MEET JEDEC MO-220-VHHD-2
2. EXPOSED PADDLE SHOULD BE SOLDERED TO THE
MOST NEGATIVE SUPPLY OF THE ADN2841
­12­
C02659­0­10/01(0)
PRINTED IN U.S.A.