Document Outline
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- GENERAL DESCRIPTION
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- POWER CONSUMPTION
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11.3 Gbps, Active Back-Termination,
Differential VCSEL Driver
ADN2530
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
FEATURES
Up to 11.3 Gbps operation
-40°C to +100°C operation
Very low power: I
SUPPLY
= 65 mA
Typical 26 ps rise/fall times
Full back-termination of output transmission lines
Crosspoint adjust function
PECL-/CML-compatible data inputs
Bias current range: 2 mA to 25 mA
Differential modulation current range: 2.2 mA to 23 mA
Automatic laser shutdown (ALS)
3.3 V operation
Compact 3 mm × 3 mm LFCSP
Voltage-input control for bias and modulation currents
XFP-compliant bias current monitor
APPLICATIONS
10 Gb Ethernet optical transceivers
10G-BASE-LRM optical transceivers
8× and 10× Fibre Channel optical transceivers
XFP/X2/XENPAK/MSA 300 optical modules
SONET OC-192/SDH STM-64 optical transceivers
GENERAL DESCRIPTION
The ADN2530 laser diode driver is designed for direct modula-
tion of packaged VCSELs with a differential resistance ranging
from 35 to 140 . The active back-termination technique
provides excellent matching with the output transmission lines
while reducing the power dissipation in the output stage. The
back-termination in the ADN2530 absorbs signal reflections
from the TOSA end of the output transmission lines, enabling
excellent optical eye quality to be achieved even when the
TOSA end of the output transmission lines is significantly
misterminated. The small package provides the optimum
solution for compact modules where laser diodes are packaged
in low pin count optical subassemblies.
The modulation and bias currents are programmable via the
MSET and BSET control pins. By driving these pins with
control voltages, the user has the flexibility to implement
various average power and extinction ratio control schemes,
including closed-loop control and look-up tables. The eye
crosspoint in the output eye diagram is adjustable via the
crosspoint adjust (CPA) control voltage input. The automatic
laser shutdown (ALS) feature allows the user to turn on/off the
bias and modulation currents by driving the ALS pin with the
proper logic levels. The product is available in a space-saving
3 mm × 3 mm LFCSP specified from -40°C to +100°C.
FUNCTIONAL BLOCK DIAGRAM
05
45
7-
00
1
100
200
800
200
10
VCC
DATAP
DATAN
MSET
GND
BSET
IBMON
IBIAS
IMODP
IMODN
ADN2530
VCC
ALS
GND
VCC
VCC
50
50
CPA
200
800
CROSS
POINT
ADJUST
IMOD
Figure 1.
ADN2530
Rev. A | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Package Thermal Specifications ................................................. 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 10
Input Stage................................................................................... 10
Bias Current ................................................................................ 10
Automatic Laser Shutdown (ALS) ........................................... 11
Modulation Current................................................................... 11
Load Mistermination ................................................................. 13
Crosspoint Adjust....................................................................... 13
Power Consumption .................................................................. 13
Applications Information .............................................................. 15
Typical Application Circuit....................................................... 15
Layout Guidelines....................................................................... 15
Design Example.......................................................................... 16
Headroom Calculations ........................................................ 16
BSET and MSET Pin Voltage Calculation .......................... 16
IBIAS Monitor Accuracy Calculations................................ 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
8/06--Rev. 0 to Rev. A
Changes to Figure 1.......................................................................... 1
Changes to Table 3............................................................................ 5
Changes to Figure 24...................................................................... 10
Changes to Figure 30...................................................................... 11
Changes to Modulation Current Section .................................... 12
Changes to Typical Application Circuit Section......................... 15
10/05--Revision 0: Initial Version
ADN2530
Rev. A | Page 3 of 20
SPECIFICATIONS
VCC = VCC
MIN
to VCC
MAX
, T
A
= -40°C to +100°C, 100 differential load impedance, crosspoint adjust disabled, unless otherwise noted.
Typical values are specified at 25°C and IMOD = 10 mA with crosspoint adjust disabled, unless otherwise noted.
Table 1.
Parameter Min
Typ
Max
Unit
Test
Conditions/Comments
BIAS CURRENT (IBIAS)
Bias Current Range
2
25
mA
Bias Current While ALS Asserted
50
A
ALS = high
Compliance Voltage
1
0.55
VCC 1.3
V
IBIAS = 25 mA
0.55
VCC 0.8
V
IBIAS = 2 mA
MODULATION CURRENT (IMODP, IMODN)
Modulation Current Range
2.2
23
mA diff
R
LOAD
= 35 to 100 differential
2.2
19
mA
diff
R
LOAD
= 140 differential
Modulation Current While ALS Asserted
250
A diff
ALS = high
Crosspoint Adjust (CPA) Range
2
35
65 %
Rise Time (20% to 80%)
2, 3 , 4
26
32.5
ps
CPA disabled
26.4
34.7
ps
CPA 35% to 65%
Fall Time (20% to 80%)
2, 3, 4
26
32.5
ps
CPA
disabled
26.5
33.7
ps
CPA 35% to 65%
Random Jitter
2, 3, 4
<0.5
ps
rms
CPA
disabled
<0.5
ps rms
CPA 35% to 65%
Deterministic Jitter
2, 4, 5
5.4
8.2
ps
p-p
10.7 Gbps, CPA disabled
5.8
8.2
ps
p-p
10.7 Gbps, CPA 35% to 65%
Deterministic Jitter
2, 4, 6
5.4
8.2
ps
p-p
11.3 Gbps, CPA disabled
5.8
8.2
ps
p-p
11.3 Gbps, CPA 35% to 65%
Differential |S22|
-5
dB
5 GHz < f < 10 GHz, Z
0
= 100 differential
-13.6
dB
f < 5 GHz, Z
0
= 100 differential
Compliance Voltage
1
VCC - 0.7
VCC + 0.7
V
DATA INPUTS (DATAP, DATAN)
Input Data Rate
11.3
Gbps
NRZ
Differential Input Swing
0.4
1.6
V p-p diff
Differential ac-coupled
Differential |S11|
-15
dB
f < 10 GHz, Z
0
= 100 differential
Input Termination Resistance
85
100
115
Differential
BIAS CONTROL INPUT (BSET)
BSET Voltage to IBIAS Gain
15
20
24
mA/V
BSET Input Resistance
800
1000
1200
MODULATION CONTROL INPUT (MSET)
MSET Voltage to IMOD Gain
14
19
23
mA/V
MSET Input Resistance
800
1000
1200
BIAS MONITOR (IBMON)
IBMON to IBIAS Ratio
50
A/mA
Accuracy of IBIAS to IBMON Ratio
-5.0
+5.0
%
IBIAS = 2 mA, R
IBMON
= 750
-4.3
+4.3
%
IBIAS = 4 mA, R
IBMON
= 750
-3.5
+3.5
%
IBIAS = 8 mA, R
IBMON
= 750
-3.0
+3.0
%
IBIAS = 14 mA, R
IBMON
= 750
-2.5
+2.5
%
IBIAS = 25 mA, R
IBMON
= 750
AUTOMATIC LASER SHUTDOWN (ALS)
V
IH
2.4
V
V
IL
0.8
V
I
IL
-20 +20 A
I
IH
0
200
A
ADN2530
Rev. A | Page 4 of 20
Parameter Min
Typ
Max
Unit
Test
Conditions/Comments
ALS Assert Time
2
s
Rising edge of ALS to fall of IBIAS and IMOD
below 10% of nominal; see Figure 2
ALS Negate Time
10
s
Falling edge of ALS to rise of IBIAS and IMOD
above 90% of nominal; see Figure 2
POWER
SUPPLY
V
CC
3.07 3.3
3.53 V
I
CC
7
27
32
mA
V
BSET
= V
MSET
= 0 V
I
SUPPLY
8
65
76
mA
V
BSET
= V
MSET
= 0 V
1
The voltage between the pin with the specified compliance voltage and GND.
2
Specified for T
A
= -40°C to +85°C due to test equipment limitation. See the Typical Performance Characteristics section for data on performance for T
A
= -40°C to +100°C.
3
The pattern used is composed of a repetitive sequence of eight 1s followed by eight 0s at 10.7 Gbps.
4
Measured using the high speed characterization circuit shown in Figure 3.
5
The pattern used is K28.5 (00111110101100000101) at 10.7 Gbps rate.
6
The pattern used is K28.5 (00111110101100000101) at 11.3 Gbps rate.
7
Only includes current in the ADN2530 VCC pins.
8
Includes current in ADN2530 VCC pins and dc current in IMODP and IMODN pull-up inductors. See the Power Consumption section for total supply current calculation.
PACKAGE THERMAL SPECIFICATIONS
Table 2.
Parameter Min
Typ
Max
Unit
Conditions/Comments
J-TOP
65
72.2
79.4
°C/W
Thermal resistance from junction to top of package.
J-PAD
2.6
5.8
10.7
°C/W
Thermal resistance from junction to bottom of exposed pad.
IC Junction Temperature
125
°C
90%
10%
ALS
IBIAS
AND IMOD
ALS
ASSERT TIME
ALS
NEGATE TIME
t
t
05457-
002
Figure 2. ALS Timing Diagram
MSET CPA
ALS
GND
BSET IBMON IBIAS GND
VCC
IMODP
IMODN
VCC
J8
J5
VEE
VEE
TP1
10nF
ADN2530
10
F
VEE
GND
GND
GND
GND
GND
GND
GND
GND
GND
50
50
OSCILLOSCOPE
BIAS TEE: PICOSECOND PULSE LABS MODEL 5542-219
ADAPTER: PASTERNACK PE-9436 2.92mm FEMALE-TO-FEMALE ADAPTER
ATTENUATOR: PASTERNACK PE-7046 2.92mm 10dB ATTENUATOR
DC-BLOCK: AGILENT BLOCKING CAPACITOR 11742A
ADAPTER
VBSET
Z
0
= 50
Z
0
= 50
Z
0
= 50
Z
0
= 50
Z
0
= 50
Z
0
= 50
750
VEE
VEE
VMSET
GND
GND
GND
VEE
VCPA
TP2
10
10nF
GND
VEE
J2
GND
GND
GND
GND
VCC
VCC
DATAN
DATAP
GND
GND
GND
J3
GND
GND
BIAS TEE
BIAS TEE
ADAPTER
ATTENUATOR
ATTENUATOR
05457-
003
DC-BLOCK
DC-BLOCK
Figure 3. High Speed Characterization Circuit
ADN2530
Rev. A | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage--VCC to GND
-0.3 V to +4.2 V
IMODP, IMODN to GND
VCC - 1.5 V to +4.5 V
DATAP, DATAN to GND
VCC - 1.8 V to VCC - 0.4 V
All Other Pins
-0.3 V to VCC + 0.3 V
Junction Temperature
150°C
Storage Temperature Range
-65°C to +150°C
Soldering Temperature
(Less than 10 sec)
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADN2530
Rev. A | Page 6 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05457-004
12
11
10
9
GND
IBIAS
IBMON
BSET
1
MSET
2
3
5
VC
C
IMODN
IMODP
VC
C
6
7
8
4
GND
ALS
CPA
16
15
14
13
ADN2530
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
VC
C
DATAN
DATAP
VC
C
NOTES:
THERE IS AN EXPOSED PAD ON THE
BOTTOM OF THE PACKAGE THAT MUST BE
CONNECTED TO THE VCC OR GND PLANE.
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
I/O
Description
1
MSET
Input
Modulation Current Control Input
2
CPA
Input
Crosspoint Adjust Control Input
3
ALS
Input
Automatic Laser Shutdown
4 GND
Power
Negative
Power
Supply
5
VCC
Power
Positive Power Supply
6
IMODN
Output
Modulation Current Negative Output
7
IMODP
Output
Modulation Current Positive Output
8
VCC
Power
Positive Power Supply
9 GND
Power
Negative
Power
Supply
10
IBIAS
Output
Bias Current Output
11 IBMON
Output
Bias
Current Monitoring Output
12
BSET
Input
Bias Current Control Input
13
VCC
Power
Positive Power Supply
14
DATAP
Input
Data Signal Positive Input
15
DATAN
Input
Data Signal Negative Input
16
VCC
Power
Positive Power Supply
Exposed Pad
Pad
Power
Connect to GND or VCC
ADN2530
Rev. A | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
T
A
= 25°C, VCC = 3.3 V, crosspoint adjust disabled, unless otherwise noted.
05457-035
0
0
30
25
20
15
10
5
25
20
15
10
5
DIFFERENTIAL MODULATION CURRENT (mA)
R
I
SE TIM
E (
p
s)
Figure 5. Rise Time vs. IMOD
05457-036
0
0
5
10
15
20
25
30
25
20
15
10
5
DIFFERENTIAL MODULATION CURRENT (mA)
FALL TIME (ps)
Figure 6. Fall Time vs. IMOD
05457-049
0
40
35
30
25
20
15
10
5
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
FREQUENCY (GHz)
DIFFE
RE
NTIAL |S
1
1
|
(dB)
Figure 7. Differential |S11|
05457-037
0
0
1
2
3
4
5
6
7
8
9
10
25
10.7Gbps
11.3Gbps
20
15
10
5
DIFFERENTIAL MODULATION CURRENT (mA)
DE
TE
RMINIS
TIC J
I
TTE
R (ps
)
Figure 8. Deterministic Jitter vs. IMOD
05457-048
0
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
25
20
15
10
5
DIFFERENTIAL MODULATION CURRENT (mA)
RANDOM J
I
TTE
R (ps
rms
)
JITTER BELOW EQUIPMENT
MEASUREMENT CAPABILITY
Figure 9. Random Jitter vs. IMOD
05457-050
0
40
35
30
25
20
15
10
5
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
FREQUENCY (GHz)
DIFFE
RE
NTIAL |S
2
2
|
(dB)
Figure 10. Differential |S22|
ADN2530
Rev. A | Page 8 of 20
05457-044
40
0
5
10
15
20
25
30
35
100
80
60
40
20
0
20
TEMPERATURE (°C)
R
I
SE TIM
E (
p
s)
Figure 11. Rise Time vs. Temperature (Worse-Case Conditions, CPA Disabled)
05457-045
40
0
5
10
15
20
25
30
35
100
80
60
40
20
0
20
TEMPERATURE (°C)
FALL TIME (ps)
Figure 12. Fall Time vs. Temperature (Worst-Case Conditions, CPA Disabled)
05457-046
40
0
0.2
0.4
0.6
0.8
1.0
100
80
60
40
20
0
20
TEMPERATURE (°C)
RANDOM J
I
TTE
R (ps
rms
)
Figure 13. Random Jitter vs. Temperature
(Worst-Case Conditions, CPA Disabled [Worst-Case IMOD = 2.2 mA])
05457-047
40
0
10
9
8
7
6
5
4
3
2
1
100
80
60
40
20
0
20
TEMPERATURE (°C)
DETERMINISTIC JITTER (ps)
10.7Gbps
11.3Gbps
Figure 14. Deterministic Jitter vs. Temperature
(Worse-Case Conditions, CPA Disabled)
05457-042
1.00
20
30
40
50
60
70
80
2.50
2.25
2.00
1.75
1.50
1.25
CPA VOLTAGE (V)
IM
OD
EYE C
R
OSSPOIN
T (
%
)
VCC = [3.07, 3.3, 3.53]
Figure 15. IMOD Eye Diagram Crosspoint vs. CPA Voltage and VCC
(IMOD = 10 mA)
05457-043
0.75
20
30
40
50
60
70
80
2.50
2.25
2.00
1.75
1.50
1.25
1.00
CPA VOLTAGE (V)
IM
OD
EYE C
R
OSSPOIN
T (
%
)
+100°C
+85°C
+25°C
40°C
Figure 16. IMOD Eye Diagram Crosspoint vs. CPA Voltage and Temperature
(IMOD = 10 mA)
ADN2530
Rev. A | Page 9 of 20
05457-038
0
0
20
40
80
60
100
120
140
25
20
15
10
5
DIFFERENTIAL MODULATION CURRENT (mA)
TOTAL S
U
P
P
LY
CURRE
NT (mA)
IBIAS = 25mA
IBIAS = 10mA
IBIAS = 2mA
Figure 17. Total Supply Current vs. IMOD
05457-039
26
0
5
10
15
20
25
31
30
29
28
27
RISE TIME (ps)
OCCURANCE
(%)
Figure 18. Worst-Case Rise Time Distribution
05457-040
26
0
5
10
15
20
25
31
30
29
28
27
FALL TIME (ps)
OCCURANCE
(%)
Figure 19. Worst-Case Fall Time Distribution
05457-014
1 LEVEL
1 LEVEL
0 LEVEL
0 LEVEL
CROSSING
Figure 20. Electrical Eye Diagram
(IMOD = 10 mA, PRBS31 Pattern at 10.3125 Gbps)
05457-016
Figure 21. Filtered 10G Ethernet Optical Eye Using AOC HFE6192-562 VCSEL
(PRBS31 Pattern at 10.3125 Gbps, 3 dB Optical Attenuator)
ADN2530
Rev. A | Page 10 of 20
THEORY OF OPERATION
As shown in Figure 1, the ADN2530 consists of an input
stage and two voltage-controlled current sources for bias and
modulation. The bias current is available at the IBIAS pin. It is
controlled by the voltage at the BSET pin and can be monitored
at the IBMON pin. The differential modulation current is
available at the IMODP and IMODN pins. It is controlled by
the voltage at the MSET pin. The output stage implements the
active back-termination circuitry for proper transmission line
matching and power consumption reduction. The ADN2530
can drive a load with differential resistance ranging from 35
to 140 . The excellent back-termination in the ADN2530
absorbs signal reflections from the TOSA end of the output
transmission lines, enabling excellent optical eye quality to be
achieved even when the TOSA end of the output transmission
lines is significantly misterminated.
INPUT STAGE
The input stage of the ADN2530 converts the data signal applied
to the DATAP and DATAN pins to a level that ensures proper
operation of the high speed switch. The equivalent circuit of the
input stage is shown in Figure 22.
VCC
50
50
VCC
DATAP
DATAN
VCC
05457-017
Figure 22. Equivalent Circuit of the Input Stage
The DATAP and DATAN pins are terminated internally with a
100 differential termination resistor. This minimizes signal
reflections at the input that could otherwise lead to degradation
in the output eye diagram. It is not recommended to drive the
ADN2530 with single-ended data signal sources.
The ADN2530 input stage must be ac-coupled to the signal
source to eliminate the need for matching between the common-
mode voltages of the data signal source and the input stage of
the driver (see Figure 23). The ac-coupling capacitors should
have an impedance less than 50 over the required frequency
range. Generally, this is achieved using 10 nF to 100 nF
capacitors.
ADN2530
DATAP
DATAN
C
C
50
50
DATA SIGNAL SOURCE
05457-018
Figure 23. AC Coupling the Data Source to the ADN2530 Data Inputs
BIAS CURRENT
The bias current is generated internally using a voltage-to-current
converter consisting of an internal operational amplifier and a
transistor, as shown in Figure 24.
GND
200
800
10
VCC
IBMON
BSET
IBMON
ADN2530
IBIAS
200
IBIAS
0
54
57
-
01
9
Figure 24. Voltage-to-Current Converter Used to Generate IBIAS
The BSET to IBIAS voltage-to-current conversion factor is
set at 20 mA/V by the internal resistors, and the bias current is
monitored at the IBMON pin using a current mirror with a gain
equal to 1/20. By connecting a 750 resistor between IBMON
and GND, the bias current can be monitored as a voltage across
the resistor. A low temperature coefficient precision resistor
must be used for the IBMON resistor (R
IBMON
). Any error in
the value of R
IBMON
due to tolerances or drift in its value over
temperature contributes to the overall error budget for the IBIAS
monitor voltage. If the IBMON voltage is being connected to an
ADC for A/D conversion, R
IBMON
should be placed close to the
ADC to minimize errors due to voltage drops on the ground
plane. See the Design Example section for example calculations
of the accuracy of the IBIAS monitor as a percentage of the
nominal IBIAS value.
ADN2530
Rev. A | Page 11 of 20
The equivalent circuits of the BSET, IBIAS, and IBMON pins
are shown in Figure 25 to Figure 27.
VCC
BSET
VCC
800
200
05457-020
Figure 25. Equivalent Circuit of the BSET Pin
10
2k
100
IBIAS
VCC
VCC
05457-021
Figure 26. Equivalent Circuit of the IBIAS Pin
VCC
IBMON
VCC
100
500
VCC
05457-022
Figure 27. Equivalent Circuit of the IBMON Pin
The recommended configuration for BSET, IBIAS, and IBMON
is shown in Figure 28.
ADN2530
BSET
VBSET
GND
IBMON
IBIAS
TO LASER CATHODE
L
R
IBMON
750
IBIAS
05457-023
Figure 28. Recommended Configuration for BSET, IBIAS, and IBMON Pins
The circuit used to drive the BSET voltage must be able to drive
the 1 k input resistance of the BSET pin. For proper operation
of the bias current source, the voltage at the IBIAS pin must be
between the compliance voltage specifications for this pin over
supply, temperature, and bias current range (see Table 1). The
maximum compliance voltage is specified for only two bias
current levels (2 mA and 25 mA), but it can be calculated for
any bias current by
V
COMPLIANCE
(V) = VCC (V) - 0.75 - 22 × IBIAS (A)
See the Headroom Calculations section for examples.
The function of Inductor L is to isolate the capacitance of the
IBIAS output from the high frequency signal path. For
recommended components, see Table 6.
AUTOMATIC LASER SHUTDOWN (ALS)
The ALS pin is a digital input that enables/disables both the bias
and modulation currents, depending on the logic state applied,
as shown in Table 5.
Table 5.
ALS Logic State
IBIAS and IMOD
High Disabled
Low Enabled
Floating Enabled
The ALS pin is compatible with 3.3 V CMOS and TTL logic
levels. Its equivalent circuit is shown in Figure 29.
VCC
ALS
VCC
100
35k
2k
05457-024
Figure 29. Equivalent Circuit of the ALS Pin
MODULATION CURRENT
The modulation current can be controlled by applying a dc
voltage to the MSET pin. This voltage is converted into a dc
current by using a voltage-to-current converter that uses an
operational amplifier and a bipolar transistor, as shown in
Figure 30.
100
200
800
MSET
GND
IMODP
IMODN
ADN2530
VCC
FROM CPA STAGE
0
54
57
-
02
5
IMOD
Figure 30. Generation of Modulation Current on the ADN2530
This dc current is switched by the data signal applied to the
input stage (DATAP and DATAN pins) and gained up by the
output stage to generate the differential modulation current at
the IMODP and IMODN pins. The output stage also generates
the active back-termination, which provides proper transmission
line termination. Active back-termination uses feedback around
an active circuit to synthesize a broadband termination resistance.
ADN2530
Rev. A | Page 12 of 20
This provides excellent transmission line termination while
dissipating less power than a traditional resistor passive back-
termination. No portion of the modulation current flows in the
active back-termination resistance. All of the preset modulation
current IMOD, the range specified in Table 1, flows in the
external load. The equivalent circuits for MSET, IMODP, and
IMODN are shown in Figure 31 and Figure 32. The two 50
resistors in Figure 32 are not real resistors. They represent the
active back-termination resistance.
VCC
MSET
800
200
VCC
05457-026
Figure 31. Equivalent Circuit of the MSET Pin
VCC
VCC
15
15
50
IMODP
IMODN
50
05457-027
Figure 32. Equivalent Circuit of the IMODP and IMODN Pins
The recommended configuration of the MSET, IMODP, and
IMODN pins is shown in Figure 33. See Table 6 for recom-
mended components. When the voltage on DATAP is greater
than the voltage on DATAN, the modulation current flows into
the IMODP pin and out of the IMODN pin, generating an
optical Logic 1 level at the TOSA output when the TOSA is
connected as shown in Figure 33.
05457-028
ADN2530
MSET
VMSET
GND
IMODN
IMODP
C
TOSA
Z
0
= 50
Z
0
= 50
C
Z
0
= 50
Z
0
= 50
L
VCC
L
VCC
VCC
L
L
IBIAS
Figure 33. Recommended Configuration for the
MSET, IMODP, and IMODN Pins
The ratio between the voltage applied to the MSET pin and the
differential modulation current available at the IMODP and
IMODN pins is a function of the load resistance value, as shown
in Figure 34.
05457-029
10
10
45
40
35
30
25
20
15
140
130
120
110
100
90
80
70
60
50
40
30
20
DIFFERENTIAL LOAD RESISTANCE
M
SET VOLTA
GE TO M
O
D
U
L
A
T
ION
CURRE
NT RATIO (mA/V
)
MAX
TYP
MIN
Figure 34. MSET Voltage to Modulation Current Ratio vs.
Differential Load Resistance
Using the resistance of the TOSA, the user can calculate the
voltage range that should be applied to the MSET pin to
generate the required modulation current range (see the
example in the Applications Information section).
The circuit used to drive the MSET voltage must be able to
drive the 1 k resistance of the MSET pin. To be able to drive
23 mA modulation currents through the differential load, the
output stage of the ADN2530 (IMODP and IMODN pins)
must be ac-coupled to the load. The voltages at these pins
have a dc component equal to VCC and an ac component with
single-ended peak-to-peak amplitude of IMOD × 50 . This
is the case when the load impedance (R
TOSA
) is less than
100 differential because the transmission line characteristic
impedance sets the peak-to-peak amplitude. For the case where
R
TOSA
is greater than 100 , the single-ended, peak-to-peak
amplitude is IMOD × R
TOSA
÷ 2. For proper operation of the
output stage, the voltages at the IMODP and IMODN pins must
be between the compliance voltage specifications for this pin
over supply, temperature, and modulation current range, as
shown in Figure 35. See the Headroom Calculations section for
examples of headroom calculations.
V
IMODP,
V
IMODN
VCC
VCC 0.7V
VCC + 0.7V
NORMAL OPERATION REGION
05457-030
Figure 35. Allowable Range for the Voltage at IMODP and IMODN
ADN2530
Rev. A | Page 13 of 20
LOAD MISTERMINATION
Due to its excellent S22 performance, the ADN2530 can drive
differential loads that range from 35 to 140 . In practice,
many TOSAs have differential resistance not equal to 100 . In
this case, with 100 differential transmission lines connecting
the ADN2530 to the load, the load end of the transmission lines
are misterminated. This mistermination leads to signal reflections
back to the driver. The excellent back-termination in the
ADN2530 absorbs these reflections, preventing their reflection
back to the load. This enables excellent optical eye quality to
be achieved even when the load end of the transmission lines is
significantly misterminated. The connection between the load
and the ADN2530 must be made with 100 differential (50
single-ended) transmission lines so that the driver end of the
transmission lines is properly terminated.
CROSSPOINT ADJUST
The crossing level in the output electrical eye diagram can be
adjusted between 35% and 65% using the crosspoint adjust (CPA)
control input. This can be used to compensate for asymmetry in
the VCSEL response and optimizes the optical eye mask margin.
The CPA input is a voltage control input, and a plot of eye cross-
point vs. CPA control voltage is shown in Figure 15 and Figure 16
in the Typical Performance Characteristics section. The equivalent
circuit for the CPA pin is shown in Figure 36. To disable the
crosspoint adjust function and set the eye crossing to 50%, the
CPA pin should be tied to VCC.
05457-031
100
VCC
CPA
Figure 36. Equivalent Circuit for CPA Pin
POWER CONSUMPTION
The power dissipated by the ADN2530 is given by
)
2
.
1
(
50
×
×
+
+
×
=
IBIAS
V
I
V
VCC
P
IBIAS
SUPPLY
MSET
where:
VCC is the power supply voltage.
IBIAS is the bias current generated by the ADN2530.
V
MSET
is the voltage applied to the MSET pin.
I
SUPPLY
is the sum of the current that flows into the VCC,
IMODP, and IMODN pins of the ADN2530 when IBIAS =
IMOD = 0 expressed in amps (see Table 1).
V
IBIAS
is the average voltage on the IBIAS pin.
Considering VBSET/IBIAS = 50 as the conversion factor from
V
BSET
to IBIAS, the dissipated power becomes
×
×
+
+
×
=
2
.
1
50
50
BSET
IBIAS
SUPPLY
MSET
V
V
I
V
VCC
P
To ensure long-term reliable operation, the junction tempera-
ture of the ADN2530 must not exceed 125°C, as specified in
Table 2. For improved heat dissipation, the module's case can be
used as a heat sink, as shown in Figure 37.
T
TOP
T
J
TPAD
DIE
PACKAGE
THERMAL COMPOUND
MODULE CASE
PCB
VIAS
COPPER PLANE
THERMO-COUPLE
05457-032
Figure 37. Typical Optical Module Structure
ADN2530
Rev. A | Page 14 of 20
P
J-TOP
T
PAD
T
TOP
T
TOP
J-PAD
T
PAD
T
J
05757-033
A compact optical module is a complex thermal environment,
and calculations of device junction temperature using the
package
JA
(junction-to-ambient thermal resistance) do not
yield accurate results. The following equation, derived from the
model in Figure 38, can be used to estimate the IC junction
temperature:
(
)
TOP
J
PAD
J
TOP
J
PAD
PAD
J
TOP
TOP
J
PAD
J
J
T
T
P
T
-
-
-
-
-
-
+
×
+
×
+
×
×
=
Figure 38. Electrical Model for Thermal Calculations
where:
T
TOP
and T
PAD
can be determined by measuring the temperature
at points inside the module, as shown in Figure 37. The thermo-
couples should be positioned to obtain an accurate measurement of
the package top and paddle temperatures.
J-TOP
and
J-PAD
are
given in Table 2.
T
TOP
is the temperature at top of package in degrees Celsius.
T
PAD
is the temperature at package exposed paddle in degrees
Celsius.
T
J
is the IC junction temperature in degrees Celsius.
P is the ADN2530 power dissipation in watts.
J-TOP
is the thermal resistance from IC junction to package top.
J-PAD
is the thermal resistance from IC junction to package
exposed pad.
ADN2530
Rev. A | Page 15 of 20
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
Figure 39 shows the typical application circuit for the
ADN2530. The dc voltages applied to the BSET and MSET pins
control the bias and modulation currents. The bias current can
be monitored as a voltage drop across the 750 resistor connected
between the IBMON pin and GND. The dc voltage applied to
the CPA pin controls the crosspoint in the output eye diagram.
By tying the CPA pin to VCC, the CPA function is disabled. The
ALS pin allows the user to turn on/off the bias and modulation
currents depending on the logic level applied to the pin. The
data signal source must be connected to the DATAP and DATAN
pins of the ADN2530 using 50 transmission lines. The
modulation current outputs, IMODP and IMODN, must be
connected to the load (TOSA) using 100 differential (50
single-ended) transmission lines. Table 6 shows recommended
components for the ac-coupling interface between the ADN2530
and TOSA. For additional application information and optical
eye diagram performance data, see the application notes and
reference design for the ADN2530 at www.analog.com.
Table 6.
Component Value Description
R1, R2
110
0603 size resistor
R3, R4
300
0603 size resistor
C3, C4
100 nF
0402 size capacitor,
Phycomp 223878719849
L6, L7
160 nH
0603 size inductor,
Murata LQW18ANR16
L2, L3
0603 size chip ferrite bead,
Murata BLM18HG601
L1, L4, L5, L8
10 H
0805 size inductor,
Murata LQM21FN100M70L
LAYOUT GUIDELINES
Due to the high frequencies at which the ADN2530 operates,
care should be taken when designing the PCB layout to obtain
optimum performance. Controlled impedance transmission
lines must be used for the high speed signal paths. The length
of the transmission lines must be kept to a minimum to reduce
losses and pattern-dependent jitter. The PCB layout must be
symmetrical both on the DATAP and DATAN inputs and on
the IMODP and IMODN outputs to ensure a balance between
the differential signals. All VCC and GND pins must be connected
to solid copper planes by using low inductance connections.
When the connections are made through vias, multiple vias can
be connected in parallel to reduce the parasitic inductance.
Each GND pin must be locally decoupled to VCC with high
quality capacitors, see Figure 39. If proper decoupling cannot be
achieved using a single capacitor, the user can use multiple
capacitors in parallel for each GND pin. A 20 F tantalum
capacitor must be used as the general decoupling capacitor for
the entire module. For recommended PCB layouts, including
those suitable for XFP modules, contact sales. For guidelines on
the surface-mount assembly of the ADN2530, consult the
Amkor Technology® "Application Notes for Surface Mount
Assembly of Amkor's MicroLeadFrame® (MLF®) Packages."
MSET
ALS
GND
BSET IBMON IBIAS GND
VCC
DATAP
DATAN
VCC
VCC
IMODP
IMODN
VCC
DATAP
DATAN
C1
C2
MSET
BSET
R5
750
ADN2530
Z
0
= 50
Z
0
= 50
Z
0
= 50
Z
0
= 50
GND
VCC
GND
VCC
TOSA
C4
C7
20
F
L2
L1
R1
+3.3V
VCC
VCC
VCC
VCC
VCC
TP1
C5
10nF
GND
GND
VCC
C6
10nF
GND
ALS
CPA
CPA
L7
L8
R4
L6
L5
R3
VCC
L3
L4
R2
VCC
Z
0
= 50
Z
0
= 50
C3
GND
05757-
034
V
CC
C8
100nF
Figure 39. Typical ADN2530 Application Circuit
ADN2530
Rev. A | Page 16 of 20
DESIGN EXAMPLE
This design example covers:
·
Headroom calculations for IBIAS, IMODP, and IMODN pins.
·
Calculation of the typical voltage required at the BSET
and MSET pins to produce the desired bias and
modulation currents.
·
Calculations of the IBIAS monitor accuracy over the IBIAS
current range.
This design example assumes that the impedance of the
TOSA is 60 , the forward voltage of the VCSEL at low current
is V
F
= 1.2 V, IBIAS = 10 mA, IMOD = 10 mA, and VCC = 3.3 V.
Headroom Calculations
To ensure proper device operation, the voltages on the IBIAS,
IMODP, and IMODN pins must meet the compliance voltage
specifications in Table 1.
Considering the typical application circuit shown in Figure 39,
the voltage at the IBIAS pin can be written as
V
IBIAS
=
VCC - V
F
- (
IBIAS × R
TOSA
) -
V
LA
where:
VCC is the supply voltage.
V
F
is the forward voltage across the laser at low current.
R
TOSA
is the resistance of the TOSA.
V
LA
is the dc voltage drop across L5, L6, L7, and L8.
For proper operation, the minimum voltage at the IBIAS pin
should be greater than 0.55 V, as specified by the minimum
IBIAS compliance specification in Table 1.
Assuming that the voltage drop across the 50 transmission lines
is negligible and that V
LA
= 0 V, V
F
= 1.2 V, and IBIAS = 10 mA,
V
IBIAS
= 3.3 - 1.2 - (0.01 × 60) = 1.5 V
V
IBIAS
= 1.5 V > 0.55 V, which satisfies the requirement
The maximum voltage at the IBIAS pin must be less than the
maximum IBIAS compliance specification as described by
V
COMPLIANCE_MAX
=
VCC - 0.75 - 22 × IBIAS (A)
For this example,
V
COMPLIANCE_MAX
= VCC 0.75 - 22 × 0.01 = 2.33 V
V
IBIAS
= 1.5 V < 2.33 V
, which satisfies the requirement
To calculate the headroom at the modulation current pins
(IMODP and IMODN), the voltage has a dc component equal
to VCC due to the ac-coupled configuration and a swing equal
to IMOD × 50 , as R
TOSA
< 100 . For proper operation of the
ADN2530, the voltage at each modulation output pin should be
within the normal operation region shown in Figure 35.
Assuming the dc voltage drop across L1, L2, L3, and L4 = 0 V
and IMOD = 10 mA, the minimum voltage at the modulation
output pins is equal to
VCC - (IMOD × 50)/2 = VCC - 0.25
VCC - 0.25 > VCC - 0.7 V, which satisfies the requirement
The maximum voltage at the modulation output pins is equal to
VCC + (IMOD × 50)/2 = VCC + 0.25
VCC + 0.25 < VCC + 0.7 V, which satisfies the requirement
Headroom calculations must be repeated for the minimum and
maximum values of the required IBIAS and IMOD ranges to
ensure proper device operation over all operating conditions.
BSET and MSET Pin Voltage Calculation
To set the desired bias and modulation currents, the BSET and
MSET pins of the ADN2530 must be driven with the appropriate
dc voltage. The voltage range required at the BSET pin to generate
the required IBIAS range can be calculated using the BSET voltage
to IBIAS gain specified in Table 1. Assuming that IBIAS = 10 mA
and the typical IBIAS/V
BSET
ratio of 20 mA/V, the BSET voltage
is given by
V
5
.
0
20
10
mA/V
20
(mA)
=
=
=
IBIAS
V
BSET
The BSET voltage range can be calculated using the required
IBIAS range and the minimum and maximum BSET voltage to
IBIAS gain values specified in Table 1.
The voltage required at the MSET pin to produce the desired
modulation current can be calculated using
K
IMOD
V
MSET
=
where
K is the MSET voltage to IMOD ratio.
The value of K depends on the actual resistance of the TOSA
and can be obtained from Figure 34. For a TOSA resistance of
60 , the typical value of K = 24 mA/V. Assuming that IMOD =
10 mA and using the preceding equation, the MSET voltage is
given by
V
42
.
0
24
10
mA/V
24
(mA)
=
=
=
IMOD
V
MSET
The MSET voltage range can be calculated using the required
IMOD range and the minimum and maximum K values. These can
be obtained from the minimum and maximum curves in Figure 34.
ADN2530
Rev. A | Page 17 of 20
IBIAS Monitor Accuracy Calculations
05457-041
0
0
1
2
3
4
5
6
25
20
15
10
5
IBIAS (mA)
ACCURACY
OF IBIAS
TO IBMON RATIO (%)
Figure 40. Accuracy of IBIAS to IBMON Ratio
This example assumes that the nominal value of IBIAS is 8 mA
and that the IBIAS range for all operating conditions is 4 mA to
14 mA. The accuracy of the IBIAS to IBMON ratio is given in
the Table 1 and is plotted in Figure 40.
Referring to Figure 40, the IBMON output current accuracy is
±4.3% for the minimum IBIAS of 4 mA and ±3.0% for the
maximum IBIAS value of 14 mA.
The accuracy of the IBMON output current as a percentage of
the nominal IBIAS is given by
%
15
.
2
mA
8
100
100
3
.
4
mA
4
_
±
=
×
=
MIN
Accuracy
IBMON
for the minimum IBIAS value, and by
%
25
.
5
mA
8
100
100
0
.
3
mA
14
_
±
=
×
=
MAX
Accuracy
IBMON
for the maximum IBIAS value. This gives a worse-case accuracy
for the IBMON output current of ±5.25% of the nominal IBIAS
value over all operating conditions. The IBMON output current
accuracy numbers can be combined with the accuracy numbers
for the 750 IBMON resistor (R
IBMON
) and any other error
sources to calculate an overall accuracy for the IBMON voltage.
ADN2530
Rev. A | Page 18 of 20
OUTLINE DIMENSIONS
1
0.50
BSC
0.60 MAX
PIN 1
INDICATOR
1.50 REF
0.50
0.40
0.30
0.25 MIN
0.45
2.75
BSC SQ
TOP
VIEW
12° MAX
0.80 MAX
0.65 TYP
SEATING
PLANE
PIN 1
INDICATOR
0.90
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
3.00
BSC SQ
*1.65
1.50 SQ
1.35
16
5
13
8
9
12
4
EXPOSED
PAD
(BOTTOM VIEW)
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 41. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
Branding
ADN2530YCPZ-WP
1
-40°C to +100°C
16-Lead LFCSP_VQ, 50-Piece Waffle Pack
CP-16-3
F08
ADN2530YCPZ-R2
1
-40°C to +100°C
16-Lead LFCSP_VQ, 250-Piece Reel
CP-16-3
F08
ADN2530YCPZ-REEL7
1
-40°C to +100°C
16-Lead LFCSP_VQ, 1500-Piece Reel
CP-16-3
F08
1
Z = Pb-free part.
ADN2530
Rev. A | Page 19 of 20
NOTES
ADN2530
Rev. A | Page 20 of 20
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D0545708/06(A)
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