REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

ADMCF328

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 2001

28-Lead Flash Memory

DSP Motor Controller with Current Sense

FUNCTIONAL BLOCK DIAGRAM

MEMORY BLOCK

PROGRAM

ROM

4K 24

PROGRAM

FLASH

4K 24

PROGRAM

RAM

512 24

DATA

MEMORY

512 16

VREF

ANALOG

INPUTS

16-BIT

THREE-

PHASE

PWM

POR

TIMER

SERIAL PORT

SPORT 1

9-BIT

PIO

2 8-BIT

AUX

PWM

WATCH-

DOG

TIMER

ADSP-2100 BASE

ARCHITECTURE

DATA

ADDRESS

GENERATORS

DAG 1 DAG 2

PROGRAM

SEQUENCER

ARITHMETIC UNITS

SHIFTER

MAC

ALU

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

2.5V

ISENSE

AMP

& TRIP

TARGET APPLICATIONS
Washing Machines, Refrigerator Compressors, Fans,

Pumps, Industrial Variable Speed Drives

MOTOR TYPES
Permanent Magnet Synchronous Motors (PMSM)
Brushless DC Motors (BDCM)

FEATURES
20 MIPS Fixed-Point DSP Core

Single Cycle Instruction Execution (50 ns)
ADSP-21xx Family Code Compatible
Independent Computational Units

ALU
Multiplier/Accumulator
Barrel Shifter

Multifunction Instructions
Single Cycle Context Switch
Powerful Program Sequencer

Zero Overhead Looping
Conditional Instruction Execution

Two Independent Data Address Generators

Memory Configuration

512 24-Bit Program Memory RAM
512 16-Bit Data Memory RAM
4K 24-Bit Program Memory ROM
4K 24-Bit Program Flash Memory

Three Independent Programmable Sectors
Security Lock Bit
10K Erase/Program Cycles

Three-Phase 16-Bit PWM Generator

16-Bit Center-Based PWM Generator
Programmable Dead Time and Narrow Pulse Deletion
Edge Resolution to 50 ns
150 Hz Minimum Switching Frequency
Double/Single Duty Cycle Update Mode Control
Programmable PWM Pulsewidth
Special Crossover Function for Brushless DC Motors
Individual Enable and Disable for Each PWM Output
High Frequency Chopping Mode for Transformer

Coupled Gate Drives

External

PWMTRIP Pin

Integrated ADC Subsystem

Five Analog Inputs Plus One Dedicated I

SENSE

Input

Acquisition Synchronized to PWM Switching Frequency
Internal Voltage Reference

9-Pin Digital I/O Port

Bit Configurable as Input or Output
Change of State Interrupt Support

Two 8-Bit Auxiliary PWM Timers

Synthesized Analog Output
Programmable Frequency
0% to 100% Duty Cycle
Two Programmable Operational Modes

Independent Mode/Offset Mode

16-Bit Watchdog Timer
Programmable 16-Bit Internal Timer with Prescaler
Double Buffered Synchronous Serial Port
Hardware Support for UART Emulation
Integrated Power-On Reset Function Options
28-Lead SOIC Package

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ADMCF328SPECIFICATIONS

= 5 V 5%, GND = 0 V, T

= 40 C to +85 C, CLKIN = 10 MHz,

unless otherwise noted)

ANALOG-TO-DIGITAL CONVERTER

Parameter

Min

Typ

Max

Unit

Conditions/Comments

Signal Input

0.3

3.5

V1, V2, VAUX0, VAUX1, VAUX2

0.4

SENSE

Resolution

Bits

Linearity Error

Bits

Zero Offset

+20

Channel-to-Channel Comparator Match

Comparator Delay

600

ADC High Level Input Current

µA

= 3.5 V

ADC Low Level Input Current

µA

= 0.0 V

NOTES

Resolution varies with PWM switching frequency (double update mode) 78.1 kHz = 8 bits, 4.9 kHz = 12 bits.

2.44 kHz sample frequency, V1, V2, VAUX0, VAUX1, VAUX2.

Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS

Parameter

Min

Typ

Max

Unit

Conditions/Comments

Low Level Input Voltage

0.8

High Level Input Voltage

Low Level Output Voltage

0.4

= 2 mA

Low Level Output Voltage

0.8

= 2 mA

High Level Output Voltage

= 0.5 mA

Low Level Input Current

120

µA

= 0 V

Low Level Input Current

µA

= 0 V

High Level Input Current

µA

= V

High Level Input Current

µA

= V

OZH

High Level Three-State Leakage Current

µA

= V

OZL

Low Level Three-State Leakage Current

µA

= 0

Low Level

PWMTRIP Current

µA

@ V

= Max, V

= 0 V

Supply Current (Idle)

Supply Current (Dynamic)

108

Supply Current (Programming)

123

NOTES

Output Pins PIO0PIO8, AH, AL, BH, BL, CH, CL.

XTAL Pin.

Internal Pull-Up,

RESET.

Internal Pull-Down,

PWMTRIP, PIO0PIO8.

Three stateable pins DT1, RFS1, TFS1, SCLK1.

Outputs not Switching.

Specifications subject to change without notice.

CURRENT SOURCE

Parameter

Min

Typ

Max

Unit

Conditions/Comments

Programming Resolution

Bits

Default Current

µA

ICONST_TRIM = 0x00

Tuned Current

100

105

µA

NOTES

For ADC Calibration.

0.3 V to 3.5 V ICONST Voltage.

Specifications subject to change without notice.

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ADMCF328

VOLTAGE REFERENCE

Parameter

Min

Typ

Max

Unit

Conditions/Comments

Voltage Level (V

REF

)

2.40

2.50

2.60

2.45

2.50

2.55

= 25

°C to 85°C SOIC

Output Voltage Drift

ppm/

°C

Specifications subject to change without notice.

SENSE

AMPLIFIERTRIP

Parameter

Min

Typ

Max

Unit

Conditions/Comments

SENSE

Gain

5.7

5.1

4.7

= 0.4 V to 0.0 V

SENSE

Current

320

+10

µA

= 0.4 V to V

1.0 V

SENSE

Input Offset Voltage

160

240

Trip Voltage (V

TRIP

)

0.70

0.57

0.45

Specifications subject to change without notice.

POWER-ON RESET

Parameter

Min

Typ

Max

Unit

Conditions/Comments

Reset Threshold (V

RST

)

3.2

3.7

4.2

Hysteresis (V

HYST

)

100

Reset Active Timeout Period (

RST

)

3.2

NOTES

CLKOUT Cycles.

Specifications subject to change without notice.

FLASH MEMORY

Parameter

Min

Typ

Max

Unit

Conditions/Comments

Endurance

10,000

Cycles

Cycle = Erase/Program/Verify

Data Retention

Years

Program and Erase Operating Temperature

Read Operating Temperature

+85

Specifications subject to change without notice.

ADMCF328

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CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADMCF328 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

Supply Voltage (V

) . . . . . . . . . . . . . . . . . . 0.3 V to +7.0 V

Input Voltage . . . . . . . . . . . . . . . . . . . . . 0.3 V to V

+ 0.3 V

Output Voltage Swing . . . . . . . . . . . . . . 0.3 V to V

+ 0.3 V

Flash Memory Erase or/Program

Temperature Range (Ambient) . . . . . . . . . . . . 0

°C to 85°C

Operating Temperature Range (Ambient) . . . 40

°C to +85°C

Storage Temperature Range . . . . . . . . . . . . 65

°C to +150°C

Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . . 280

°C

*Stresses greater than those listed may cause permanent damage to the device.

These are stress ratings only; functional operation of the device at these or any
other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ORDERING GUIDE

Temperature

Instruction

Package

Model

Range

Rate

Description

Option

ADMCF328BR

°C to +85°C

20 MHz

28-Lead Wide Body (SOIC)

R-28

ADMCF328-EVALKIT

Development Tool Kit

PIN FUNCTION DESCRIPTIONS

Pin

No.

Name

Type

PIO6/CLKOUT

I/O

PIO5/RFS1

I/O

PIO4/DR1A

I/O

PIO3/SCLK1

I/O

PIO2/DR1B

I/O

PIO1/DT1

I/O

PIO0/TFS1

I/O

CLKIN

XTAL

SUP

PWMTRIP

SENSE

VAUX0

VAUX1

VAUX2

ICONST

GND

RESET

PIO8/AUX0

I/O

PIO7/AUX1

I/O

PIN CONFIGURATION

TOP VIEW

(Not to Scale)

ADMCF328

PIO6/CLKOUT

PIO7/AUX1

PIO5/RFS1

PIO8/AUX0

PIO4/DR1A

PIO3/SCLK1

PIO2/DR1B

PIO1/DT1

PIO0/TFS1

CLKIN

XTAL

RESET

GND

PWMTRIP

ICONST

SENSE

VAUX2

VAUX1

VAUX0

ADMCF328

REV. 0

GENERAL DESCRIPTION

The ADMCF328 is a low cost, single-chip DSP-based control-
ler, suitable for permanent magnet synchronous motors, and
brushless dc motors. The ADMCF328 integrates a 20 MIPS,
fixed-point DSP core with a complete set of motor control and
system peripherals that permits fast, efficient development of
motor controllers.

The DSP core of the ADMCF328 is the ADSP-2171, which is
completely code-compatible with the ADSP-21xx DSP family
and combines three computational units, data address generators
and a program sequencer. The computational units comprise
an ALU, a multiplier/accumulator (MAC) and a barrel shifter.
The ADSP-2171 adds new instructions for bit manipulation,
multiplication (

× squared), biased rounding and global inter-

rupt masking.

The system peripherals are the power-on reset circuit (POR),
the watchdog timer and a synchronous serial port. The serial
port is configurable, and double buffered, with hardware sup-
port for UART and SCI port emulation.

The ADMCF328 provides 512

× 24-bit program memory RAM,

× 24-bit program memory ROM, 4K × 24-bit program

FLASH memory, and 512

× 16-bit data memory RAM. The

user code will be stored and executed from the flash memory.
The program and data memory RAM can be used for dynamic
data storage or can be loaded through the serial port from an
external device as in other ADMCxxx family parts. The pro-
gram memory ROM contains a monitor function as well as
useful routines for erasing, programming, and verifying the
flash memory.

The motor control peripherals of the ADMCF328 provide a 12-bit
analog data acquisition system with five analog input channels,
one dedicated I

SENSE

function (combining internal amplification,

sampling and overcurrent PWM shutdown features), and an
internal voltage reference. In addition, a three-phase, 16-bit,
center-based PWM generation unit can be used to produce high
accuracy PWM signals with minimal processor overhead. The
ADMCF328 also contains two auxiliary PWM outputs and
nine lines of digital I/O.

Because the ADMCF328 has a limited number of pins, functions
such as the auxiliary PWM and the serial communication port
are multiplexed with the nine programmable input/output (PIO)
pins. The pin functions can be independently selected to allow
maximum flexibility for different applications.

PM ROM

4K 24

PM RAM

512 24

BUS

EXCHANGE

COMPANDING

CIRCUITRY

DATA

ADDRESS

GENERATOR

DATA

ADDRESS

GENERATOR

DM RAM
512 16

R BUS

DMA BUS

PMA BUS

DMD BUS

PMD BUS

INSTRUCTION

REGISTER

INPUT REGS

OUTPUT REGS

SHIFTER

CONTROL

LOGIC

SERIAL

PORT

RECEIVE REG

TRANSMIT REG

TIMER

INPUT REGS

OUTPUT REGS

MAC

INPUT REGS

OUTPUT REGS

ALU

PROGRAM

SEQUENCER

FLASH

PROGRAM

MEMORY

4K 24

Figure 3. DSP Core Block Diagram

ADMCF328

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DSP CORE ARCHITECTURE OVERVIEW

Figure 3 is an overall block diagram of the DSP core of the
ADMCF328, which is based on the fixed-point ADSP-2171.
The flexible architecture and comprehensive instruction set of
the ADSP-2171 allow the processor to perform multiple operations
in parallel. In one processor cycle (50 ns with a 10 MHz CLKIN)
the DSP core can:

· Generate the next program address.
· Fetch the next instruction.
· Perform one or two data moves.
· Update one or two data address pointers.
· Perform a computational operation.

This all takes place while the processor continues to:

· Receive and transmit through the serial port.
· Decrement the interval timer.
· Generate three-phase PWM waveforms for a power inverter.
· Generate two signals using the 8-bit auxiliary PWM timers.
· Acquire four analog signals.
· Decrement the watchdog timer.

The processor contains three independent computational units:
the arithmetic and logic unit (ALU), the multiplier/accumulator
(MAC) and the shifter. The computational units process 16-bit
data directly and have provisions to support multiprecision com-
putations. The ALU performs a standard set of arithmetic and
logic operations as well as providing support for division primitives.
The MAC performs single-cycle multiply, multiply/add, and
multiply/subtract operations with 40 bits of accumulation. The
shifter performs logical and arithmetic shifts, normalization,
denormalization and derive-exponent operations. The shifter can
be used to efficiently implement numeric format control, including
floating-point representations.

The internal result (R) bus directly connects the computational
units so that the output of any unit may be the input of any unit
on the next cycle.

A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps and
subroutine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADMCF328 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain the loop.

Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches from data memory and pro-
gram memory. Each DAG maintains and updates four address
pointers (I registers). Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value in one of
four modify (M registers). A length value may be associated with
each pointer (L registers) to implement automatic modulo
addressing for circular buffers. The circular buffering feature is
also used by the serial ports for automatic data transfers to and

from on-chip memory. DAG1 generates only data memory
address and provides an optional bit-reversal capability. DAG2
may generate either program or data memory addresses but has
no bit-reversal capability.

Efficient data transfer is achieved with the use of five internal
buses:

· Program memory address (PMA) bus.
· Program memory data (PMD) bus.
· Data memory address (DMA) bus.
· Data memory data (DMD) bus.
· Result (R) bus.

Program Memory on the ADMCF328 can either be internal
(on-chip RAM) or external (Flash). Internal program memory
can store both instructions and data, permitting the ADMCF328
to fetch two operands in a single instruction cycle--one from
program memory and one from data memory. Operation from
external program memory is described in detail in the ADSP-
2100 Family User's Manual, Third Edition.

The ADMCF328 writes data from its 16-bit registers to the
24-bit program memory using the PX register to provide the
lower eight bits. When it reads data (not instructions) from
24-bit program memory to a 16-bit data register, the lower
eight bits are placed in the PX register.

The ADMCF328 can respond to a number of distinct DSP core
and peripheral interrupts. The DSP interrupts comprise a serial
port receive interrupt, a serial port transmit interrupt, a timer
interrupt, and two software interrupts. Additionally, the motor
control peripherals include two PWM interrupts and a PIO
interrupt.

The serial port (SPORT1) provides a complete synchronous
serial interface with optional companding in hardware and a
wide variety of framed and unframed data transmit and receive
modes of operation. SPORT1 can generate an internal program-
mable serial clock or accept an external serial clock.

A programmable interval counter is also included in the DSP
core and can be used to generate periodic interrupts. A 16-bit
count register (TCOUNT) is decremented every n processor
cycles, where n1 is a scaling value stored in the 8-bit TSCALE
register. When the value of the counter reaches zero, an interrupt
is generated, and the count register is reloaded from a 16-bit
period register (TPERIOD).

The ADMCF328 instruction set provides flexible data moves
and multifunction instructions (one or two data moves within a
computation) that will execute from internal program memory
RAM. The ADMCF328 assembly language uses an algebraic
syntax for ease of coding and readability. A comprehensive set
of development tools support program development. For further
information on the DSP core, refer to the ADSP-2100 Family
User's Manual, Third Edition, with particular reference to the
ADSP-2171.

ADMCF328

REV. 0

Serial Port

The ADMCF328 incorporates a complete synchronous serial port
(SPORT1) for serial communication and multiprocessor com-
munication. The following is a brief list of capabilities of the
ADMCF328 SPORT1. Refer to the ADSP-2100 Family User's
Manual, Third Edition, for further details.

· SPORT1 is bidirectional and has a separate, double-buffered

transmit and receive section.

· SPORT1 can use an external serial clock or generate its own

serial clock internally.

· SPORT1 has independent framing for the receive and trans-

mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame synchronization signals are active high or inverted,
with either of two pulsewidths and timings.

· SPORT1 supports serial data word lengths from 3 bits to 16 bits

and provides optional A-law and

µ-law companding accord-

ing to ITU (formerly CCITT) recommendation G.711.

· SPORT1 receive and transmit sections can generate unique

interrupts on completing a data word transfer.

· SPORT1 can receive and transmit an entire circular buffer of

data with only one overhead cycle per data word. An interrupt is
generated after a data buffer transfer.

· SPORT1 can be configured to have two external interrupts

(IRQ0 and IRQ1), and the Flag In and Flag Out signals.
The internally generated serial clock may still be used in
this configuration.

· SPORT1 has two data receive pins (DR1A and DR1B), which

are internally multiplexed onto the one DR1 port of the
SPORT1. The particular data receive pin selected is deter-
mined by a bit in the MODECTRL register.

PIN FUNCTION DESCRIPTION

The ADMCF328 is available in a 28-lead SOIC package.
Table I describes the pins.

Table I. Pin List

Pin Group

# of Input/

Name

Pins Output Function

RESET

Processor Reset Input

SPORT1

I/O

Serial Port 1 Pins (TFS1, RFS1,
DT1, DR1A, DR1B, SCLK1)

CLKOUT

Processor Clock Output

CLKIN, XTAL

I, O

External Clock or Quartz
Crystal Connection Point

PIO0PIO8

I/O

Digital I/O Port Pins

AUX0AUX1

Auxiliary PWM Outputs

AHCL

PWM Outputs

PWMTRIP

PWM Trip Signal

V1V2

Analog Inputs

VAUX0VAUX2 3

Auxiliary Analog Input

SENSE

Current Sense Amplifier Input

ICONST

ADC Constant Current Source

Power Supply

GND

Ground

NOTE

Multiplexed pins, individually selectable through PIOSELECT and PIODATA1

registers.

INTERRUPT OVERVIEW

The ADMCF328 can respond to 16 different interrupt sources
with minimal overhead, five of which are internal DSP core
interrupts and 11 from the motor control peripherals. The five
DSP core interrupts are SPORT1 receive (or

IRQ0) and trans-

mit (or

IRQ1), the internal timer, and two software interrupts.

The motor control peripheral interrupts are the nine program-
mable I/Os and two from the PWM (PWMSYNC pulse and
PWMTRIP). All motor control interrupts are multiplexed into the
DSP core through the peripheral

IRQ2 interrupt. The interrupts

are internally prioritized and individually maskable. A detailed
description of the entire interrupt system of the ADMCF328 is
presented later, following a more detailed description of each
peripheral block.

MEMORY MAP

The ADMCF328 has two distinct memory types: program memory
and data memory. In general, program memory contains user
code and coefficients, while the data memory is used to store
variables and data during program execution. Three kinds of
program memory are provided on the ADMCF328: RAM, ROM,
and flash memory. The motor control peripherals are memory
mapped into a region of the data memory space starting at 0x2000.
The complete program and data memory maps are given in
Tables II and III, respectively.

Table II. Program Memory Map

Memory

Address Range

Type

Function

0x00000x002F

RAM

Internal Vector Table

0x00300x01FF

RAM

User Program Memory

0x02000x07FF

Reserved

0x08000x17FF

ROM

Reserved Program Memory

0x18000x1FFF

Reserved

0x20000x20FF

FLASH

User Program Memory
Sector 0

0x21000x21FF

FLASH

User Program Memory
Sector 1

0x22000x2FFF

FLASH

User Program Memory
Sector 2

0x30000x3FFF

Reserved

Table III. Data Memory Map

Memory

Address Range

Type

Function

0x00000x1FFF

Reserved

0x20000x20FF

Memory Mapped Registers

0x21000x37FF

Reserved

0x38000x39FF

RAM

User Data Memory

0x3A000x3BFF

RAM

Reserved

0x3C000x3FFF

Memory Mapped Registers

ADMCF328

REV. 0

FLASH MEMORY SUBSYSTEM

The ADMCF328 has 4K

× 24-bit of user-programmable, non-

volatile flash memory. A flash programming utility is provided
with the development tools, which performs the basic device
programming operations: erase, program, and verify.

The flash memory array is partitioned into three asymmetrically
sized sectors of 256 words, 256 words, and 3584 words, labeled
Sector 0, Sector 1, and Sector 2, respectively. These sectors are
mapped into external program memory address space.

Four flash memory interface registers are connected to the DSP.
These 16-bit registers are mapped into the register area of data
memory space. They are named Flash Memory Control Register
(FMCR), Flash Memory Address Register (FMAR), Flash
Memory Data Register Low (FMDRL) and Flash Memory Data
Register High (FMDRH). These registers are diagrammed later in
this data sheet. They are used by the flash memory programming
utility. The user program may read these registers, but should not
modify them directly. The flash programming utility provides
a complete interface to the flash memory.

Special Flash Registers

The flash module has four nonvolatile 8-bit registers called Special
Flash Registers (SFRs) which are accessible independently of the
main flash array, via the flash programming utility. These regis-
ters are for general purpose, nonvolatile storage. When erased,
the Special Flash Registers contain all 0s. To read Special Flash
Registers from the user program, call the read_reg routine con-
tained in ROM. Refer to the (ADMCF32x DSP Motor Controller
Developers Reference Manual) for an example.

Boot-from-Flash Code

A security feature is available in the form of a code that, when set,
causes the processor to execute the program in flash memory upon
power-up or reset. In this mode, the flash programming utility
and debugger are unable to communicate with the ADMCF328.
Consequently, the contents of the flash memory can neither
be programmed nor read.

The boot-from-flash code may be set via the flash programming
utility, when the user's program is thoroughly tested and loaded
into flash program memory at address 0x2200. The user's program
must contain a mechanism for clearing the boot-from-flash code
if reprogramming the flash memory is desired. The only way
to clear boot-from-flash is from within the user program, by calling
the flash_init or auto_erase_reg routines that are included in
the ROM. The user program must be signaled in some way to call
the necessary routine to clear the boot-from-flash code. An example
would be to detect a high level on a PIO pin during start-up initial-
ization and then call the flash_init or auto_erase_routine. The
flash_init routine will erase the entire user program in flash
memory before clearing the boot-from-flash code, thus ensuring
the security of the user program. If security is not a concern, the
auto_erase_reg routine can be used to clear the boot-from-flash
code while leaving the user program intact.

Refer to the ADMCF32x DSP Motor Controller Developer's Reference
Manual for further instructions and an example of using the
boot-from-flash code.

FLASH PROGRAM BOOT SEQUENCE

On power-up or reset, the processor begins instruction execu-
tion at address 0x0800 of internal program ROM. The ROM

monitor program that is located there checks the Boot-from-
Flash code. If that code is set, the processor jumps to location
0x2200 in external flash program memory, where it expects to
find the user's application program.

If the Boot-from-Flash code is not set, the monitor attempts
to boot from an external device as described in the ADMCF32x
DSP Motor Controller Developers Reference Manual

SYSTEM INTERFACE

Figure 4 shows a basic system configuration for the ADMCF328
with an external crystal.

ADMCF328

XTAL

CLKIN

10MHz

CLKOUT

RESET

22pF

Figure 4. Basic System Configuration

Clock Signals

The ADMCF328 can be clocked either by a crystal or a TTL-
compatible clock signal. For normal operation, the CLKIN
input cannot be halted, changed during operation, or operated
below the specified minimum frequency. If an external clock is
used, it should be a TTL-compatible signal running at half
the instruction rate. The signal is connected to the CLKIN pin
of the ADMCF328. In this mode, with an external clock signal,
the XTAL pin must be left unconnected. The ADMCF328 uses
an input clock with a frequency equal to half the instruction
rate; a 10 MHz input clock yields a 50 ns processor cycle (which
is equivalent to 20 MHz). Normally, instructions are executed
in a single processor cycle. All device timing is relative to the
internal instruction rate, which is indicated by the CLKOUT
signal when enabled.

Because the ADMCF328 includes an on-chip oscillator feedback
circuit, an external crystal may be used instead of a clock source, as
shown in Figure 4. The crystal should be connected across the
CLKIN and XTAL pins, with two capacitors as shown in Figure 4.
A parallel-resonant, fundamental frequency, microprocessor-grade
crystal should be used. A clock output signal (CLKOUT) is
generated by the processor at the processor's cycle rate of twice
the input frequency.

Reset

The ADMCF328 DSP core and peripherals must be correctly
reset when the device is powered up to assure proper initialization.
The ADMCF328 contains an integrated power-on reset (POR)
circuit that provides a complete system reset on power-up and
power-down. The POR circuit monitors the voltage on the
ADMCF328 V

pin and holds the DSP core and peripherals

in reset while V

is less than the threshold voltage level, V

RST

When this voltage is exceeded, the ADMCF328 is held in reset
for an additional 2

DSP clock cycles (t

RST

in Figure 5). On

power-down, when the voltage on the V

pin falls below

RST

HYST

, the ADMCF328 will be reset. Also, if the external

RESET pin is actively pulled low at any time after power-up, a
complete hardware reset of the ADMCF328 is initiated.

ADMCF328

REV. 0

RST

RESET

RST 

HYST

RST

Figure 5. Power-On Reset Operation

The ADMCF328 reset sets all internal stack pointers to the
empty stack condition, masks all interrupts, clears the MSTAT
register and performs a full reset of all of the motor control periph-
erals. Following a power-up, it is possible to initiate a DSP
core and motor control peripheral reset by pulling the

RESET

pin low. The

RESET signal must meet the minimum pulse-

width specification, t

RSP

. Following the reset sequence, the

DSP core starts executing code from the internal PM ROM
located at 0x0800.

DSP Control Registers

The DSP core has a system control register, SYSCNTL, memory
mapped at DM (0x3FFF). SPORT1 is configured as a serial
port when Bit 10 is set, or as flags and interrupt lines when this
bit is cleared. For proper operation of the ADMCF328, all other
bits in this register must be cleared.

The DSP core has a wait state control register, MEMWAIT,
memory mapped at DM (0x3FFE). The default value of this
resister is 0xFFFF. For proper operation of the ADMCF328,
this register must always contain the value 0x8000 (which is the
default).

The configuration of both the SYSCNTL and MEMWAIT reg-
isters of the ADMCF328 are shown at the end of the data sheet.

THREE-PHASE PWM CONTROLLER
Overview

The PWM generator block of the ADMCF328 is a flexible,
programmable, three-phase PWM waveform generator that can
be programmed to generate the required switching patterns to
drive a three-phase voltage source inverter for ac induction
motors (ACIM) or permanent magnet synchronous motors
(PMSM). In addition, the PWM block contains special functions
that considerably simplify the generation of the required PWM
switching patterns for control of electronically commutated motors
(ECM) or brushless dc motors (BDCM).

The PWM generator produces three pairs of active high PWM
signals on the six PWM output pins (AH, AL, BH, BL, CH, and
CL). The six PWM output signals consist of three high side
drive signals (AH, BH, and CH) and three low side drive signals
(AL, BL, and CL). The switching frequency, dead time, and
minimum pulsewidths of the generated PWM patterns are
programmable using, respectively, the PWMTM, PWMDT, and
PWMPD registers. In addition, three registers (PWMCHA,
PWMCHB, and PWMCHC) control the duty cycles of the three
pairs of PWM signals.

Each of the six PWM output signals can be enabled or disabled
by separate output enable bits of the PWMSEG register. In
addition, three control bits of the PWMSEG register permit

crossover of the two signals of a PWM pair for easy control of
ECM or BDCM. In crossover mode, the PWM signal destined
for the high side switch is diverted to the complementary low
side output, and the signal destined for the low side switch is
diverted to the corresponding high side output signal.

In many applications, there is a need to provide an isolation barrier
in the gate-drive circuits that turn on the power devices of the
inverter. In general, there are two common isolation techniques:
optical isolation using optocouplers, and transformer isolation
using pulse transformers. The PWM controller of the ADMCF328
permits mixing of the output PWM signals with a high frequency
chopping signal to permit an easy interface to such pulse trans-
formers. The features of this gate-drive chopping mode can be
controlled by the PWMGATE register. There is an 8-bit value
within the PWMGATE register that directly controls the chopping
frequency. In addition, high frequency chopping can be indepen-
dently enabled for the high side and the low side outputs using
separate control bits in the PWMGATE register.

The PWM generator is capable of operating in two distinct modes:
single update mode or double update mode. In single update
mode, the duty cycle values are programmable only once per
PWM period, so that the resultant PWM patterns are symmetri-
cal about the midpoint of the PWM period. In the double update
mode, a second updating of the PWM duty cycle values is imple-
mented at the midpoint of the PWM period. In this mode, it is
possible to produce asymmetrical PWM patterns that produce
lower harmonic distortion in three-phase PWM inverters. This
technique also permits the closed-loop controller to change the
average voltage applied to the machine winding at a faster rate,
allowing wider closed-loop bandwidths to be achieved. The operat-
ing mode of the PWM block (single or double update mode) is
selected by a control bit in MODECTRL register.

The PWM generator of the ADMCF328 also provides an internal
signal that synchronizes the PWM switching frequency to the
A/D operation. In single update mode, a PWMSYNC pulse is
produced at the start of each PWM period. In double update
mode, an additional PWMSYNC pulse is produced at the mid-
point of each PWM period. The width of the PWMSYNC pulse
is programmable through the PWMSYNCWT register.

The PWM signals produced by the ADMCF328 can be shut
off in a number of different ways. First, there is a dedicated
asynchronous PWM shutdown pin,

PWMTRIP, which, when

brought LO, instantaneously places all six PWM outputs in the
OFF state. In addition, PWM shutdown is initiated when the
voltage on the analog input pin (I

SENSE

) is pulled below the

trip voltage level, corresponding to an over-current fault. Because
these two hardware shutdown mechanisms are asynchronous,
and the associated PWM disable circuitry does not use clocked
logic, the PWM will shut down even if the DSP clock is not run-
ning. The PWM system may also be shut down from software
by writing to the PWMSWT register.

Status information about the PWM system of the ADMCF328
is available to the user in the SYSSTAT register. In particular,
the state of

PWMTRIP is available, as well as a status bit that

indicates whether operation is in the first half or the second half
of the PWM period.

ADMCF328

REV. 0

A functional block diagram of the PWM controller is shown in
Figure 6. The generation of the six output PWM signals on pins
AH to CL is controlled by four important blocks:

· The three-phase PWM timing unit, which is the core of the

PWM controller, generates three pairs of complemented and
dead-time-adjusted center-based PWM signals.

· The output control unit allows the redirection of the outputs

of the three-phase timing unit for each channel to either the
high side or the low side output. In addition, the output con-
trol unit allows individual enabling/disabling of each of the six
PWM output signals.

· The GATE drive unit provides the high chopping frequency

and its subsequent mixing with the PWM signals.

· The PWM shutdown controller manages the three PWM

shutdown modes (via the

PWMTRIP pin, the analog block or

the PWMSWT register) and generates the correct

RESET

signal for the Timing Unit.

· The PWM controller is driven by a clock at the same frequency

as the DSP instruction rate, CLKOUT, and is capable of
generating two interrupts to the DSP core. One interrupt is
generated on the occurrence of a PWMSYNC pulse, and
the other is generated on the occurrence of any PWM shut-
down action.

Three-Phase Timing Unit

The 16-bit three-phase timing unit is the core of the PWM con-
troller and produces three pairs of pulsewidth modulated signals
with high resolution and minimal processor overhead. There are
four main configuration registers (PWMTM, PWMDT, PWMPD
and PWMSYNCWT) that determine the fundamental charac-
teristics of the PWM outputs. In addition, the operating mode
of the PWM (single or double update mode) is selected by Bit 6

of the MODECTRL register. These registers, in conjunction with
the three 16-bit duty cycle registers (PWMCHA, PWMCHB and
PWMCHC), control the output of the three-phase timing unit.

PWM Switching Frequency: PWMTM Register

The PWM switching frequency is controlled by the PWM
period register, PWMTM. The fundamental timing unit of
the PWM controller is t

= 1/f

CLKOUT

where f

CLKOUT

is the

CLKOUT frequency (DSP instruction rate). Therefore, for a
20 MHz CLKOUT, the fundamental time increment is 50 ns.
The value written to the PWMTM register is effectively the
number of t

clock increments in half a PWM period. The

required PWMTM value is a function of the desired PWM
switching frequency (f

PWM

) and is given by:

PWMTM

CLKOUT

PWM

CLKIN

PWM

Therefore, the PWM switching period, T

, can be written as:

PWMTM

= ×

For example, for a 20 MHz CLKOUT and a desired PWM
switching frequency of 10 kHz (T

= 100

µs), the correct value

to load into the PWMTM register is:

PWMTM

x E

1000

0 3 8

The largest value that can be written to the 16-bit PWMTM
register is 0xFFFF = 65,535, which corresponds to a minimum
PWM switching frequency of:

PWM,min

65 535

153

for a CLKOUT frequency of 20 MHz.

PWMTRIP

PWMSWT (0)

OVER

CURRENT

TRIP

PWM SHUTDOWN CONTROLLER

ANALOG BLOCK

PWMTRIP

SENSE

PWMSEG (8...0)

OUTPUT

CONTROL

UNIT

GATE

DRIVE

UNIT

CLK

PWM DUTY CYCLE

REGISTERS

PWM CONFIGURATION

REGISTERS

TO INTERRUPT
CONTROLLER

THREE-PHASE

PWM TIMING

UNIT

CLK

RESET

SYNC

PWMSYNC

CLKOUT

AH
AL
BH

PWMGATE (9...0)

PWMTM (15...0)
PWMDT (9...0)
PWMPD (15...0)
PWMSYNCWT (7...0)
MODECTRL (6)

PWMCHA (15...0)
PWMCHB (15...0)
PWMCHC (15...0)

Figure 6. Overview of the PWM Controller of the ADMCF328

ADMCF328

REV. 0

PWM Switching Dead Time: PWMDT Register

The second important PWM block parameter that must be
initialized is the switching dead time. This is a short delay time
introduced between turning off one PWM signal (for example
AH) and turning on its complementary signal, AL. This short
time delay is introduced to permit the power switch being turned
off to completely recover its blocking capability before the
complementary switch is turned on. This time delay prevents a
potentially destructive short-circuit condition from developing
across the dc link capacitor of a typical voltage source inverter.

Dead time is controlled by the PWMDT register. The dead
time is inserted into the three pairs of PWM output signals. The
dead time, T

, is related to the value in the PWMDT register by:

PWMDT

CLKOUT

× ×

= ×

Therefore, a PWMDT value of 0x00A (= 10), introduces a 1

µs

delay between the turn-off of any PWM signal (for example AH)
and the turn-on of its complementary signal (AL). The amount
of the dead time can therefore be programmed in increments of
2 t

(or 100 ns for a 20 MHz CLKOUT). The PWMDT register

is a 10-bit register. For a CLKOUT rate of 20 MHz its maximum
value of 0x3FF (= 1023) corresponds to a maximum programmed
dead time of:

Dmax

= 1023

× 2 × t

= 1023

× 2 × 50 × 10

sec

= 102

µs

The dead time can be programmed to zero by writing 0 to the
PWMDT register.

PWM Operating Mode: MODECTRL and SYSSTAT Registers

The PWM controller of the ADMCF328 can operate in two dis-
tinct modes: single update mode and double update mode. The
operating mode of the PWM controller is determined by the
state of Bit 6 of the MODECTRL register. If this bit is cleared, the
PWM operates in the single update mode. Setting Bit 6 places
the PWM in the double update mode. By default, following
either a peripheral reset or power-on, Bit 6 of the MODECTRL
register is cleared. This means that the default operating mode
is single update mode.

In single update mode, a single PWMSYNC pulse is produced
in each PWM period. The rising edge of this signal marks
the start of a new PWM cycle and is used to latch new values
from the PWM configuration registers (PWMTM, PWMDT,
PWMPD, and PWMSYNCWT) and the PWM duty cycle
registers (PWMCHA, PWMCHB, and PWMCHC) into the
three-phase timing unit. The PWMSEG register is also latched
into the output control unit on the rising edge of the PWMSYNC
pulse. In effect, this means that the parameters of the PWM
signals can be updated only once per PWM period at the start of
each cycle. Thus, the generated PWM patterns are symmetrical
about the midpoint of the switching period.

In double update mode, there is an additional PWMSYNC pulse
produced at the midpoint of each PWM period. The rising edge
of this new PWMSYNC pulse is again used to latch new values
of the PWM configuration registers, duty cycle registers and the
PWMSEG register. As a result, it is possible to alter both the
characteristics (switching frequency, dead time, minimum pulse-
width and PWMSYNC pulsewidth) and the output duty cycles
at the midpoint of each PWM cycle. Consequently, it is pos-
sible to produce PWM switching patterns that are no longer

symmetrical about the midpoint of the period (asymmetrical
PWM patterns).

In the double update mode, operation in the first half or the
second half of the PWM cycle is indicated by Bit 3 of the
SYSSTAT register. In double update mode, this bit is cleared
during operation in the first half of each PWM period (between
the rising edge of the original PWMSYNC pulse and the rising
edge of the new PWMSYNC pulse, which is introduced in
double update mode). Bit 3 of the SYSSTAT register is set
during the second half of each PWM period. If required, a user
may determine the status of this bit during a PWMSYNC inter-
rupt service routine.

The advantages of the double update mode are that lower har-
monic voltages can be produced by the PWM process and wider
control bandwidths are possible. However, for a given PWM
switching frequency, the PWMSYNC pulses occur at twice the
rate in the double update mode. Because new duty cycle values
must be computed in each PWMSYNC interrupt service routine,
there is a larger computational burden on the DSP in the double
update mode.

Width of the PWMSYNC Pulse: PWMSYNCWT Register

The PWM controller of the ADMCF328 produces an internal
PWM synchronization pulse at a rate equal to the PWM switching
frequency in single update mode and at twice the PWM frequency
in the double update mode. This PWMSYNC synchronizes
the operation of the PWM unit with the A/D converter system.
The width of this PWMSYNC pulse is programmable by the
PWMSYNCWT register. The width of the PWMSYNC pulse,
T

PWMSYNC

, is given by:

PWMSYNCWT

PWMSYNC

(

)

which means that the width of the pulse is programmable from t

to 256 t

(corresponding to 50 ns to 12.8

µs for a CLKOUT rate

of 20 MHz). Following a reset, the PWMSYNCWT register con-
tains 0x27 (= 39) so that the default PWMSYNC width is 2.0

µs.

PWM Duty Cycles: PWMCHA, PWMCHB, PWMCHC
Registers

The duty cycles of the six PWM output signals are controlled
by the three duty cycle registers, PWMCHA, PWMCHB, and
PWMCHC. The integer value in the register PWMCHA controls
the duty cycle of the signals on AH and AL. PWMCHB controls
the duty cycle of the signals on BH and BL, and PWMCHC
controls the duty cycle of the signals on CH and CL. The duty
cycle registers are programmed in integer counts of the funda-
mental time unit, t

, and define the desired on-time of the

high-side PWM signal produced by the three-phase timing unit
over half the PWM period. The switching signals produced by
the three-phase timing unit are also adjusted to incorporate the
programmed dead time value in the PWMDT register.

The PWM is center-based. This means that in single update mode
the resulting output waveforms are symmetrical and centered in
the PWMSYNC period. Figure 7 presents a typical PWM tim-
ing diagram illustrating the PWM-related registers' (PWMCHA,
PWMTM, PWMDT, and PWMSYNCWT) control over the
waveform timing in both half cycles of the PWM period. The
magnitude of each parameter in the timing diagram is determined
by multiplying the integer value in each register by t

(typically

50 ns). It may be seen in the timing diagram how dead time is
incorporated into the waveforms by moving the switching edges
away from the instants set by the PWMCHA register.

ADMCF328

REV. 0

PWMCHA

2 PWMDT

PWMSYNCWT + 1

PWMCHA

PWMTM

PWMSYNC

SYSSTAT (3)

2 PWMDT

Figure 7. Typical PWM Outputs of Three-Phase Timing
Unit in Single Update Mode

Each switching edge is moved by an equal amount (PWMDT
× t

) to preserve the symmetrical output patterns. The PWMSYNC

pulse, whose width is set by the PWMSYNCWT register, is also
shown. Bit 3 of the SYSSTAT register indicates which half cycle
is active. This can be useful in double update mode, as will be
discussed later.

The resultant on-times of the PWM signals shown in Figure 7
may be written as:

PWMCHA

PWMDT

PWMTM

PWMCHA

PWMDT

= ×

(

)

(

)

The corresponding duty cycles are:

PWMCHA

PWMDT

PWMTM

PWMCHA

PWMDT

PWMTM

Obviously, negative values of T

and T

are not permitted

because the minimum permissible value is zero, corresponding
to a 0% duty cycle. In a similar fashion, the maximum value is
T

, corresponding to a 100% duty cycle.

The output signals from the timing unit for operation in double
update mode are shown in Figure 8. This illustrates a completely
general case where the switching frequency, dead time and duty
cycle are all changed in the second half of the PWM period. Of
course, the same value for any or all of these quantities could be
used in both halves of the PWM cycle. However, it can be seen
that there is no guarantee that symmetrical PWM signals will be
produced by the timing unit in this double update mode. Addi-
tionally, it is seen that the dead time is inserted into the PWM
signals in the same way as in the single update mode.

PWMCHA

PWMSYNCWT

+ 1

PWMCHA

PWMTM

PWMSYNCWT

+ 1

PWMSYNC

SYSSTAT (3)

2 PWMDT

Figure 8. Typical PWM Outputs of Three-Phase Timing
Unit in Double Update Mode

In general, the on-times of the PWM signals in double update
mode are defined by:

= (PWMCHA

+ PWMCHA

PWMDT

)

× t

= (PWMTM

+ PWMTM

PWMCHA

PWMDT

)

× t

where the subscript 1 refers to the value of that register during
the first half cycle and the subscript 2 refers to the value during
the second half cycle. The corresponding duty cycles are:

PWMCHA

PWMTM

PWMDT

PWMTM

PWMCHA

PWMTM

PWMCHA

PWMDT

PWMTM

+
+

(

)

(

)

because for the completely general case in double update mode,
the switching period is given by:

= (PWMTM

+ PWMTM

)

× t

Again, the values of T

and T

are constrained to lie between

zero and T

PWM signals similar to those illustrated in Figure 7 and Figure
8 can be produced on the BH, BL, CH, and CL outputs by pro-
gramming the PWMCHB and PWMCHC registers in a manner
identical to that described for PWMCHA.

The PWM controller does not produce any PWM outputs until
all of the PWMTM, PWMCHA, PWMCHB, and PWMCHC
registers have been written to at least once. After these registers
have been written, the counters in the three-phase timing unit
are enabled. Writing to these registers also starts the main PWM
timer. If during initialization, the PWMTM register is written
before the PWMCHA, PWMCHB, and PWMCHC registers,
the first PWMSYNC pulse (and interrupt if enabled) will be gener-
ated (1.5

× t

× PWMTM) seconds after the initial write to the

PWMTM register in single update mode. In double update mode,
the first PWMSYNC pulse will be generated (t

× PWMTM)

seconds after the initial write to the PWMTM register in single
update mode.

Effective PWM Resolution

In single update mode, the same values of PWMCHA, PWMCHB
and PWMCHC are used to define the on-times in both half
cycles of the PWM period. As a result, the effective resolution of
the PWM generation process is 2 t

(or 100 ns for a 20 MHz

CLKOUT) since incrementing one of the duty cycle registers by

ADMCF328

REV. 0

one changes the resultant on-time of the associated PWM signals
by t

in each half period (or 2 t

for the full period).

In double update mode, improved resolution is possible since
different values of the duty cycle registers are used to define the
on-times in both the first and second halves of the PWM period.
As a result, it is possible to adjust the on-time over the whole
period in increments of t

. This corresponds to an effective

PWM resolution of t

in double update mode (or 50 ns for a

20 MHz CLKOUT).

The achievable PWM switching frequency at a given PWM
resolution is tabulated in Table IV.

Table IV. Achievable PWM Resolution in Single and Double
Update Modes

Resolution

Single Update Mode

Double Update Mode

(Bit)

PWM Frequency (kHz)

39.1

78.1

19.5

39.1

9.8

19.5

4.9

9.8

2.4

4.9

Minimum Pulsewidth: PWMPD Register

In many power converter switching applications, it is desirable
to eliminate PWM switching pulses shorter than a certain width.
It takes a finite time to both turn on and turn off modern
power semiconductor devices. Therefore, if the width of any of the
PWM pulses is shorter than some minimum value, it may
be desirable to completely eliminate the PWM switching for
that particular cycle.

The allowable minimum on-time for any of the six PWM outputs
for half a PWM period that can be produced by the PWM control-
ler may be programmed using the PWMPD register. The minimum
on-time is programmed in increments of t

so that the minimum

on-time produced for any half PWM period, T

MIN

, is related to

the value in the PWMPD register by:

MIN

= PWMPD

× t

A PWMPD value of 0x002 defines a permissible minimum
on-time of 100 ns for a 20 MHz CLKOUT.

In each half cycle of the PWM, the timing unit checks the on-
time of each of the six PWM signals. If any of the times is found
to be less than the value specified by the PWMPD register, the
corresponding PWM signal is turned OFF for the entire half
period, and its complementary signal is turned completely ON.

Consider the example where PWMTM = 200, PWMCHA = 5,
PWMDT = 3, and PWMPD = 10 with a CLKOUT of 20 MHz,
while operating in single update mode. For this case, the PWM
switching frequency is 50 kHz and the dead time is 300 ns. The
minimum permissible on-time of any PWM signal over one-half
of any period is 500 ns. Clearly, for this example, the dead-time
adjusted on-time of the AH signal for one-half a PWM period is
(53)

× 50 ns = 100 ns. Because this is less than the minimum

permissible value, output AH of the timing unit will remain
OFF (0% duty cycle). Additionally, the AL signal will be turned
ON for the entire half period (100% duty cycle).

Output Control Unit: PWMSEG Register

The operation of the output control unit is managed by the 9-bit
read/write PWMSEG register. This register sets two distinct
features of the output control unit that are directly useful in the
control of ECM or BDCM.

The PWMSEG register contains three crossover bits, one for each
pair of PWM outputs. Setting Bit 8 of the PWMSEG register
enables the crossover mode for the AH/AL pair of PWM signals;
setting Bit 7 enables crossover on the BH/BL pair of PWM
signals; and setting Bit 6 enables crossover on the CH/CL pair
of PWM signals. If crossover mode is enabled for any pair of
PWM signals, the high-side PWM signal from the timing unit
(for example AH) is diverted to the associated low-side output
of the output control unit so that the signal will ultimately
appear at the AL pin. Of course, the corresponding low-side
output of the timing unit is also diverted to the complementary
high-side output of the output control unit so that the signal
appears at Pin AH. Following a reset, the three crossover bits
are cleared so that the crossover mode is disabled on all three
pairs of PWM signals.

The PWMSEG register also contains six bits (Bits 0 to 5) that
can be used to individually enable or disable each of the six
PWM outputs. If the associated bit of the PWMSEG register is
set, the corresponding PWM output is disabled regardless of the
value of the corresponding duty cycle register. This PWM output
signal will remain in the OFF state as long as the corresponding
enable/disable bit of the PWMSEG register is set. The PWM
output enable function gates the crossover function. After a reset,
all six enable bits of the PWMSEG register are cleared, thereby
enabling all PWM outputs by default.

In a manner identical to the duty cycle registers, the PWMSEG
is latched on the rising edge of the PWMSYNC signal so that
changes to this register only become effective at the start of each
PWM cycle in single update mode. In double update mode, the
PWMSEG register can also be updated at the midpoint of the
PWM cycle.

In the control of an ECM, only two inverter legs are switched
at any time, and often the high-side device in one leg must be
switched ON at the same time as the low-side driver in a second
leg. Therefore, by programming identical duty cycles for two
PWM channels (for example, let PWMCHA = PWMCHB) and
setting Bit 7 of the PWMSEG register to crossover the BH/BL
pair of PWM signals, it is possible to turn ON the high-side
switch of Phase A and the low-side switch of Phase B at the
same time. In the control of an ECM, one inverter leg (Phase C
in this example) is disabled for a number of PWM cycles. This
disable may be implemented by disabling both the CH and CL
PWM outputs by setting Bits 0 and 1 of the PWMSEG register.
This is illustrated in Figure 9, where it can be seen that both
the AH and BL signals are identical, because PWMCHA =
PWMCHB, and the crossover bit for Phase B is set. In addition,
the other four signals (AL, BH, CH, and CL) have been disabled
by setting the appropriate enable/disable bits of the PWMSEG
register. For the situation illustrated in Figure 9, the appropriate
value for the PWMSEG register is 0x00A7. In ECM operation,
because each inverter leg is disabled for certain periods of time,
the PWMSEG register is changed based upon the position of
the rotor shaft (motor commutation).

ADMCF328

REV. 0

PWMTM

PWMCHA

= PWMCHB

PWMCHA

= PWMCHB

2 PWMDT

Figure 9. An example of PWM signals suitable for ECM
control. PWMCHA = PWMCHB, BH/BL are a crossover pair.
AL, BH, CH, and CL outputs are disabled. Operation is in
single update mode.

Gate Drive Unit: PWMGATE Register

The gate drive unit of the PWM controller adds features that
simplify the design of isolated gate drive circuits for PWM
inverters. If a transformer-coupled power device gate drive ampli-
fier is used, the active PWM signal must be chopped at a high
frequency. The PWMGATE register allows the programming of
this high frequency chopping mode. The chopped active PWM
signals may be required for the high-side drivers only, for the
low-side drivers only, or for both the high-side and low-side
switches. Therefore, independent control of this mode for both
high- and low-side switches is included with two separate control
bits in the PWMGATE register.

Typical PWM output signals with high-frequency chopping
enabled on both high-side and low-side signals are shown in
Figure 10. Chopping of the high-side PWM outputs (AH, BH,
and CH) is enabled by setting Bit 8 of the PWMGATE register.
Chopping of the low-side PWM outputs (AL, BL, and CL) is
enabled by setting Bit 9 of the PWMGATE register. The high
chopping frequency is controlled by the 8-bit word (GDCLK)
written to Bits 0 to 7 of the PWMGATE register. The period
and the frequency of this high frequency carrier are:

GDCLK

CHOP

CLKOUT

(

)

[

]

(

)

[

]

The GDCLK value may range from 0 to 255, corresponding
to a programmable chopping frequency rate from 19.5 kHz to
5 MHz for a 20 MHz CLKOUT rate. The gate drive features
must be programmed before operation of the PWM controller
and typically are not changed during normal operation of the
PWM controller. Following a reset, by default, all bits of the
PWMGATE register are cleared so that high frequency chopping
is disabled.

PWMTM

(GDCLK+1)

]

PWMDT

PWMCHA

Figure 10. Typical PWM signals with high frequency gate
chopping enabled on both high-side and low-side switches
(GDCLK is the integer equivalent of the value in Bits 0 to 7
of the PWMGATE register.)

PWM Shutdown

In the event of external fault conditions, it is essential that the
PWM system be instantaneously shut down. Two methods of
sensing a fault condition are provided by the ADMCF328. For
the first method, a low level on the

PWMTRIP pin initiates

an instantaneous, asynchronous (independent of DSP clock)
shutdown of the PWM controller. This places all six PWM
outputs in the OFF state, disables the PWMSYNC pulse and
associated interrupt signal, and generates a

PWMTRIP interrupt

signal. The

PWMTRIP pin has an internal pull-down resistor so

that even if the pin becomes disconnected, the PWM outputs will
be disabled. The state of the

PWMTRIP pin can be read from

bit 0 of the SYSSTAT register.

The second method for detecting a fault condition is through the
I

SENSE

pin in the analog block of the ADMCF328. The I

SENSE

pin monitors the feedback signals from a dc bus current sensing
resistor that represents the total current in the motor. When the
voltage of I

SENSE

goes below I

SENSE

trip threshold,

PWMTRIP

will be internally pulled low. The negative edge of the internal
PWMTRIP will generate a shutdown in the same manner as a
negative edge on pin

PWMTRIP.

It is possible through software to initiate a PWM shutdown by
writing to the 1-bit read/write PWMSWT register (0x2061).
Writing to this bit generates a PWM shutdown in a manner
identical to the

PWMTRIP or I

SENSE

pins. Following a PWM

shutdown, it is possible to determine if the shutdown was gener-
ated from hardware or software by reading the same PWMSWT
register. Reading this register also clears it.

Restarting the PWM after a fault condition is detected requires
clearing the fault and reinitializing the PWM. Clearing the fault
requires that

PWMTRIP returns to a HI state and I

SENSE

returns

to a voltage greater than the I

SENSE

trip threshold. After the

fault has been cleared, the PWM can be restarted by writing to
registers PWMTM, PWMCHA, PWMCHB, and PWMCHC. After
the fault is cleared and the PWM registers are initialized, internal
timing of the three-phase timing unit will resume, and the
new duty cycle values will be latched on the next rising edge
of PWMSYNC.

ADMCF328

REV. 0

PWM Registers

The configuration of the PWM registers is described at the end
of the data sheet. The parameters of the PWM block are tabu-
lated in Table V.

ADC OVERVIEW

The ADC of the ADMCF328 is based upon the single slope
conversion technique. This approach offers an inherently
monotonic conversion process and to within the noise and stability
of its components, and there will be no missing codes.

Table VI. ADC Auxiliary Channel Selection

MODECTRL (1)

MODECTRL (0)

Select

ADCMUX1

ADCMUX0

VAUX0

VAUX1

VAUX2

Calibration (V

REF

)

The single slope technique has been adapted on the ADMCF328
for four channels that are simultaneously converted. Refer to
Figure 11 for the functional schematic of the ADC. Two of the
main inputs (V1 and V2) are directly connected as high imped-
ance voltage inputs. The third main input channel (I

SENSE

) has

a special design to monitor the voltage on a current-sensing
resistor whose voltage is always below (more negative than)
the power supply rail. The fourth channel has been configured
with a serially-connected 4-to-1 multiplexer. Table VI shows the
multiplexer input selection codes. One of these auxiliary mul-
tiplexed channels is used to calibrate the ramp against the
internal voltage reference (V

REF

VAUX0

V2L

VAUXL

PWMSYNC (CONVST)

ADC

REGISTERS

V1L

V3L

SENSE

(CAP RESET)

CLK MODECTRL<7>

12-BIT

ADC

TIMER

BLOCK

PWMTRIP

VREF

COMP

ADC REGISTERS

ADC1
ADC2
ADC3
ADCAUX

MODECTRL<0..1>

EXTERNAL
CHARGING
CAP

ICONST

ICONST_TRIM<2:0>

VAUX1

VAUX2

COMP

0.8

GND

41

MUX

Figure 11. ADC Overview

Comparing each ADC input to a reference ramp voltage and
timing the comparison of the two signals performs the conversion
process. The actual conversion point is the time point inter-
section of the input voltage and the ramp voltage (V

) as shown in

Figure 12. This time is converted to counts by the 12-bit ADC
Timer Block and is stored in the ADC registers. The ramp voltage
used to perform the conversion is generated by driving a fixed
current into an off-chip capacitor, where the capacitor voltage is

= (I/C)

× t

Table V. Fundamental Characteristics of PWM Generation Unit of ADMCF328

16-BIT PWM TIMER

Parameter

Min

Typ

Max

Unit

Counter Resolution

Bits

Edge Resolution (Single Update Mode)

100

Edge Resolution (Double Update Mode)

Programmable Dead Time Range

100

µs

Programmable Dead Time Increments

100

Programmable Pulse Deletion Range

100

µs

Programmable Pulse Deletion Increments

100

PWM Frequency Range

150

PWMSYNC Pulsewidth (T

CRST

)

0.05

12.5

µs

Gate Drive Chop Frequency Range

0.02

MHz

ADMCF328

REV. 0

Following reset, V

= 0 at t = 0. This reset and the start of

the conversion process are initiated by the PWMSYNC pulse,
as shown in Figure 12. The width of the PWMSYNC pulse is
controlled by the PWMSYNCWT register and should be pro-
grammed according to Figure 13 to ensure complete resetting.
In order to compensate for IC process manufacturing tolerances
(and to adjust for capacitor tolerances), the current source of the
ADMCF328 is software programmable. The software setting of the
magnitude of the ICONST current generator is accomplished by
selecting one of eight steps over approximately 20% current range.

PWMSYNC

VIL

COMPARATOR

OUTPUT

CRST

PWM

CRST

VIL

CMAX

Figure 12. Analog Input Block Operation

The ADC system consists of four comparators and a single
timer, which may be clocked at either the DSP rate or half the
DSP rate, depending on the setting of the ADCCNT bit (Bit 7)
of the MODECTRL register. When this bit is cleared, the timers
count at a slower rate of CLKIN. When this bit is set, they count
at CLKOUT or twice the rate of CLKIN. ADC1, ADC2, ADC3,
and ADCAUX are the registers that capture the conversion
times, which are effectively the timer values, when the associated
comparator trips.

CHARGING CAPACITOR nF

200

DECIMAL COUNTS

100

150

Figure 13. PWMSYNCWT Program Value

ADC Resolution

The ADC is intrinsically linked to the PWM block through the
PWMSYNC pulse controlling the ADC conversion process.
Because of this link, the effective resolution of the ADC is a
function of both the PWM switching frequency and the rate
at which the ADC counter timer is clocked. For a CLKOUT
period of t

and a PWM period of T

PWM

, the maximum count of

the ADC is given by:

Max Count = min (4095, (T

PWM

CRST

)/2 t

)

for MODECTRL Bit 7 = 0

Max Count = min (4095, (T

PWM

CRST

)/t

)

for MODECTRL Bit 7 = 1

Where T

PWM

is equal to the PWM period if operating in single

update mode, or it is equal to half that period if operating in
double update mode. For an assumed CLKOUT frequency of
20 MHz and PWMSYNC pulsewidth of 2.0

µs, the effective

resolution of the ADC block is tabulated for various PWM
switching frequencies in Table VII.

Table VII. ADC Resolution Examples

PWM

MODECTRL[7] = 0

MODECTRL[7] = 1

Frequency

Max

Effective

Max

Effective

(kHz)

Count

Resolution

Count

Resolution

2.4

4095

2480

>11

4095

1230

>10

2460

>11

535

1070

>10

380

760

Charging Capacitor Selection

The charging capacitor value is selected based on the sample
(PWM) frequency desired. A too-small capacitor value will reduce
the available resolution of the ADC by having the ramp voltage
rise rapidly and convert too quickly, not utilizing all possible
counts available in the PWM cycle. Too large a capacitor may not
convert in the available PWM cycle returning 0x000. To select a
charging capacitor, use Figure 14, select the sampling frequency
desired, determine if the current source is to be tuned to a nominal
100

µA or left in the default (0x0 code) trim state, then determine

the proper charge capacitor off the appropriate curve.

FREQUENCY kHz

100

NOM

TUNED ICONST

DEFAULT ICONST

Figure 14. Timing Capacitor Selection

ADMCF328

REV. 0

Programmable Current Source

The ADMCF328 has an internal current source that is used to
charge an external capacitor, generating the voltage ramp used
for conversion. The magnitude of the output of the current
source circuit is subject to manufacturing variations and can
vary from one device to the next. Therefore, the ADMCF328
incudes a programmable current source whose output can always
be tuned to within 5% of the target 100

µA. A 3-bit register,

ICONST_TRIM, allows the user to make this adjustment. The
output current is proportional to the value written to the regis-
ter: 0x0 produces the minimum output, and 0x7 produces the
maximum output. The default value of ICONST_TRIM after
reset is 0x0.

ADC Reference Ramp Calibration

The peak of the ADC ramp voltage should be as close as possible
to 3.5 V to achieve the optimum ADC resolution and signal range.
When the current source is in the Default State, the peak of the
ADC ramp slope will be lower than this "3.5 V" target ramp.
When the current source value is increased, the ADC ramp
slope will become closer to the target value. The "tuned" ramp
slope is the one closest to the target ramp.

A simple calibration procedure using the internal 2.5 V reference
voltage allows the selection of the ICONST_TRIM register
value to reach this:

1. A high quality linear ADC capacitor is selected using Figure

14 for a tuned ICONST.

2. Program PWMSYNCWT to proper count as in Figure 13.

3. The ADC Max Count is calculated, as described in a previ-

ous section.

4. The target reference conversion is calculated as TARGET =

(Max Count)

× (2.5 V/3.5 V).

5. Reset or software sets the ICONST_TRIM register to zero.

6. Select calibration channel in software on ADC multiplexer.

7. The calibration channel value is compared with the target

reference conversion.

8. If this value is greater than the TARGET, the ICONST_TRIM

value is incremented by one, and Step 7 is repeated.

9. If the calibration channel value is less than the TARGET,

the calibration is completed.

REF

3.5V

0.3V

MINIMUM

RAMP

TARGET

RAMP

Figure 15. Current Ramp

Current Sense Amplifier

The ADMCF328 analog circuit block also integrates an inverting
amplifier, a sample-and-hold amplifier, and an over-current-
trip comparator. The current sense amplifier input signal range
is matched to the requirements of medium to low power motor
control applications. There is an output offset that matches the
amplifier output signal range to the input signal range of the A/D
converter. This amplifier is followed by a sample-and-hold
amplifier that samples the current sense signal on the falling edge
of the PWMSYNC pulse. This sampling amplifier system can be
used to capture the winding current signal in a brushless dc motor.

WINDING

CURRENT SENSE SIGNAL

CIRCUIT COMMON

WINDING

BUS

Figure 16. Typical Power Inverter Switching Topology
for DC Brushless Motor Control

Current Sense Amplifier Application

The ADMCF328 current sense amplifier system has been
provided to simplify the measurement of the motor winding
currents in brushless dc motor control systems. The assumed
power circuit configuration, illustrated in Figure 16, is one in
which a current sense resistor is placed between the circuit com-
mon and the return path to the negative power bus. The normal
PWM modulation scheme keeps one upper device fully conduct-
ing while the duty cycle of one of the lower power switches is
varied. In this case, there is a negative going voltage across the
resistive shunt when the complementary upper diode conducts.
The shunt signal, I

BUS

, shown in Figure 17, is sampled at the

midpoint of the lower device-on period using the PWMSYNC
pulse. The captured value represents the current in the motor
winding I

WINDING

ADC Registers

The configuration of all registers of the ADC System is shown at
the end of the data sheet.

AUXILIARY PWM TIMERS
Overview

The ADMCF328 provides two variable frequency, variable duty
cycle, 8-bit, auxiliary PWM outputs that are available at the AUX1
and AUX0 pins when enabled. These auxiliary PWM outputs
can be used to provide switching signals to other circuits in a
typical motor control system such as power factor corrected
front-end converters or other switching power converters. Alter-
natively, by addition of a suitable filter network, the auxiliary
PWM output signals can be used as simple single-bit digital-to-
analog converters.

ADMCF328

REV. 0

LOWER TRANSISTOR

CONDUCTION

UPPER

DIODE

CONDUCTION

LOWER TRANSISTOR

CONDUCTION

PWMSYNC

BUS

WINDING

Figure 17. Bus Current Signals

The auxiliary PWM system of the ADMCF328 can operate in
two different modes: independent mode or offset mode. The
operating mode of the auxiliary PWM system is controlled
by Bit 8 of the MODECTRL register. Setting Bit 8 of the
MODECTRL register places the auxiliary PWM system in the
independent mode. In this mode, the two auxiliary PWM genera-
tors are completely independent and separate switching
frequencies and duty cycles may be programmed for each aux-
iliary PWM output. In this mode, the 8-bit AUXTM0 register
sets the switching frequency of the signal at the AUX0 output
pin. Similarly, the 8-bit AUXTM1 register sets the switching
frequency of the signal at the AUX1 pin. The fundamental time
increment for the auxiliary PWM outputs is twice the DSP
instruction rate (or 2 t

) and the corresponding switching

periods are given by:

AUX0

= 2

× (AUXTM0 + 1) × t

AUX1

= 2

× (AUXTM1 + 1) × t

Since the values in both AUXTM0 and AUXTM1 can range
from 0 to 0xFF, the achievable switching frequency of the
auxiliary PWM signals may range from 39.1 kHz to 10 MHz for
a CLKOUT frequency of 20 MHz.

The on-time of the two auxiliary PWM signals is programmed
by the two 8-bit AUXCH0 and AUXCH1 registers, according to:

AUX0

= 2

× (AUXCH0) × t

AUX1

= 2

× (AUXCH1) × t

so that output duty cycles from 0% to 100% are possible. Duty
cycles of 100% are produced if the on-time value exceeds the
period value. Typical auxiliary PWM waveforms in independent
mode are shown in Figure 18(a).

When Bit 8 of the MODECTRL register is cleared, the auxiliary
PWM channels are placed in offset mode. In offset mode, the
switching frequency of the two signals on the AUX0 and AUX1
pins are identical and controlled by AUXTM0 in a manner
similar to that previously described for independent mode. In
addition, the on times of both the AUX0 and AUX1 signals are
controlled by the AUXCH0 and AUXCH1 registers as before.
However, in this mode the AUXTM1 register defines the offset
time from the rising edge of the signal on the AUX0 pin to that
on the AUX1 pin according to:

OFFSET

= 2

× (AUXTM1 + 1) × t

For correct operation in this mode, the value written to the
AUXTM1 register must be less than the value written to the
AUXTM0 register. Typical auxiliary PWM waveforms in offset
mode are shown in Figure 18(b). Again, duty cycles from 0% to
100% are possible in this mode.

In both operating modes, the resolution of the auxiliary PWM
system is eight bits only at the minimum switching frequency
(AUXTM0 = AUXTM1 = 255 in independent mode, AUXTM0
= 255 in offset mode). Obviously, as the switching frequency is
increased, the resolution is reduced.

Values can be written to the auxiliary PWM registers at any
time. However, new duty cycle values written to the AUXCH0
and AUXCH1 registers only become effective at the start of the
next cycle. Writing to the AUXTM0 or AUXTM1 registers
causes the internal timers to be reset to 0 and new PWM cycles
to begin.

By default following a reset, Bit 8 of the MODECTRL register
is cleared, thus enabling offset mode. In addition, the registers
AUXTM0 and AUXTM1 default to 0xFF, corresponding to
the minimum switching frequency and zero offset. The on-time
registers AUXCH0 and AUXCH1 default to 0x00.

Auxiliary PWM Interface, Registers and Pins

The registers of the auxiliary PWM system are summarized at
the end of the data sheet.

AUX0

AUX1

2 (AUXTM0 + 1)

2 (AUXTM1 + 1)

2 AUXCH1

2 AUXCH0

(a) Independent Mode

AUX0

AUX1

2 (AUXTM1 + 1)

2 (AUXTM0 + 1)

2 AUXCH0

2 (AUXTM0 + 1)

2 AUXCH1

(b) Offset Mode

Figure 18. Typical Auxiliary PWM Signals. (All Times in
Increments of t

)

PWM DAC Equation

The auxiliary PWM output can be filtered in order to produce
a low frequency analog signal between 0 V to V

. For example,

a 2-pole filter with a 1.2 kHz cutoff frequency will sufficiently
attenuate the PWM carrier. Figure 19 shows how the filter would
be applied.

ADMCF328

REV. 0

R1 = R2 = 13k
C1 = C2 = 10nF

AUXPWM

Figure 19. Auxiliary PWM Output Filter

WATCHDOG TIMER

The ADMCF328 incorporates a watchdog timer that can per-
form a full reset of the DSP and motor control peripherals in the
event of software error. The watchdog timer is enabled by writing a
timeout value to the 16-bit WDTIMER register. The timeout
value represents the number of CLKIN cycles required for the
watchdog timer to count down to zero. When the watchdog timer
reaches zero, a full DSP core and motor control peripheral reset
is performed. In addition, Bit 1 of the SYSSTAT register is set
so that after a watchdog reset, the ADMCF328 can determine
that the reset was due to the timeout of the watchdog timer
and not an external reset. Following a watchdog reset, Bit 1 of
the SYSSTAT register may be cleared by writing zero to the
WDTIMER register. This clears the status bit but does not
enable the watchdog timer.

On reset, the watchdog timer is disabled and is only enabled
when the first timeout value is written to the WDTIMER register.
To prevent the watchdog timer from timing out, the user must
write to the WDTIMER register at regular intervals (shorter than
the programmed WDTIMER period value). On all but the first
write to WDTIMER, the particular value written to the register
is unimportant since writing to WDTIMER simply reloads the
first value written to this register.

PROGRAMMABLE DIGITAL INPUT/OUTPUT

The ADMCF328 has nine programmable digital input/output
(PIO) pins that are all multiplexed with other functions. The nine
PIO lines PIO0PIO8 are multiplexed with the serial port (Pins
PIO0/TFS1 to PIO5/RFS1), the CLKOUT (pin PIO6/CLKOUT)
and the auxiliary PWM outputs (Pins PIO7/AUX1 and PIO8/
AUX0). When configured as a PIO, each of these nine pins can
act as an input, output, or an interrupt source.

The operating mode of pins PIO0/TFS1 to PIO7/AUX1 is con-
trolled by the PIOSELECT register. This 8-bit register has a bit
for each input so that the mode of each pin may be selected indi-
vidually. Bit 0 of PIOSELECT controls the operation of the
PIO0/TFS1 pin. Bit 1 controls the PIO1/DT1 pin, etc. Setting
the appropriate bit in the PIOSELECT register causes the cor-
responding pin to be configured for PIO functionality. Clearing
the bit selects the alternate (SPORT, CLKOUT, or AUXPWM)
mode of the corresponding pin. Following power-on reset, all
bits of PIOSELECT are set such that PIO functionality is
selected. The operating mode of the PIO8/AUX0 pin is selected
by Bit 1 of the PIODATA1 register. In a manner identical to the

PIOSELECT register, setting this bit enables PIO functionality
(PIO8) while clearing the bit enables auxiliary PWM functional-
ity (AUX0).

Once PIO functionality has been selected for any or all of these
nine pins, the direction may be set by the 8-bit PIODIR0 regis-
ter (for PIO0 to PIO7) and the 1-bit PIODIR1 register (for PIO8).
Clearing any bit configures the corresponding PIO line as an
input while setting the bit configures it as an output. By default,
following a reset, all bits of PIODIR0 and PIODIR1 are cleared
configuring the PIO lines as inputs.

The data of the PIO0 to PIO8 lines is controlled by the
PIODATA0 register (for PIO0 to PIO7) and Bit 0 of the
PIODATA1 register (for PIO8). These registers can be used to
read data from those PIO lines configured as inputs and write data
to those configured as outputs. Any of the nine pins that have been
configured for PIO functionality can be made to act as an interrupt
source by setting the appropriate bit of the PIOINTEN0 register
(for PIO0 to PIO7) or the PIOINTEN1 register (for PIO8). In
order to act as an interrupt source the pin must also be configured
as an input. An interrupt is generated upon a change of state
(low-to-high transition or high-to-low transition) on any input
that has been configured as an interrupt source. Following a
change of state event on any such input, the corresponding
bit is set in the PIOFLAG0 register (for PIO0 to PIO7) and
PIOFLAG1 (for PIO8) and a common PIO interrupt is gener-
ated. Reading the PIOFLAG0 and PIOFLAG1 registers permits
determining the interrupt source. Reading the PIOFLAG0 and
PIOFLAG1 registers automatically clears all bits of the registers.
Following power-on or reset, all bits of PIOINTEN0 and
PIOINTEN1 are cleared so that no interrupts are enabled.

Each PIO line has an internal pull-down resistor so that follow-
ing power-on or reset all nine lines are configured as input PIOs
and will be read as logic lows if left unconnected.

Multiplexing of PIO Lines

The PIO0PIO5 lines are multiplexed on the ADMCF328 with
the functional lines of the serial port, SPORT1. Although the
PIOSELECT register permits individual selection of the func-
tionality of each pin, certain restrictions apply when using
SPORT1 for serial communications.

In general, when transmitting and receiving data on the DTI and
DRIB pins, respectively, the PIO0/TFS1 and PIO5/RFS1 pins
must also be selected for SPORT (TFS1 and RFS1) functional-
ity even if unframed communication is implemented. Therefore,
when using SPORT1 for any type of serial communication, the
minimal setting for PIOSELECT is 0xD8 (i.e., select DTI, DRIB,
RFS1 and TFS1, select PIO7, PIO6, PIO4, PIO3 as digital I/O).

If the serial port communications use an internally generated
SCLK1, the PIO3/SCLK1 pin may be used as a general-purpose
PIO line. When external SCLK mode is selected, the PIO/SCLK1
pin must be enabled as SCLK1 (PIOSELECT [3] = 0).

Table VIII. Fundamental Characteristics of Auxiliary PWM Timer of ADMCF328

AUXILIARY PWM TIMERS

Parameter

Test Conditions

Min

Typ

Max

Unit

Resolution

Bits

PWM Frequency

10 MHz CLKIN

0.039

MHz

ADMCF328

REV. 0

When the DRIB data receive line of SPORT1 is selected as
the data receive line (MODECTRL [4] = 1), the PIO4/DRIA
line may be used as a general-purpose PIO pin. When the DRIA
data receive line of SPORT1 is selected as the data receive line
(MODECTRL [4] = 0), the PIO2/DRIB line may be used as
a general-purpose PIO pin.

The functionality of the PIO6/CLKOUT, PIO7/AUX1, and
PIO8/AUX0 pins may be selected on a pin-by-pin basis as desired.

PIO Registers

The configuration of all registers of the PIO system is shown at
the end of the data sheet.

INTERRUPT CONTROL

The ADMCF328 can respond to 16 different interrupt sources,
some of which are generated by internal DSP core interrupts
and others from the motor control peripherals. The DSP core
interrupts include the following:

· A Peripheral (or IRQ2) Interrupt.
· A SPORT1 Receive (or

IRQ0) and a SPORT1 Transmit (or

IRQ1) Interrupt.

· Two Software Interrupts.
· An Interval Timer Time-Out Interrupt.

The interrupts generated by the motor control peripherals include:

· A PWMSYNC Interrupt.
· Nine Programmable Input/Output (PIO) Interrupts.
· A PWM Trip Interrupt.

The core interrupts are internally prioritized and individually
maskable. All peripheral interrupts are multiplexed into the DSP
core through the peripheral (

IRQ2) interrupt.

The PWMSYNC interrupt is triggered by a low-to-high tran-
sition on the PWMSYNC pulse. The

PWMTRIP interrupt is

triggered on a high-to-low transition on the

PWMTRIP pin, an

overcurrent on the I

SENSE

pin, or by writing to the PWMSWT

The ADMCF328 interrupt control system is configured and
controlled by the IFC, IMASK, and ICNTL registers of the
DSP core and by the IRQFLAG register for the PWMSYNC
and

PWMTRIP interrupts. PIO interrupts are enabled and

disabled by the PIOINTEN0 and PIOINTEN1 registers.

Table IX. Interrupt Vector Addresses

Interrupt Source

Interrupt Vector Address

PWMTRIP

0x002C (Highest Priority)

Peripheral Interrupt (

IRQ2)

0x0004

PWMSYNC

0x000C

PIO

0x0008

Software Interrupt 1

0x0018

Software Interrupt 0

0x001C

SPORT1 Transmit Interrupt (or

IRQ1) 0x0020

SPORT1 Receive Interrupt (or

IRQ0) 0x0024

Timer

0x0028 (Lowest Priority)

Interrupt Masking

Interrupt masking (or disabling) is controlled by the IMASK
register of the DSP core. This register contains individual bits
that must be set to enable the various interrupt sources. If any
peripheral interrupt (PWMSYNC,

PWMTRIP, or PIO) is to

be enabled, the

IRQ2 interrupt enable bit (Bit 9) of the IMASK

Interrupt Configuration

The IFC and ICNTL registers of the DSP core control and config-
ure the interrupt controller of the DSP core. The IFC register is a
16-bit register that may be used to force and/or clear any of
the eight DSP interrupts. Bits 0 to 7 of the IFC register may
be used to clear the DSP interrupts while Bits 8 to 15 can be
used to force a corresponding interrupt. Writing to Bits 11 and 12
in IFC is the only way to create the two software interrupts.

The ICNTL register is used to configure the sensitivity (edge
or level) of the

IRQ0, IRQ1, and IRQ2 interrupts and to enable/

disable interrupt nesting. Setting Bit 0 of ICNTL configures the
IRQ0 as edge-sensitive, while clearing the bit configures it for
level-sensitive. Bit 1 is used to configure the

IRQ1 interrupt.

Bit 2 is used to configure the

IRQ2 interrupt. It is recommended

that the

IRQ2 interrupt always be configured as level-sensitive

to ensure that no peripheral interrupts are lost. Setting Bit 4 of
the ICNTL register enables interrupt nesting. The configuration
of both the IFC and ICNTL registers is shown at the end of the
data sheet.

Interrupt Operation

Following a reset, the ROM code on the ADMCF328 must
copy a default interrupt vector table into program memory
RAM from address 0x0000 to 0x002F. Since each interrupt
source has a dedicated four-word space in this vector table, it is
possible to code short interrupt service routines (ISR) in place.
Alternatively, it may be necessary to insert a JUMP instruction
to the appropriate start address of the interrupt service routine if
more memory is required for the ISR.

When an interrupt occurs, the program sequencer ensures that
there is no latency (beyond synchronization delay) when pro-
cessing unmasked interrupts. In the case of the timer, SPORT1,
and software interrupts, the interrupt controller automatically
jumps to the appropriate location in the interrupt vector table. At
this point, a JUMP instruction to the appropriate ISR is required.

Motor control peripheral interrupts are slightly different. When a
peripheral interrupt is detected, a bit is set in the IRQFLAG regis-
ter for PWMSYNC and

PWMTRIP or in the PIOFLAG0, or

PIOFLAG1 registers for a PIO interrupt, and the

IRQ2 line

is pulled low until all pending interrupts are acknowledged.

The DSP software must determine the source of the interrupts
by reading IRQFLAG register. If more than one interrupt
occurs simultaneously, the higher priority interrupt service routine
is executed. Reading the IRQFLAG register clears the

PWMTRIP

and PWMSYNC bits and acknowledges the interrupt, thus allow-
ing further interrupts when the ISR exits.

ADMCF328

REV. 0

A user's PIO interrupt service routine must read the PIOFLAG0
and PIOFLAG1 registers to determine which PIO port is
the source of the interrupt. Reading registers PIOFLAG0 and
PIOFLAG1 clears all bits in the registers and acknowledges
the interrupt, thus allowing further interrupts after the ISR exits.

The configuration of all these registers is shown at the end of
the data sheet.

SYSTEM CONTROLLER

The system controller block of the ADMCF328 performs the
following functions:

Manages the interface and data transfer between the DSP
core and the motor control peripherals.

Handles interrupts generated by the motor control peripherals
and generates a DSP core interrupt signal

IRQ2.

Controls the ADC multiplexer select lines.

Enables

PWMTRIP and PWMSYNC interrupts.

Controls the multiplexing of the SPORT1 pins to select
either DR1A or DR1B data receive pins. It also allows con-
figuration of SPORT1 as a UART interface.

Controls the PWM single/double update mode.

Controls the ADC conversion time modes.

Controls the auxiliary PWM operation mode.

Contains a status register (SYSSTAT) that indicates the
state of the

PWMTRIP pin, the watchdog timer and the

PWM timer.

10. Performs a reset of the motor control peripherals and control

registers following a hardware, software or watchdog initi-
ated reset.

SPORT1 Control

Both data receive pins are multiplexed internally into the single
data receive input of SPORT1 as shown in Figure 20. Two con-
trol bits in the MODECTRL register control the state of the
SPORT1 pins by manipulating internal multiplexers in the
ADMCF328.

DSP
CORE
SPORT1

PIO4/DR1A

PIO2/DR1B

PIO0/TFS1

PIO5/RFS1

PIO3/SCLK1

MODECTRL (5 . . . 4)

UARTEN

DR1SEL

DT1

DR1

TFS1

RFS1

SCLK1

FL1

ADMCF328

PIO1/DT1

Figure 20. Internal Multiplexing of SPORT1 Pins

Bit 4 of the MODECTRL register (DR1SEL) selects between the
two data receive pins. Setting Bit 4 of MODECTRL connects pin
DR1B to the internal data receive port DR1 of SPORT1. Clearing
Bit 4 connects DR1A to DR1.

Setting Bit 5 of the MODECTRL register (SPORT1 Mode) con-
figures the serial port for UART mode. In this mode, the DR1 and
RFS1 pins of the internal serial port are connected together. Addi-
tionally, setting the SPORT1 Mode bit connects the FL1 flag of
the DSP to the external PIO5/RFS1 pin.

Flag Pins

The ADMCF328 provides flag pins. The alternate configuration
of SPORT1 includes a Flag In (FI) and Flag Out (FO) pin.
This alternate configuration of SPORT1 is selected by Bit 10 of
the DSP system control register, SYSCNTL at data memory
address, 0x3FFF. In the alternate configuration, the DR1 pin
(either DR1A or DR1B depending upon the state of the DR1SEL
bit) becomes the FI pin and the DT1 pin becomes the FO pin.
Additionally, RFS1 is configured as the

IRQ0 interrupt input

and TFS1 is configured as the

IRQ1 interrupt. The serial port

clock, SCLK1, is still available in the alternate configuration.

Development Tools

Users are recommended to obtain the ADMCF328-EVALKIT
from Analog Devices. The tool kit contains everything required
to quickly and easily evaluate and develop applications using the
ADMCF328 and ADMC328 DSP Motor Controllers. Please
contact your ADI sales representative for ordering information.

ADMCF328

REV. 0

Table X. Peripheral Register Map

Address
(HEX)

Name

Bits Used

Function

0x2000

ADC1

[15 . . . 4]

ADC Results for V1

0x2001

ADC2

[15 . . . 4]

ADC Results for V2

0x2002

ADC3

[15 . . . 4]

ADC Results for I

SENSE

0x2003

ADCAUX

[15 . . . 4]

ADC Results for VAUX

0x2004

PIODIR0

[7 . . . 0]

PIO0 . . . 7 Pins Direction Setting

0x2005

PIODATA0

[7 . . . 0]

PIO0 . . . 7 Pins Input/Output Data

0x2006

PIOINTEN0

[7 . . . 0]

PIO0 . . . 7 Pins Interrupt Enable

0x2007

PIOFLAG0

[7 . . . 0]

PIO0 . . . 7 Pins Interrupt Status

0x2008

PWMTM

[15 . . . 0]

PWM Period

0x2009

PWMDT

[9 . . . 0]

PWM Dead Time

0x200A

PWMPD

[9 . . . 0]

PWM Pulse Deletion Time

0x200B

PWMGATE

[9 . . . 0]

PWM Gate Drive Configuration

0x200C

PWMCHA

[15 . . . 0]

PWM Channel A Pulsewidth

0x200D

PWMCHB

[15 . . . 0]

PWM Channel B Pulsewidth

0x200E

PWMCHC

[15 . . . 0]

PWM Channel C Pulsewidth

0x200F

PWMSEG

[8 . . . 0]

PWM Segment Select

0x2010

AUXCH0

[7 . . . 0]

AUX PWM Output 0

0x2011

AUXCH1

[7 . . . 0]

AUX PWM Output 1

0x2012

AUXTM0

[7 . . . 0]

Auxiliary PWM Frequency Value

0x2013

AUXTM1

[7 . . . 0]

Auxiliary PWM Frequency Value/Offset

0x2014

Reserved

0x2015

MODECTRL

[8 . . . 0]

Mode Control Register

0x2016

SYSSTAT

[3 . . . 0]

System Status

0x2017

IRQFLAG

[1 . . . 0]

Interrupt Status

0x2018

WDTIMER

[15 . . . 0]

Watchdog Timer

0x2019 . . . 43

Reserved

0x2044

PIODIR1

[0]

PIO8 Pin Direction Setting

0x2045

PIODATA1

[1 . . . 0]

PIO8 Data and Mode Control

0x2046

PIOINTEN1

[0]

PIO8 Pin Interrupt Enable

0x2047

PIOFLAG1

[0]

PIO8 Pin Interrupt Status

0x2048

Reserved

0x2049

PIOSELECT

[7 . . . 0]

PIO0 to PIO7 Mode Select

0x204A . . . 5F

Reserved

0x2060

PWMSYNCWT

[7 . . . 0]

PWMSYNC Pulsewidth

0x2061

PWMSWT

[0]

PWM S/W Trip Bit

0x2062 . . . 67

Reserved

0x2068

ICONST_TRIM

[2. . .0]

ICONST_TRIM

0x2069 . . . 70

Reserved

0x2080

FMCR

[15. . .0]

Flash Memory Control Register

0x2081

FMAR

[11. . .0]

Flash Memory Address Register

0x2082

FMDRH

[13. . .0]

Flash Memory Data Register High

0x2083

FMDRL

[15. . .0]

Flash Memory Data Register Low

0x2084 . . . FF

Reserved

ADMCF328

REV. 0

PWMDT

CLKOUT

SECONDS

PWMDT (R/W)

DM (0x2009)

PWMDT

PWM

PWMTM (R/W)

DM (0x2008)

PWMTM

2 PWMTM

CLKOUT

0 = ENABLE
1 = DISABLE

CH OUTPUT DISABLE

CL OUTPUT DISABLE

BH OUTPUT DISABLE

BL OUTPUT DISABLE

AH OUTPUT DISABLE

AL OUTPUT DISABLE

0 = NO CROSSOVER
1 = CROSSOVER

A CHANNEL CROSSOVER

B CHANNEL CROSSOVER

C CHANNEL CROSSOVER

DM (0x200F)

PWMSEG (R/W)

PWMSYNCWT (R/W)

DM (0x2060)

PWMSYNCWT

PWMSYNC, ON

PWMSYNCWT + 1

CLKOUT

PWMSWT (R/W)

DM (0x2061)

Figure 22. Configuration of PWM Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field--these
bits should always be written as shown.

ADMCF328

REV. 0

0 = SPORT
1 = UART

SPORT1 MODE

SELECT

0 = DR1A
1 = DR1B

SPORT1 DATA

RECEIVE SELECT

0 = DISABLE
1 = ENABLE

PWMSYNC

INTERRUPT

0 = DISABLE
1 = ENABLE

PWMTRIP

INTERRUPT

SYSSTAT (R)

0 = LOW
1 = HIGH

DM (0x2016)

0 = NORMAL
1 = WATCHDOG RESET
OCCURRED

PWMTRIP

PIN STATUS

WATCHDOG

STATUS

PWM TIMER

STATUS

0 = 1ST HALF OF PWM
CYCLE
1 = 2ND HALF OF PWM
CYCLE

MODECTRL (R/W)

DM (0x2015)

0 = SINGLE UPDATE MODE
1 = DOUBLE UPDATE MODE

ADC MUX CONTROL
00 VAUX0
01 VAUX1
10 VAUX2
11 VAUX3

AUXILIARY

PWM SELECT

0 = OFFSET MODE

1 = INDEPENDENT MODE

ADC

COUNTER

SELECT

0 = CLKIN RATE

1 = CLKOUT RATE

IRQFLAG (R)

PWMTRIP INTERRUPT

PWMSYNC INTERRUPT

DM (0x2017)

WDTIMER (W)

DM (0x2018)

0 = NO INTERRUPT
1 = INTERRUPT
OCCURRED

PWM UPDATE

MODE SELECT

Figure 28. Configuration of Status Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field--these
bits should always be written as shown.

Part Number ADMCF328