REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
ADMC331
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
Single Chip DSP
Motor Controller
FUNCTIONAL BLOCK DIAGRAM
ARITHMETIC UNITS
SHIFTER
MAC
ALU
MEMORY
SPORT 1
TIMER
DATA
RAM
1K
16
PROGRAM
ROM
2K 24
PROGRAM
RAM
2K 24
WATCH-
DOG
TIMER
24-BIT
PIO
16-BIT
3-PHASE
PWM
7
ANALOG
INPUTS
2 8 BIT
AUX
PWM
ADSP-2100 BASE
ARCHITECTURE
SERIAL PORTS
PROGRAM
SEQUENCER
DATA
ADDRESS
GENERATORS
DAG 1
DAG 2
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
SPORT 0
TARGET APPLICATIONS
Washing Machines, Refrigerator Compressors, Fans,
Pumps, Industrial Variable Speed Drives
FEATURES
26 MIPS Fixed-Point DSP Core
Single Cycle Instruction Execution (38.5 ns)
ADSP-2100 Family Code Compatible
Independent Computational Units
ALU
Multiplier/Accumulator
Barrel Shifter
Multifunction Instructions
Single Cycle Context Switch
Powerful Program Sequencer
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generator
Memory Configuration
2K 24-Bit Program Memory RAM
2K 24-Bit Program Memory ROM
1K 16-Bit Data Memory RAM
Three-Phase 16-Bit PWM Generator
16-Bit Center-Based PWM Generator
Programmable Deadtime and Narrow Pulse Deletion
Edge Resolution to 38.5 ns
198 Hz Minimum Switching Frequency
Double/Single Duty Cycle Update Mode Control
Programmable PWM Pulsewidth
Suitable for AC Induction and Synchronous Motors
Special Signal Generation for Switched Reluctance
Motors
Special Crossover Function for Brushless DC Motors
Individual Enable and Disable for all PWM Outputs
High Frequency Chopping Mode for Transformer
Coupled Gate Drives
Hardwired Polarity Control
External
PWMTRIP Pin
Seven Analog Input Channels
Acquisition Synchronized to PWM Switching
Frequency
Conversion Speed Control
24 Bits of Digital I/O Port
Bit Configurable as Input or Output
Change of State Interrupt Support
Two 8-Bit Auxiliary PWM Timers
Synchronized Analog Output
Programmable Frequency
0% to 100% Duty Cycle
(Continued on page 7)
2
REV. B
ADMC331SPECIFICATIONS
(V
DD
= +5 V 10%, GND = SGND = 0 V, T
A
= 40 C to +85 C, unless otherwise noted)
Parameter
Min
Typ
Max
Units
Conditions/Comments
ANALOG-TO-DIGITAL CONVERTER
Charging Capacitor = 1000 pF
2.5 kHz Sample Frequency
Signal Input
0.3
3.3
1
V
Resolution
12
2
Bits
No Missing Codes
Converter Linearity
2
12
LSBs
Zero Offset
5
50
mV
Channel-to-Channel Comparator Match
22
mV
Comparator Delay
600
ns
Current Source
10.16
12.7
15.24
µA
Current Source Linearity
2
%
ELECTRICAL CHARACTERISTICS
V
IL
Logic Low
0.8
V
V
IH
Logic High
2
V
V
OL
Low Level Output Voltage
0.4
V
I
OL
= 2 mA
V
OL
Low Level Output Voltage (XTAL)
0.5
V
I
OL
= 2 mA
V
OH
High Level Output Voltage
4
V
I
OH
= 0.5 mA
I
IL
Low Level Input Current
10
µA
V
IN
= 0 V
I
IH
High Level Input Current
10
µA
V
IN
= V
DD
I
IH
Hi-Level
PWMTRIP, PIO0PIO23 Current
100
µA
@ V
DD
= max, V
IN
= V
DD
max
I
IH
Hi-Level PWMPOL/
PWMSR Current
10
µA
@ V
DD
= max, V
IN
= V
DD
max
I
IL
Lo-Level
PWMTRIP, PIO0PIO23 Current
10
µA
@ V
DD
= max, V
IN
= 0 V
I
IL
Lo-Level PWMPOL/
PWMSR Current
100
µA
@ V
DD
= max, V
IN
= 0 V
I
DD
Supply Current (Dynamic)
120
mA
13 MHz DSP Clock
I
DD
Supply Current (Idle)
60
mA
13 MHz DSP Clock
REFERENCE VOLTAGE OUTPUT
Voltage Level
2.2
2.55
2.9
V
100
µA Load
Output Voltage Change T
MIN
to T
MAX
20
mV
16-BIT PWM TIMER
Counter Resolution
16
Bits
Edge Resolution (Single Update Mode)
76.9
ns
13 MHz CLKIN
Edge Resolution (Double Update Mode)
38.5
ns
13 MHz CLKIN
Programmable Deadtime Range
0
78
µs
13 MHz CLKIN
Programmable Deadtime Increments
76.9
ns
13 MHz CLKIN
Programmable Pulse Deletion Range
0
78
µs
13 MHz CLKIN
Programmable Pulse Deletion Increments
76.9
ns
13 MHz CLKIN
PWM Frequency Range
0.198
kHz
13 MHz CLKIN
PWMSYNC Pulsewidth (T
CRST
)
0.077
9.8
µs
13 MHz CLKIN
Gate Drive Chop Frequency Range
0.02
6.5
MHz
13 MHz CLKIN
AUXILIARY PWM TIMERS
Resolution
8
Bits
PWM Frequency
0.051
6.5
MHz
13 MHz CLKIN
NOTES
1
Signal input max V = 3.5 V if V
DD
= 5 V
± 5%.
2
Resolution varies with PWM switching frequency (13 MHz Clock in Double Update mode), 50.7 kHz = 9 bits, 6.3 kHz = 12 bits.
Specifications subject to change without notice.
ADMC331
3
REV. B
TIMING PARAMETERS
Parameter
Min
Max
Unit
Clock Signals
t
CK
is defined as 0.5 t
CKI
. The ADMC331 uses an input clock with a frequency equal
to half the instruction rate; a 13 MHz input clock (which is equivalent to 76.9 ns)
yields a 38.5 ns processor cycle (equivalent to 26 MHz). t
CK
values within the range
of 0.5 t
CKI
period should be substituted for all relevant timing parameters to obtain
specification value.
Example: t
CKH
= 0.5 t
CK
10 ns = 0.5 (38.5 ns) 10 ns = 9.25 ns.
Timing Requirements:
t
CKI
CLKIN Period
76.9
150
ns
t
CKIL
CLKIN Width Low
20
ns
t
CKIH
CLKIN Width High
20
ns
Switching Characteristics:
t
CKL
CLKOUT Width Low
0.5 t
CK
10
ns
t
CKH
CLKOUT Width High
0.5 t
CK
10
ns
t
CKOH
CLKIN High to CLKOUT High
0
20
ns
Control Signals
Timing Requirement:
t
RSP
RESET Width Low
5 t
CK
1
ns
PWM Shutdown Signals
Timing Requirement:
t
PWMTPW
PWMTRIP Width Low
2 t
CK
ns
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
CLKIN
CLKOUT
t
CKOH
t
CKI
t
CKIH
t
CKH
t
CKL
t
CKIL
Figure 1. Clock Signals
ADMC331
4
REV. B
Parameter
Min
Max
Unit
Serial Ports
Timing Requirements:
t
SCK
SCLK Period
100
ns
t
SCS
DR/TFS/RFS Setup before SCLK Low
15
ns
t
SCH
DR/TFS/RFS Hold after SCLK Low
20
ns
t
SCP
SCLK
IN
Width
40
ns
Switching Characteristics:
t
CC
CLKOUT High to SCLK
OUT
0.25 t
CK
0.25 t
CK
+ 20
ns
t
SCDE
SCLK High to DT Enable
0
ns
t
SCDV
SCLK High to DT Valid
30
ns
t
RH
TFS/RFS
OUT
Hold after SCLK High
0
ns
t
RD
TFS/RFS
OUT
Delay from SCLK High
30
ns
t
SCDH
DT Hold after SCLK High
0
ns
t
SCDD
SCLK High to DT Disable
30
ns
t
TDE
TFS (Alt) to DT Enable
0
ns
t
TDV
TFS (Alt) to DT Valid
25
ns
t
RDV
RFS (Multichannel, Frame Delay Zero) to DT Valid
30
ns
t
CC
t
CC
t
SCH
t
SCS
t
RD
t
RH
t
SCP
t
SCP
t
SCK
t
SCDV
t
SCDE
t
SCDH
t
SCDD
t
TDE
t
TDV
t
RDV
CLKOUT
SCLK
DR
RFS
IN
TFS
IN
RFS
OUT
TFS
OUT
DT
TFS
(ALTERNATE
FRAME MODE)
RFS
(MULTICHANNEL MODE,
FRAME DELAY 0 [MFD = 0])
Figure 2. Serial Ports
ADMC331
5
REV. B
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (V
DD
) . . . . . . . . . . . . . . . . . . 0.3 V to +7.0 V
Supply Voltage (AV
DD
) . . . . . . . . . . . . . . . . . 0.3 V to +7.0 V
Input Voltage . . . . . . . . . . . . . . . . . . . . 0.3 V to V
DD
+ 0.3 V
Output Voltage Swing . . . . . . . . . . . . . . 0.3 V to V
DD
+ 0.3 V
Operating Temperature Range (Ambient) . . . 40
°C to +85°C
Storage Temperature Range . . . . . . . . . . . . 65
°C to +150°C
Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . +280
°C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
ORDERING GUIDE
Temperature
Instruction
Package
Package
Model
Range
Rate
Description
Option
ADMC331BST
40
°C to +85°C
26 MHz
80-Lead Plastic Thin Quad Flatpack (TQFP)
ST-80
ADMC331-ADVEVALKIT
Development Tool Kit
ADMC331-PB
Evaluation/Processor Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADMC331 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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