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Part Number ADM3070E

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3.3 V, ±15 kV ESD-Protected, Half- and
Full-Duplex, RS-485/RS-422 Transceivers
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E
Rev. 0
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
FEATURES
TIA/EIA RS-485/RS-422 compliant
±15 kV ESD protection on RS-485 input/output pins
Data rates
ADM3070E/ADM3071E/ADM3072E: 250 kbps
ADM3073E/ADM3074E/ADM3075E: 500 kbps
ADM3076E: 16 Mbps
Half- and full-duplex options
True fail-safe receiver inputs
Up to 256 nodes on the bus
-40°C to +125°C temperature option
Hot-swap input structure on DE and RE pins
Reduced slew rates for low EMI
Low power shutdown current (all except
ADM3071E/ADM3074E)
Outputs high-Z when disabled or powered off
Common-mode input range: -7 V to +12 V
Thermal shutdown and short-circuit protection
8-lead and 14-lead narrow SOIC packages
APPLICATIONS
Power/energy metering
Industrial control
Lighting systems
Telecommunications
Security systems
Instrumentation
GENERAL DESCRIPTION
The ADM3070E to ADM3076E are 3.3 V, low power data
transceivers with ±15 kV ESD protection suitable for full- and
half-duplex communication on multipoint bus transmission
lines. They are designed for balanced data transmission, and they
comply with TIA/EIA standards RS-485 and RS-422.
The devices have an unit load receiver input impedance,
which allows up to 256 transceivers on a bus. Because only one
driver should be enabled at any time, the output of a disabled or
powered-down driver is tristated to avoid overloading the bus.
The receiver inputs have a true fail-safe feature, which
eliminates the need for external bias resistors and ensures a
logic high output level when the inputs are open or shorted.
This guarantees that the receiver outputs are in a known state
before communication begins and when communication ceases.
FUNCTIONAL BLOCK DIAGRAMS
ADM3070E/
ADM3073E/
ADM3076E
RO
RE
DE
DI
V
CC
A
B
Z
Y
GND
R
D
06
28
5
-
00
1
Figure 1.
ADM3071E/
ADM3074E
RO
DI
V
CC
A
B
Z
Y
GND
R
D
0
628
5-
00
2
.
Figure 2.
ADM3072E/
ADM3075E
RO
RE
DE
DI
V
CC
A
B
GND
D
R
062
85
-
0
03
Figure 3.
(continued on Page 3)
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E
Rev. 0 | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 4
Timing Specifications--ADM3070E/ADM3071E/
ADM3072E.................................................................................... 5
Timing Specifications--ADM3073E/ADM3074E/
ADM3075E.................................................................................... 6
Timing Specifications--ADM3076E ......................................... 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Test Circuits and Switching Characteristics................................ 10
Typical Performance Characteristics ........................................... 12
Circuit Description......................................................................... 15
Function Tables........................................................................... 15
Receiver Fail-Safe ....................................................................... 15
Hot-Swap Capability .................................................................. 16
Line Length vs. Data Rate ......................................................... 16
±15 kV ESD Protection ............................................................. 16
Human Body Model .................................................................. 16
256 Transceivers on the Bus...................................................... 16
Reduced EMI and Reflections .................................................. 16
Low Power Shutdown Mode..................................................... 17
Driver Output Protection.......................................................... 17
Typical Applications................................................................... 17
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 20
REVISION HISTORY
8/06--Revision 0: Initial Version
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E
Rev. 0 | Page 3 of 20
GENERAL DESCRIPTION
(continued from Page 1)
The driver outputs are slew rate limited, in order to reduce EMI
and data errors caused by reflections from improperly
terminated buses. Excessive power dissipation caused by bus
contention or by output shorting is prevented with a thermal
shutdown circuit.
The parts are fully specified over the industrial tem-
perature ranges and are available in 8-lead and 14-lead
narrow SOIC packages.
Table 1. Selection Table
Part No.
Half/Full
Duplex
Data Rate
(Mbps)
Slew Rate
Limited
Driver/Receiver
Enable
Low Power
Shutdown
±15 kV ESD Protection
on Bus Pins
Pin
Count
ADM3070E Full
0.25
Yes
Yes
Yes
Yes
14
ADM3071E Full
0.25
Yes
No
No
Yes
8
ADM3072E Half
0.25
Yes
Yes
Yes
Yes
8
ADM3073E Full
0.5
Yes
Yes
Yes
Yes
14
ADM3074E Full
0.5
Yes
No
No
Yes
8
ADM3075E Half
0.5
Yes
Yes
Yes
Yes
8
ADM3076E Full
16
No
Yes
Yes
Yes
14
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E
Rev. 0 | Page 4 of 20
SPECIFICATIONS
V
CC
= 3.3 V ± 10%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2. ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E
Parameter
Symbol Min
Typ Max Unit Test
Conditions/Comments
DRIVER
Differential Outputs
Differential Output Voltage
V
OD
2.0 V
CC
V R
L
= 100 (RS-422) (see Figure 7)
1.5
V
CC
V R
L
= 54 (RS-485) (see Figure 7)
V
CC
V No
load
|V
OD
| for Complementary Output States
1
V
OD
0.2
V
R = 54 or 100 (see Figure 7)
Common-Mode Output Voltage
V
OC
V
CC
/2
3
V
R = 54 or 100 (see Figure 7)
|V
OC
| for Complementary Output States
1
V
OC
0.2
V
R = 54 or 100 (see Figure 7)
Short-Circuit Output Current
I
OSD
40 250
mA
0
V
<
V
OUT
< 12 V
-
250
-
40 mA
-
7 V < V
OUT
< V
CC
Short-Circuit Foldback Output Current
I
OSDF
20 mA
(V
CC
-
1 V) < V
OUT
< 12 V
-
20 mA
-
7 V < V
OUT
< +1 V
Output Leakage (Y, Z) Full Duplex
I
O
125
A
DE = 0 V, RE = 0 V, V
CC
= 0 V or 3.6 V, V
IN
= 12 V
-
100 A
DE = 0 V, RE = 0 V, V
CC
= 0 V or 3.6 V, V
IN
= -7 V
Logic Inputs
Input High Voltage
V
IH
2.0 V
DE, DI, RE
Input Low Voltage
V
IL
0.8
V
DE, DI, RE
Input Hysteresis
V
HYS
100
mV
DE, DI, RE
Logic Input Current
I
IN1
±1
A
DE, DI, RE
Input Impedance First Transition
1
10
k
DE
Thermal Shutdown Threshold
T
TS
175
°C
Thermal Shutdown Hysteresis
T
TSH
15
°C
RECEIVER
Differential Inputs
Differential Input Threshold Voltage
V
TH
-
200
-
125
-
50 mV
-
7 V < V
CM
< +12 V
Input Hysteresis
V
TH
15
mV
V
A
+ V
B
= 0 V
Input Resistance (A, B)
R
IN
96 k
-
7 V < V
CM
< +12 V
Input Current (A, B)
I
A, B
125
A
DE = 0 V, V
CC
= 0 V or 3.6 V, V
IN
= 12 V
-
100
A
DE = 0 V, V
CC
= 0 V or 3.6 V, V
IN
= -7 V
RO Logic Output
Output High Voltage
V
OH
V
CC
-
0.6
V
I
OUT
= -1 mA
Output Low Voltage
V
OL
0.4
V
I
OUT
= 1 mA
Short-Circuit Output Current
I
OSR
±80
mA
0
V
<
V
RO
< V
CC
Tristate Output Leakage Current
I
OZR
±1
A
V
CC
= 3.6 V, 0 V < V
OUT
< V
CC
POWER SUPPLY
Supply Current
I
CC
0.8
1.5
mA
No load, DE = V
CC
, RE = 0 V
0.8
1.5
mA
No load, DE = V
CC
, RE = V
CC
0.8
1.5
mA
No load, DE = 0 V, RE = 0 V
Shutdown Current
I
SHDN
0.05
10
A
DE = 0 V, RE = V
CC
ESD PROTECTION
A, B, Y, Z Pins
±15
kV
Human body model
All Pins Except A, B, Y, Z Pins
±4
kV
Human body model
1
|V
OD
| and |V
OC
| are the changes in V
OD
and V
OC
, respectively, when the DI input changes state.
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E
Rev. 0 | Page 5 of 20
TIMING SPECIFICATIONS--ADM3070E/ADM3071E/ ADM3072E
V
CC
= 3.3 V ± 10%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
Symbol Min Typ Max Unit Test
Conditions/Comments
DRIVER
Maximum Data Rate
250
kbps
Propagation Delay, Low to High Level
t
DPLH
250
1500
ns C
L
= 50 pF
, R
L
= 54 (see Figure 8 and Figure 9)
Propagation Delay, High to Low Level
t
DPHL
250
1500
ns C
L
= 50 pF
, R
L
= 54 (see Figure 8 and Figure 9)
Rise Time/Fall Time
t
DR
/t
DF
350
1600
ns C
L
= 50 pF
, R
L
= 54 (see Figure 8 and Figure 9)
|t
DPLH
- t
DPHL
| Differential Driver Output Skew
t
DSKEW
200
ns C
L
= 50 pF
, R
L
= 54 (see Figure 8 and Figure 9)
Enable to Output High
t
DZH
2500
ns
(See
Figure 10)
Enable to Output Low
t
DZL
2500
ns
(See
Figure 11)
Disable Time from Low
t
DLZ
100
ns
(See
Figure 11)
Disable Time from High
t
DHZ
100
ns
(See
Figure 10)
Enable Time from Shutdown to High
t
DZH(SHDN)
5500 ns
(See
Figure 10)
Enable Time from Shutdown to Low
t
DZL(SHDN)
5500 ns
(See
Figure 11)
RECEIVER
Propagation Delay, Low to High Level
t
RPLH
200
ns C
L
= 15 pF (see Figure 12 and Figure 13)
Propagation Delay, High to Low Level
t
RPHL
200
ns C
L
= 15 pF (see Figure 12 and Figure 13)
|t
RPLH
- t
RPHL
| Output Skew
t
RSKEW
30 ns C
L
= 15 pF (see Figure 12 and Figure 13)
Enable to Output High
t
RZH
50
ns
(See
Figure 14)
Enable to Output Low
t
RZL
50
ns
(See
Figure 14)
Disable Time from Low
t
RLZ
50
ns
(See
Figure 14)
Disable Time from High
t
RHZ
50
ns
(See
Figure 14)
Enable Time from Shutdown to High
t
RZH(SHDN)
4000 ns
(See
Figure 14)
Enable Time from Shutdown to Low
t
RZL(SHDN)
4000 ns
(See
Figure 14)
TIME TO SHUTDOWN
t
SHDN
50
200
600
ns