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2 pF Off Capacitance, 1 pC Charge Injection,

±15 V/12 V 4:1

iCMOSTM Multiplexer

Preliminary Technical Data

ADG1204

Rev. PrD

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700

www.analog.com

Fax: 781.326.8703

FEATURES

2 pF off capacitance
1 pC charge injection
33 V supply range
120 on resistance
Fully specified at +12 V, ±15 V
No V

supply required

3 V logic-compatible inputs
Rail-to-rail operation
14-lead TSSOP and 12-lead LFCSP
Typical power consumption: <0.03 µW

APPLICATIONS

Automatic test equipment
Data aquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Communication systems

FUNCTIONAL BLOCK DIAGRAM

ADG1204

1 OF 4

DECODER

04779-0-001

Figure 1.

GENERAL DESCRIPTION

The ADG1204 is a CMOS analog multiplexer, comprising four
single channels designed on an iCMOS process. iCMOS
(industrial-CMOS) is a modular manufacturing process that
combines high voltage CMOS (complementary metal-oxide
semiconductor) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 30-V operation in a footprint that no other genera-
tion of high voltage parts has been able to achieve. Unlike
analog ICs using conventional CMOS processes, iCMOS
components can tolerate high supply voltages, while providing
increased performance, dramatically lower power consumption,
and reduced package size.

The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-and-
hold applications, where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth make
the parts suitable for video signal switching. iCMOS construc-
tion ensures ultralow power dissipation, making the parts
ideally suited for portable and battery powered instruments.

The ADG1204 switches one of four inputs to a common output,
D, as determined by the 3-bit binary address lines, A0, A1, and
EN. Logic 0 on the EN pin disables the device. Each switch
conducts equally well in both directions when on, and has an
input signal range that extends to the supplies. In the off condi-
tion, signal levels up to the supplies are blocked. All switches
exhibit break-before-make switching action. Inherent in the
design is low charge injection for minimum transients when
switching the digital inputs.

PRODUCT HIGHLIGHTS

2 pF off capacitance (±15 V supply).

1 pC charge injection.

3 V logic-compatible digital inputs:
V

= 2.0 V, V

= 0.8 V

No V

logic power supply required.

Ultralow power dissipation: <0.03 µW.

14-lead TSSOP and 12-lead 3 mm × 3 mm LFCSP package.

ADG1204

Preliminary Technical Data

Rev. PrD | Page 2 of 16

TABLE OF CONTENTS

Specifications..................................................................................... 3

Dual Supply ................................................................................... 3

Single Supply ................................................................................. 5

Absolute Maximum Ratings............................................................ 7

Truth Table .................................................................................... 7

ESD Caution.................................................................................. 7

Pin Configurations and Function Descriptions ............................8

Terminology .......................................................................................9

Typical Performance Characteristics ........................................... 10

Test Circuits..................................................................................... 13

Outline Dimensions ....................................................................... 15

Ordering Guide .......................................................................... 15

REVISION HISTORY

11/04--Revision PrD: Preliminary Version

Preliminary Technical Data

ADG1204

Rev. PrD | Page 3 of 16

SPECIFICATIONS

DUAL SUPPLY

= 15 V ± 10%, V

= -15 V, GND = 0 V, unless otherwise noted.

Table 1.

Parameter

25°C

85°C

Y Version

Unit Test

Conditions/Comments

ANALOG SWITCH

Analog Signal Range

to V

On Resistance (R

)

120

160

180

typ

= ±10 V, I

= -10 mA; Figure 21

max

On Resistance Match between

Channels (R

)

typ

= ±10 V, I

= -10 mA

max

On Resistance Flatness (R

FLAT(ON)

)

typ

= -5 V, 0 V, +5 V; I

= -10 mA

max

LEAKAGE CURRENTS

= +10 V, V

= -10 V

Source Off Leakage, I

(Off)

±0.01

nA typ

= 0 V/10 V, V

= 10 V/0 V; Figure 22

±0.5

±1

±5

nA max

Drain Off Leakage, I

(Off)

±0.01

nA typ

= 0 V/10 V, V

= 10 V/0 V; Figure 22

±0.5

±1

±5

nA max

Channel On Leakage, I

, I

(On)

±0.04

nA typ

= V

= 0 V or 10 V; Figure 23

±1

±2

±5

nA max

DIGITAL INPUTS

Input High Voltage, V

INH

2.0

V min

Input Low Voltage, V

INL

0.8

V max

Input Current, I

INL

or I

0.005

µA typ

= V

INL

or V

INH

±0.5

µA max

Digital Input Capacitance, C

pF typ

DYNAMIC CHARACTERISTICS

Transition Time, t

TRANS

ns typ

= 50 , C

= 35 pF

ns max

= ±10 V; Figure 24

(EN)

ns typ

= 50 , C

= 35 pF

ns max

= ±10 V; Figure 24

OFF

(EN)

ns typ

= 50 , C

= 35 pF

ns max

= ±10 V; Figure 24

Break-before-Make Time Delay, t

ns typ

= 50 , C

= 35 pF

ns min

= V

= 10 V; Figure 25

Charge Injection

pC typ

= 0 V, R

= 0 , C

= 1 nF; Figure 26

Off Isolation

dB typ

= 50 , C

= 5 pF, f = 1 MHz; Figure 27

Channel-to-Channel Crosstalk

dB typ

= 50 , C

= 5 pF, f = 1 MHz; Figure 28

Total Harmonic Distortion + Noise

0.002

% typ

= 600 , 5 V rms, f = 20 Hz to 20 kHz

-3 dB Bandwidth

700

MHz typ

= 50 , C

= 5 pF; Figure 29

(Off)

pF typ

(Off)

pF typ

, C

(On)

pF typ

POWER REQUIREMENTS

= +16.5 V, V

= -16.5 V

0.001

µA typ

Digital Inputs = 0 V or V

5.0

µA max

150

µA typ

Digital Inputs = 5 V

300

µA max

0.001

µA typ

Digital Inputs = 0 V or V

5.0

µA max

ADG1204

Preliminary Technical Data

Rev. PrD | Page 4 of 16

Parameter

25°C

85°C

Y Version

Unit Test

Conditions/Comments

GND

0.001

µA typ

Digital Inputs = 0 V or V

5.0

µA max

GND

150

µA typ

Digital Inputs = 5 V

300

µA max

Y Version temperature range is -40°C to +125°C.

Guaranteed by design, not subject to production test.

= +5 V ± 10%, V

= -5 V ± 10%, GND = 0 V, unless otherwise noted.

Table 2.

Parameter

25°C 85°C Y

Version

Unit Test

Conditions/Comments

ANALOG SWITCH

Analog Signal Range

to V

On Resistance (R

)

220

typ

= ±3.3 V, I

= -10 mA; Figure 21

max

On Resistance Match between

Channels (R

)

typ

max

= ±3.3 V, I

= -10 mA

On Resistance Flatness (R

FLAT(ON)

)

typ

= ±3.3 V, I

= -10 mA

max

LEAKAGE CURRENTS

= 5.5 V, V

= -5.5 V

Source Off Leakage, I

(Off)

±0.01

nA typ

= ±4.5 V, V

= ±4.5 V; Figure 22

±0.5

±1

±5

nA max

Drain Off Leakage, I

(Off)

±0.01

nA typ

= ±4.5 V, V

= ±4.5 V; Figure 22

±0.5

±1

±5

nA max

Channel On Leakage, I

, I

(On)

±0.04

nA typ

= V

= ±4.5 V; Figure 23

±1

±2

±5

nA max

DIGITAL INPUTS

Input High Voltage, V

INH

2.0

V min

Input Low Voltage, V

INL

0.8

V max

Input Current, I

INL

or I

INH

0.005

µA typ

= V

INL

or V

INH

±0.5

µA max

Digital Input Capacitance, C

pF typ

DYNAMIC CHARACTERISTICS

160

typ

= 300 , C

= 35 pF

ns max

= 3 V; Figure 24

OFF

typ

= 300 , C

= 35 pF

ns max

= 3 V; Figure 24

Break-before-Make Time Delay, t

typ

= 300 , C

= 35 pF

min

= V

= 3 V; Figure 25

Charge Injection

pC typ

= 0 V, R

= 0 , C

= 1 nF; Figure 26

pC max

Off Isolation

dB typ

= 50 , C

= 5 pF, f = 1 MHz; Figure 27

Channel-to-Channel Crosstalk

dB typ

= 50 , C

= 5 pF, f = 1 MHz; Figure 28

-3 dB Bandwidth

MHz typ

= 50 , C

= 5 pF; Figure 29

(Off)

pF typ

f = 1 MHz

(Off)

pF typ

f = 1 MHz

, C

(On)

100

pF typ

f = 1 MHz

Preliminary Technical Data

ADG1204

Rev. PrD | Page 5 of 16

Parameter

25°C 85°C Y

Version

Unit Test

Conditions/Comments

POWER REQUIREMENTS

= +5.5 V, V

= -5.5 V

0.001

µA typ

Digital Inputs = 0 V or 5.5 V

5.0

µA

max

0.001

µA typ

Digital Inputs = 0 V or 5.5 V

5.0

µA

max

Y Version temperature range is -40°C to +125°C.

Guaranteed by design, not subject to production test.

SINGLE SUPPLY

= 12 V ± 10%, V

= 0 V, GND = 0 V, unless otherwise noted.

Table 3.

Parameter 25°C

85°C

Version

Unit Test

Conditions/Comments

ANALOG SWITCH

Analog Signal Range

0 V to V

On Resistance (R

)

220

typ

= 10 V, I

= -10 mA; Figure 21

max

On Resistance Match between

typ

= 10 V, I

= -10 mA

Channels (R

)

max

On Resistance Flatness (R

FLAT(ON)

)

typ

= 3 V, 6 V, 9 V; I

= -10 mA

LEAKAGE CURRENTS

= 12 V

Source Off Leakage, I

(Off)

±0.01

nA typ

= 1 V/10 V, V

= 10 V/1 V; Figure 22

±0.5

±1

±5

nA max

Drain Off Leakage, I

(Off)

±0.01

nA typ

= 1 V/10 V, V

= 10 V/1 V; Figure 22

±0.5

±1

±5

nA max

Channel On Leakage, I

, I

(On)

±0.04

nA typ

= V

= 1 V or 10 V; Figure 23

±1

±2

±5

nA max

DIGITAL INPUTS

Input High Voltage, V

INH

2.0

V min

Input Low Voltage, V

INL

0.8

V max

Input Current, I

INL

or I

INH

0.001

µA typ

= V

INL

or V

INH

±0.5

µA max

Digital Input Capacitance, C

pF typ

DYNAMIC CHARACTERISTICS

Transition Time, t

TRANS

ns typ

= 50 , C

= 35 pF

ns max

= ±10 V; Figure 24

(EN)

ns typ

= 50 , C

= 35 pF

ns max

= 8 V; Figure 24

OFF

(EN)

ns typ

= 50 , C

= 35 pF

ns max

= 8 V; Figure 24

Break-before-Make Time Delay, t

ns typ

= 50 , C

= 35 pF

ns min

= V

= 8 V; Figure 25

Charge Injection

pC typ

= 0 V, R

= 0 , C

= 1 nF; Figure 26

Off Isolation

dB typ

= 50 , C

= 5 pF, f = 1 MHz; Figure 27

Channel-to-Channel Crosstalk

dB typ

= 50 , C

= 5 pF, f = 1 MHz; Figure 28

-3 dB Bandwidth

700

MHz typ

= 50 , C

= 5 pF; Figure 29

(Off)

pF typ

(Off)

pF typ

, C

(On)

pF typ

Preliminary Technical Data

ADG1204

Rev. PrD | Page 7 of 16

ABSOLUTE MAXIMUM RATINGS

= 25°C, unless otherwise noted.

Table 4.

Parameter Rating

to V

38 V

to GND

-0.3 V to +25 V

to GND

+0.3 V to -25 V

Analog Inputs

- 0.3 V to V

+ 0.3 V

Digital Inputs

GND - 0.3 V to V

+ 0.3 V or

30 mA, whichever occurs first

Peak Current, S or D

100 mA (pulsed at 1 ms, 10%
duty cycle max)

Continuous Current, S or D

30 mA

Operating Temperature Range

Industrial (B Version)

-40°C to +85°C

Automotive (Y Version)

-40°C to +125°C

Storage Temperature Range

-65°C to +150°C

Junction Temperature

150°C

14-Lead TSSOP,

Thermal

Impedance

150.4°C/W

12-Lead LFCSP,

Thermal

Impedance

30.4°C/W

Lead Temperature, Soldering

Vapor Phase (60 s)

215°C

Infrared (15 s)

220°C

Overvoltages at IN, S, or D are clamped by internal diodes. Current should be

limited to the maximum ratings given.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.

TRUTH TABLE

Table 5.

EN A1 A0 S1 S2 S3 S4

Off

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

ADG1204

Preliminary Technical Data

Rev. PrD | Page 8 of 16

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TOP VIEW

ADG1204

NC = NO CONNECT

GND

04779-0-002

Figure 2. TSSOP Pin Configuration

PIN 1
INDICATOR

NC = NO CONNECT

9 GND

8 V

7 S3

4
D

1
2

1
1

1
0

TOP VIEW

(Not to Scale)

ADG1204

04779-0-003

Figure 3. LFCSP Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

TSSOP LFCSP Mnemonic Function

Logic Control Input.

2 12

Active High Digital Input. When low, the device is disabled and all switches are off.
When high, Ax logic inputs determine on switches.

3 1 V

Most Negative Power Supply Potential.

Source Terminal. Can be an input or an output.

Drain Terminal. Can be an input or an output.

79 5 NC

Connection.

Source Terminal. Can be an input or an output.

12 8 V

Most Positive Power Supply Potential.

GND

Ground (0 V) Reference.

Logic Control Input.

Preliminary Technical Data

ADG1204

Rev. PrD | Page 9 of 16

TERMINOLOGY

The positive supply current.

The negative supply current.

)

The analog voltage on Terminals D and S.

The ohmic resistance between D and S.

FLAT(ON)

Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.

(Off)

The source leakage current with the switch off.

(Off)

The drain leakage current with the switch off.

, I

(On)

The channel leakage current with the switch on.

INL

The maximum input voltage for Logic 0.

INH

The minimum input voltage for Logic 1.

INL

INH

)

The input current of the digital input.

(Off)

The off switch source capacitance, which is measured with
reference to ground.

(Off)

The off switch drain capacitance, which is measured with
reference to ground.

, C

(On)

The on switch capacitance, which is measured with reference to
ground.

The digital input capacitance.

(EN)

The delay between applying the digital control input and the
output switching on. See Figure 24, Test Circuit 4.

OFF

(EN)

The delay between applying the digital control input and the
output switching off.

Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.

Off Isolation
A measure of unwanted signal coupling through an off switch.

Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.

Bandwidth
The frequency at which the output is attenuated by 3 dB.

On Response
The frequency response of the on switch.

Insertion Loss
The loss due to the on resistance of the switch.

THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.

TRANS

The delay time between the 50% and 90% points of the digital
input and switch on condition when switching from one
address state to another.

Preliminary Technical Data

ADG1204

Rev. PrD | Page 13 of 16

TEST CIRCUITS

04779-0-020

(OFF)

04779-0-021

(ON)

NC = No Connect

04779-0-022

Figure 21. Test Circuit 1--On Resistance

Figure 22. Test Circuit 2--Off Leakage

Figure 23. Test Circuit 3--On Leakage

GND

35pF

OUT

50%

90%

ADDRESS

DRIVE (V

)
)

OUT

+2.4V

TRANSITION

0.1

04779-0-023

Figure 24. Test Circuit 4--Address to Output Switching Times

ADDRESS

DRIVE (V

)

OUT

GND

35pF

OUT

+2.4V

0.1

04779-0-024

BBM

80%

Figure 25. Test Circuit 5--Break-before-Make Time

Delay.

ENABLE

DRIVE (V

)

GND

35pF

OUT

0.1

04779-0-025

OFF

(EN)

50%

0.9V0

OUTPUT

Figure 26. Test Circuit 6--Enable to Output Switching Delay

ADG1204

Preliminary Technical Data

Rev. PrD | Page 14 of 16

GND

SW OFF

INJ

= C

OUT

SW ON

SW OFF

SW ON

SW OFF

DECODER

OUT

1nF

04779-0-026

Figure 27. Test Circuit 7-- Charge Injection

OUT

NETWORK

ANALYZER

OFF ISOLATION = 20 LOG

OUT

0.1

GND

04779-0-027

Figure 28. Test Circuit 8--Off Isolation

OUT

NETWORK

ANALYZER

INSERTION LOSS = 20 LOG

OUT

WITH SWITCH

OUT

WITHOUT SWITCH

0.1

GND

04779-0-028

Figure 29. Test Circuit 9--Bandwidth

CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG

OUT

GND

OUT

NETWORK

ANALYZER

R
50

0.1

04779-0-029

Figure 30. Test Circuit 10--Channel-to-Channel Crosstalk

OUT

AUDIO PRECISION

600

V p-p

0.1

GND

04779-0-030

Figure 31. Test Circuit 11--THD + Noise

Preliminary Technical Data

ADG1204

Rev. PrD | Page 15 of 16

OUTLINE DIMENSIONS

4.50
4.40
4.30

6.40

BSC

PIN 1

5.10
5.00
4.90

0.65

BSC

SEATING

PLANE

0.15
0.05

0.30
0.19

1.20

MAX

1.05
1.00
0.80

0.20
0.09

8°
0°

0.75
0.60
0.45

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153AB-1

Figure 32. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimension shown in millimeters

*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1

EXCEPT FOR EXPOSED PAD DIMENSION.

0.50

BSC

0.60 MAX

PIN 1

INDICATOR

0.75
0.55
0.35

0.25 MIN

0.45

TOP

VIEW

12 MAX

0.80 MAX
0.65 TYP

PIN 1

INDICATOR

1.00
0.85
0.80

0.30
0.23
0.18

0.05 MAX
0.02 NOM

0.20 REF

*1.45

1.30 SQ
1.15

2.75

BSC SQ

3.00

BSC SQ

COPLANARITY

0.08

EXPOSED PAD

(BOTTOM VIEW)

SEATING

PLANE

Figure 33. 12-Lead Lead Frame Chip Scale Package [VQ_LFCSP]

3 mm × 3 mm Body, Very Thin Quad

(CP-12-1)

Dimensions shown in inches and (millimeters)

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

ADG1204YRU

-40°C to +125°C

Thin Shrink Small Outline Package (TSSOP)

RU-14

ADG1204YCP

-40°C to +125°C

Lead Frame Chip Scale Package (LFCSP)

CP-12-1

Part Number ADG1204

Document Outline