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Part Number ADF7020-1

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ADF7020-1 High Performance, ISM Band, FSK/ASK Transceiver IC Preliminary Data Sheet (Rev. PrE)
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High Performance, ISM Band,
FSK/ASK Transceiver IC
Preliminary Technical Data
ADF7020-1
Rev. PrE
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.


One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Low power, low IF transceiver
Frequency bands:
135 MHz to 650 MHz
Data rates supported
0.15 kbps to 200 kbps, FSK
0.15 kbps to 64 kbps, ASK
2.3 V to 3.6 V power supply
Programmable output power
-16 dBm to +13 dBm in 0.3 dBm steps
Receiver sensitivity
-119 dBm at 1 kbps, FSK
-112 dBm at 9.6 kbps, FSK
-106.5 dBm at 9.6 kbps, ASK
Low power consumption
18 mA in receive mode
27 mA in transmit mode (10 dBm output)
On-chip VCO and fractional-N PLL
On-chip 7-bit ADC and temperature sensor
Fully automatic frequency control loop (AFC) compensates
for lower tolerance crystals
Digital RSSI
Integrated TRx switch
Leakage current <1 A in power-down mode
APPLICATIONS
Low cost wireless data transfer
Remote control/security systems
Wireless metering
Keyless entry
Home automation
Process and building control
Wireless voice
FUNCTIONAL BLOCK DIAGRAM
Tx/Rx
CONTROL
AGC
CONTROL
FSK/ASK
DEMODULATOR
DATA
SYNCHRONIZER
RSSI
7-BIT ADC
GAIN
DIV R
SERIAL
PORT
RFOUT
OFFSET
CORRECTION
OFFSET
CORRECTION
LNA
VCO
PFD
CP
AFC
CONTROL
OSC1
OSC2
DIVIDERS/
MUXING
N/N+1
DIV P
MUX
TEMP
SENSOR
RING
OSC
CLK
DIV
CLKOUT
TEST MUX
VCOIN CPOUT
POLARIZATION
LDO(1:4)
MUXOUT
ADCIN
RSET
CREG(1:4)
R
LNA
R
FIN
R
FINB
SLE
SDATA
CE
DATA CLK
SREAD
SCLK
INT/LOCK
DATA I/O
FSK MOD
CONTROL
GAUSSIAN
FILTER
-
MODULATOR
01975-001
IF FILTER
Figure 1.
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ADF7020-1
Preliminary Technical Data
Rev. PrE | Page 2 of 44
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications..................................................................................... 4
Timing Characteristics..................................................................... 7
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 12
Frequency Synthesizer ................................................................... 14
Reference Input........................................................................... 14
Choosing Channels for Best System Performance................. 16
Transmitter ...................................................................................... 17
RF Output Stage.......................................................................... 17
Modulation Schemes.................................................................. 17
Receiver Section.............................................................................. 19
RF Front End............................................................................... 19
RSSI/AGC.................................................................................... 20
FSK Demodulators on the ADF7020-1 ................................... 20
FSK Correlator/Demodulator................................................... 20
Linear FSK Demodulator .......................................................... 22
AFC Section ................................................................................ 22
Automatic Sync Word Recognition ......................................... 23
Applications..................................................................................... 24
LNA/PA Matching...................................................................... 24
Transmit Protocol and Coding Considerations ..................... 25
Device Programming after Initial Power-Up ......................... 25
Interfacing to Microcontroller/DSP ........................................ 25
Serial Interface ................................................................................ 28
Readback Format........................................................................ 28
Register 0--N Register............................................................... 29
Register 1--Oscillator/Filter Register...................................... 30
Register 2--Transmit Modulation Register (ASK/OOK
Mode)........................................................................................... 31
Register 2--Transmit Modulation Register (FSK Mode) ..... 32
Register 2--Transmit Modulation Register (GFSK/GOOK
Mode)........................................................................................... 33
Register 3--Receiver Clock Register ....................................... 34
Register 4--Demodulator Set-up Register.............................. 35
Register 5--Sync Byte Register................................................. 36
Register 6--Correlator/Demodulator Register ...................... 37
Register 7--Readback Set-up Register .................................... 38
Register 8--Power-Down Test Register .................................. 39
Register 9--AGC Register......................................................... 40
Register 10--AGC 2 Register.................................................... 41
Register 11--AFC Register ....................................................... 41
Register 12--Test Register......................................................... 42
Register 13--Offset Removal and Signal Gain Register ....... 43
Outline Dimensions ....................................................................... 44
Ordering Guide .......................................................................... 44
REVISION HISTORY
9/05--PrE: Initial Version
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Preliminary Technical Data
ADF7020-1
Rev. PrE | Page 3 of 44
GENERAL DESCRIPTION
The ADF7020-1 is a low power, highly integrated FSK/GFSK/
ASK/OOK/GOOK transceiver designed for operation in the
low UHF and VHF bands. The ADF7020-1 uses an external
VCO inductor which allows you to set the operating frequency
anywhere between 135MHz and 650MHz. Typical range of the
VCO is about 10% of the operating frequency. A complete
transceiver can be built using a small number of external
discrete components, making the ADF7020-1 very suitable for
price-sensitive and area-sensitive applications.
The transmit section contains a VCO and low noise
fractional-N PLL with output resolution of <1 ppm. This
frequency agile PLL allows the ADF7020-1 to be used in
frequency hopping spread spectrum (FHSS) systems. The VCO
operates at twice the fundamental frequency to reduce spurious
emissions and frequency pulling problems.
The transmitter output power is programmable in 0.3 dB steps
from -16 dBm to +13 dBm. The transceiver RF frequency,
channel spacing, and modulation are programmable using a
simple 3-wire interface. The device operates with a power
supply range of 2.3 V to 3.6 V and can be powered down when
not in use.
A low IF architecture is used in the receiver (200 kHz),
minimizing power consumption and the external component
count and avoiding interference problems at low frequencies.
The ADF7020-1 supports a wide variety of programmable
features including Rx linearity, sensitivity, and IF bandwidth,
allowing the user to trade off receiver sensitivity and selectivity
against current consumption, depending on the application.
The receiver also features a patent-pending automatic frequency
control (AFC) loop, allowing the PLL to track out the frequency
error in the incoming signal.
An on-chip ADC provides readback of an integrated tempera-
ture sensor, an external analog input, the battery voltage, or the
RSSI signal, which provides savings on an ADC in some
applications. The temperature sensor is accurate to ±10°C over
the full operating temperature range of -40°C to +85°C. This
accuracy can be improved by doing a 1-point calibration at
room temperature and storing the result in memory.
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ADF7020-1
Preliminary Technical Data
Rev. PrE | Page 4 of 44
SPECIFICATIONS
V
DD
= 2.3 V to 3.6 V, GND = 0 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical specifications are at V
DD
= 3 V, T
A
= 25°C.
All measurements are performed using the EVAL-ADF7020-1-DBX using PN9 data sequence, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions
RF CHARACTERISTICS
Frequency Ranges (Direct Output)
300
650
MHz
VCO adjust = 0, VCO bias = 6
Frequency Ranges (Divide-by-2 Mode)
135
325
MHz
See conditions for Direct Output.
Phase Frequency Detector Frequency
RF/256
20.96
MHz
PFD must be less than Direct Output
Frequency/31
TRANSMISSION
PARAMETERS
Data
Rate
FSK/GFSK
0.15
200
kbps
OOK/ASK
0.15
64
1
kbps
OOK/ASK
0.3
100
kbaud
Using Manchester encoding
Frequency Shift Keying
GFSK/FSK Frequency Deviation
2, 3
1
110
kHz
PFD = 3.625 MHz
4.88
620
kHz
PFD = 20 MHz
Deviation Frequency Resolution
100
Hz
PFD = 3.625 MHz
Gaussian Filter BT
0.5
Amplitude
Shift
Keying
ASK Modulation Depth
30
dB
OOK­PA Off Feedthrough
-50
dBm
Transmit Power
4
-20
+13 dBm
V
DD
= 3.0 V, T
A
= 25°C
Transmit Power Variation vs. Temp.
±1
dB
From -40°C to +85°C
Transmit Power Variation vs. VDD
±1
dB
From 2.3 V to 3.6 V at 315 MHz, T
A
= 25°C
Transmit Power Flatness
TBD
dB
Programmable Step Size
-20 dBm to +13 dBm
0.3125
dB
Integer Boundary
-55
dBc
50 kHz loop BW
Reference
-65
dBc
Harmonics
Second Harmonic
-27
dBc
Unfiltered conductive
Third Harmonic
-21
dBc
All Other Harmonics
-35
dBc
VCO Frequency Pulling, OOK Mode
30
kHz rms
DR = 9.6 kbps
Optimum PA Load Impedance
5
TBD
FRF = 135 MHz
TBD
FRF = 315 MHz
TBD
FRF = 615 MHz
RECEIVER PARAMETERS
FSK/GFSK Input Sensitivity
At BER = 1E - 3, FRF = 315 MHz,
LNA and PA matched separately
6
Sensitivity at 1 kbps
-119.2
dBm
FDEV= 5 kHz, high sensitivity mode
7
Sensitivity at 9.6 kbps
-112.8
dBm
FDEV = 10 kHz, high sensitivity mode
Sensitivity at 200 kbps
-100
dBm
FDEV = 50 kHz, high sensitivity mode
OOK Input Sensitivity
At BER = 1E - 3, FRF = 315 MHz
Sensitivity at 1 kbps
-116
dBm
High sensitivity mode
Sensitivity at 9.6 kbps
-106.5
dBm
High sensitivity mode
LNA and Mixer, Input IP3
7
Enhanced Linearity Mode
6.8
dBm
Pin = -20 dBm, 2 CW interferers
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Preliminary Technical Data
ADF7020-1
Rev. PrE | Page 5 of 44
Parameter
Min
Typ
Max
Unit
Test Conditions
Low Current Mode
-3.2
dBm
FRF = 315 MHz, F1 = FRF + 3 MHz
High Sensitivity Mode
-35
dBm
F2 = FRF + 6 MHz, maximum gain
Rx Spurious Emissions
8
-57
dBm
<1 GHz at antenna input
-47
dBm
>1 GHz at antenna input
AFC
Pull-In Range
±50
kHz
IF_BW = 200 kHz
Response Time
48
Bits
Mod index = 0.875
Accuracy
1
kHz
CHANNEL
FILTERING
Adjacent Channel Rejection
(Offset = ±1 × IF Filter BW Setting)
27
dB
Second Adjacent Channel Rejection
(Offset = ±2 × IF Filter BW Setting)
50
dB
Third Adjacent Channel Rejection
(Offset = ±3 × IF Filter BW Setting)
55
dB
IF filter BW settings = 100 kHz, 150 kHz,
200 kHz
Desired signal 3 dB above the input sensitivity
level, CW interferer power level increased until
BER = 10
-3
, image channel excluded
Image Channel Rejection
35
dB
Image at FRF-400 kHz
CO-CHANNEL
REJECTION
-2
dB
Wideband Interference Rejection
70
dB
Swept from 100 MHz to 2 GHz, measured as
channel rejection
BLOCKING
±1 MHz
60
dB
Desired signal 3 dB above the input sensitivity
level, CW interferer power level increased until
BER = 10
-2
±5 MHz
68
dB
±10 MHz
65
dB
±10 MHz (High Linearity Mode)
72
dB
Saturation (Maximum Input Level)
12
dBm
FSK mode, BER = 10
-3
LNA Input Impedance
TBD
FRF = 135 MHz, RFIN to GND
TBD
FRF = 315 MHz
TBD
FRF = 615 MHz
RSSI
Range at Input
-100 to
-36
dBm
Linearity
±2
dB
Absolute Accuracy
±3
dB
Response Time
150
s
See the RSSI/AGC section
PHASE-LOCKED
LOOP
VCO Gain
TBD
MHz/V
315 MHz band,
VCO adjust = 0, VCO_BIAS_SETTING = 6
TBD
MHz/V
135 MHz, VCO adjust = 0
TBD
MHz/V
433 MHz, VCO adjust = 0
Phase Noise (In-Band)
-89
dBc/Hz
PA = 0 dBm, V
DD
= 3.0 V, PFD = 10 MHz, FRF =
315 MHz, VCO_BIAS_SETTING = 8
Phase Noise (Out-of-Band)
-110
dBc/Hz
1 MHz offset
Residual FM
128
Hz
From 200 Hz to 20 kHz, FRF = 315 MHz
PLL Settling
40
s
Measured for a 10 MHz frequency step to within
5 ppm accuracy,
PFD = 20 MHz, LBW = 50 kHz

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