ADF4108 PLL Frequency Synthesizer Data Sheet (Rev. 0)
PLL Frequency Synthesizer
ADF4108
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
FEATURES
8.0 GHz bandwidth
3.2 V to 3.6 V power supply
Separate charge pump supply (V
P
) allows extended tuning
voltage in 3.3 V systems
Programmable, dual modulus prescaler 8/9, 16/17, 32/33, or
64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
Loop filter design possible with ADIsimPLL
APPLICATIONS
Broadband wireless access
Satellite systems
Instrumentation
Wireless LANs
Base stations for wireless radio
GENERAL DESCRIPTION
The ADF4108 frequency synthesizer can be used to implement
local oscillators in the up-conversion and down-conversion
sections of wireless receivers and transmitters. It consists of a
low noise digital PFD (phase frequency detector), a precision
charge pump, a programmable reference divider, programmable
A and B counters, and a dual-modulus prescaler (P/P + 1). The
A (6-bit) and B (13-bit) counters, in conjunction with the dual-
modulus prescaler (P/P + 1), implement an N divider (N =
BP + A). In addition, the 14-bit reference counter (R counter),
allows selectable REFIN frequencies at the PFD input. A
complete phase-locked loop (PLL) can be implemented if the
synthesizer is used with an external loop filter and voltage
controlled oscillator (VCO). Its very high bandwidth means
that frequency doublers can be eliminated in many high
frequency systems, simplifying system architecture and
reducing cost.
FUNCTIONAL BLOCK DIAGRAM
CLK
DATA
LE
REF
IN
RF
IN
A
RF
IN
B
24-BIT INPUT
REGISTER
SD
OUT
AV
DD
DV
DD
CE
AGND DGND
14-BIT
R COUNTER
R COUNTER
LATCH
22
14
FUNCTION
LATCH
A, B COUNTER
LATCH
FROM
FUNCTION
LATCH
PRESCALER
P/P + 1
N = BP + A
LOAD
LOAD
13-BIT
B COUNTER
6-BIT
A COUNTER
6
19
13
M3 M2 M1
MUX
SD
OUT
AV
DD
HIGH Z
MUXOUT
CPGND
R
SET
V
P
CP
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
REFERENCE
CHARGE
PUMP
CURRENT
SETTING 1
ADF4108
CPI3 CPI2 CPI1
CPI6 CPI5 CPI4
CURRENT
SETTING 2
06
01
5-
0
01
Figure 1.
ADF4108
Rev. 0 | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics..................................................................... 5
Absolute Maximum Rating ............................................................. 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ........................................................................ 9
Reference Input Stage................................................................... 9
RF Input Stage............................................................................... 9
Prescaler (P/P + 1)........................................................................ 9
A and B Counters ......................................................................... 9
R Counter ...................................................................................... 9
Phase Frequency Detector and Charge Pump...........................9
MUXOUT and Lock Detect...................................................... 10
Input Shift Register .................................................................... 10
Latch Summary........................................................................... 11
Reference Counter Latch Map.................................................. 12
AB Counter Latch Map ............................................................. 13
Function Latch Map................................................................... 14
Initialization Latch Map ............................................................ 15
Function Latch............................................................................ 16
Initialization Latch ..................................................................... 17
Power Supply Considerations................................................... 17
Interfacing ....................................................................................... 18
ADuC812 Interface .................................................................... 18
ADSP-2181 Interface ................................................................. 18
PCB Design Guidelines for Chip Scale Package......................... 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
4/06--Revision 0: Initial Version
ADF4108
Rev. 0 | Page 3 of 20
SPECIFICATIONS
AV
DD
= DV
DD
= 3.3 V ± 2%, AV
DD
V
P
5.5 V, AGND = DGND = CPGND = 0 V, R
SET
= 5.1 k, dBm referred to 50 , T
A
= T
MIN
to
T
MAX
, unless otherwise noted.
Table 1.
Parameter B
Version
1
B Chips
2
(Typ)
Unit Test
Conditions/Comments
RF CHARACTERISTICS
See Figure 12 for input circuit
RF Input Frequency (RF
IN
)
1.0/8.0
1.0/8.0
GHz min/max
For lower frequencies ensure slew rate (SR) > 320 V/s
RF Input Sensitivity
-5/+5
-5/+5
dBm min/max
Maximum Allowable Prescaler
Output Frequency
3
300
325
300
325
MHz max
MHz max
P = 8
P = 16
REF
IN
CHARACTERISTICS
REF
IN
Input Frequency
20/250
20/250
MHz min/max
For f < 20 MHz, ensure SR > 50 V/s
REF
IN
Input Sensitivity
4
0.8/V
DD
0.8/V
DD
V p-p min/max
Biased at AV
DD
/2
5
REF
IN
Input Capacitance
10
10
pF max
REF
IN
Input Current
±100
±100
A max
PHASE DETECTOR
Phase Detector Frequency
6
104 104
MHz
max
CHARGE PUMP
Programmable; see Figure 19
I
CP
Sink/Source
High Value
5
5
mA typ
With R
SET
= 5.1 k
Low Value
625
625
A typ
Absolute Accuracy
2.5
2.5
% typ
With R
SET
= 5.1 k
R
SET
Range
3.0/11
3.0/11
k typ
See Figure 19
I
CP
Three-State Leakage
1
1
nA typ
1 nA typical; T
A
= 25°C
Sink and Source Current
Matching
2
2
% typ
0.5 V V
CP
V
P
0.5 V
I
CP
vs. V
CP
1.5
1.5
% typ
0.5 V V
CP
V
P
0.5 V
I
CP
vs. Temperature
2
2
% typ
V
CP
= V
P
/2
LOGIC INPUTS
V
IH
, Input High Voltage
1.4
1.4
V min
V
IL
, Input Low Voltage
0.6
0.6
V max
I
INH
, I
INL
, Input Current
±1
±1
A max
C
IN
, Input Capacitance
10
10
pF max
LOGIC OUTPUTS
V
OH
, Output High Voltage
1.4
1.4
V min
Open-drain output chosen; 1 k pull-up resistor to 1.8 V
V
OH
, Output High Voltage
V
DD
- 0.4
V
DD
- 0.4
V min
CMOS output chosen
I
OH
100
100
A
max
V
OL
, Output Low Voltage
0.4
0.4
V max
I
OL
= 500 A
POWER SUPPLIES
AV
DD
3.2/3.6
3.2/3.6
V min/V max
DV
DD
AV
DD
AV
DD
V
P
AV
DD
/5.5 AV
DD
/5.5
V min/V max
AV
DD
V
P
5.5 V
I
DD
(AI
DD
+ DI
DD
)
7
17
17
mA max
15 mA typ
I
P
0.4
0.4
mA
max
T
A
= 25°C
Power-Down Mode (AI
DD
+ DI
DD
)
8
10 10
A
typ
ADF4108
Rev. 0 | Page 4 of 20
Parameter B
Version
1
B Chips
2
(Typ) Unit
Test
Conditions/Comments
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
9
-219 -219
dBc/Hz
typ
Phase Noise Performance
10
@
VCO
output
7900 MHz Output
11
-81
-81
dBc/Hz typ
@ 1 kHz offset and 1 MHz PFD frequency
Spurious Signals
7900 MHz Output
11
61
61
dBc typ
@ 1 MHz offset and 1 MHz PFD frequency
1
Operating temperature range (B version) is 40°C to +85°C.
2
The B chip specifications are given as typical values.
3
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
4
AV
DD
= DV
DD
= 3.3 V.
5
AC coupling ensures AV
DD
/2 bias.
6
Guaranteed by design. Sample tested to ensure compliance.
7
T
A
= 25°C; AV
DD
= DV
DD
= 3.3 V; P = 32; RF
IN
= 8 GHz, f
PFD
= 200 kHz, REF
IN
= 10 MHz.
8
T
A
= 25°C; AV
DD
= DV
DD
= 3.3 V; R = 16,383; A = 63; B = 891; P = 32; RF
IN
= 7.0 GHz.
9
This value can be used to calculate phase noise for any application. Use the formula 219 + 10 log(f
PFD
) + 20 logN to calculate in-band phase noise performance as seen
at the VCO output. The value given is the lowest noise mode.
10
The phase noise is measured with the EVAL-ADF4108EB1 evaluation board, with the Hittite HMC506LP4 VCO. The spectrum analyzer provides the REFIN for the
synthesizer (f
REFOUT
= 10 MHz @ 0 dBm).
11
f
REFIN
= 10 MHz; f
PFD
= 1 MHz; f
RF
= 7900 MHz; N = 7900; loop B/W = 50 kHz, VCO = HMC506LP4, spurs are dominated by the leakage current on the tuning port of the
HMC506LP4 VCO.
ADF4108
Rev. 0 | Page 5 of 20
TIMING CHARACTERISTICS
AV
DD
= DV
DD
= 3.3 V ± 2%, AV
DD
V
P
5.5 V, AGND = DGND = CPGND = 0 V, R
SET
= 5.1 k, dBm referred to 50 , T
A
= T
MIN
to
T
MAX
, unless otherwise noted.
Table 2.
Parameter
1
Limit
2
(B Version)
Unit
Test Conditions/Comments
t
1
10
ns min
DATA to CLOCK setup time
t
2
10
ns min
DATA to CLOCK hold time
t
3
25
ns min
CLOCK high duration
t
4
25
ns min
CLOCK low duration
t
5
10
ns min
CLOCK to LE setup time
t
6
20
ns min
LE pulse width
1
Guaranteed by design but not production tested.
2
Operating temperature range (B Version) is 40°C to +85°C.
CLOCK
DB22
DB2
DATA
LE
t
1
LE
DB23 (MSB)
t
2
DB1 (CONTROL
BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
6
t
5
t
3
t
4
06
01
5-
0
02
Figure 2. Timing Diagram
ADF4108
Rev. 0 | Page 6 of 20
ABSOLUTE MAXIMUM RATING
T
A
= 25°C, unless otherwise noted.
Table 3.
Parameter Rating
AV
DD
to GND
1
0.3 V to +3.9 V
AV
DD
to DV
DD
0.3 V to +0.3 V
V
P
to GND
0.3 V to +5.8 V
V
P
to AV
DD
0.3 V to +5.8 V
Digital I/O Voltage to GND
0.3 V to V
DD
+ 0.3 V
Analog I/O Voltage to GND
0.3 V to V
P
+ 0.3 V
REFIN, RF
IN
A, RF
IN
B to GND
0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (B Version)
40°C to +85°C
Storage Temperature Range
65°C to +125°C
Maximum Junction Temperature
150°C
TSSOP
JA
Thermal Impedance
112°C/W
CSP
JA
Thermal Impedance
(Paddle Soldered)
30.4°C/W
Reflow Soldering
Peak Temperature (60 sec)
260
Time at Peak Temperature
40 sec
Transistor Count
CMOS 6425
Bipolar 303
1
GND = AGND = DGND = 0 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADF4108
Rev. 0 | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
06
01
5-
0
30
R
SET
CP
CPGND
AGND
1
2
3
4
5
6
7
8
RF
IN
B
RF
IN
A
AV
DD
REF
IN
MUXOUT
LE
DATA
CLK
CE
DGND
16
15
14
13
12
11
10
9
V
P
DV
DD
TOP VIEW
(Not to Scale)
ADF4108
NOTE: TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).
15 MUXOUT
14 LE
13 DATA
12 CLK
CPGND 1
AGND 2
AGND 3
20 CP
11 CE
6
7
8
DG
ND 9
DG
ND 10
19
18
17
16
RF
IN
B 4
RF
IN
A 5
R
SET
V
P
DV
DD
DV
DD
PIN 1
INDICATOR
TOP VIEW
(Not to Scale)
ADF4108
AV
DD
AV
DD
RE
F
IN
0
60
15
-
00
3
Figure 3. TSSOP Pin Configuration for TSSOP
Figure 4. LFCSP_VQ Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
TSSOP LFCSP_VQ Mnemonic Description
1 19
R
SET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the R
SET
pin is 0.66 V. The relationship between I
CP
and R
SET
is
SET
MAX
CP
R
I
5
.
25
=
with R
SET
= 5.1 k, I
CP MAX
= 5 mA.
2 20
CP
Charge Pump Output. When enabled, this pin provides ±I
CP
to the external loop filter, which in turn
drives the external VCO.
3
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
4
2, 3
AGND
Analog Ground. This is the ground return path of the prescaler.
5 4
RF
IN
B
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a
small bypass capacitor, typically 100 pF. See Figure 12.
6 5
RF
IN
A
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
7 6,
7 AV
DD
Analog Power Supply. This voltage may range from 3.2 V to 3.6 V. Decoupling capacitors to the
analog ground plane should be placed as close as possible to this pin. AV
DD
must be the same value
as DV
DD
.
8 8
REF
IN
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and a dc equivalent input
resistance of 100 k. See Figure 11. This input can be driven from a TTL or CMOS crystal oscillator or
it can be ac-coupled.
9
9, 10
DGND
Digital Ground.
10 11
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into
three-state mode. Taking the pin high will power up the device, depending on the status of the
power-down bit, F2.
11 12
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS
input.
12 13
DATA Serial Data Input. The serial data is loaded MSB first with the 2 LSBs being the control bits. This input
is a high impedance CMOS input.
13 14
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into
one of the four latches, the latch being selected using the control bits.
14 15
MUXOUT
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
15 16,
17 DV
DD
Digital Power Supply. This may range from 3.2 V to 3.6 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DV
DD
must be the same value as AV
DD
.
16 18
V
P
Charge Pump Power Supply. This voltage should be greater than or equal to V
DD
. In systems where
V
DD
is 3.3 V, it can be set to 5 V and used to drive a VCO with a tuning range of up to 5 V.
ADF4108
Rev. 0 | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
0.50000
0.60000
0.70000
0.80000
0.90000
1.00000
1.10000
1.20000
1.30000
1.40000
1.50000
1.60000
1.70000
1.80000
1.90000
2.00000
2.10000
2.20000
2.30000
2.40000
2.50000
2.60000
2.70000
2.80000
2.90000
3.00000
3.10000
3.20000
3.30000
3.40000
3.50000
3.60000
3.70000
3.80000
3.90000
4.00000
4.10000
4.20000
17.2820
20.6919
24.5386
27.3228
31.0698
34.8623
38.5574
41.9093
45.6990
49.4185
52.8898
56.2923
60.2584
63.1446
65.6464
68.0742
71.3530
75.5658
79.6404
82.8246
85.2795
85.6298
86.1854
86.4997
88.8080
91.9737
95.4087
99.1282
102.748
107.167
111.883
117.548
123.856
130.399
136.744
142.766
149.269
154.884
0.89148
0.88133
0.87152
0.85855
0.84911
0.83512
0.82374
0.80871
0.79176
0.77205
0.75696
0.74234
0.72239
0.69419
0.67288
0.66227
0.64758
0.62454
0.59466
0.55932
0.52256
0.48754
0.46411
0.45776
0.44859
0.44588
0.43810
0.43269
0.42777
0.42859
0.43365
0.43849
0.44475
0.44800
0.45223
0.45555
0.45313
0.45622
4.30000
4.40000
4.50000
4.60000
4.70000
4.80000
4.90000
5.00000
5.10000
5.20000
5.30000
5.40000
5.50000
5.60000
5.70000
5.80000
5.90000
6.00000
6.10000
6.20000
6.30000
6.40000
6.50000
6.60000
6.70000
6.80000
6.90000
7.00000
7.10000
7.20000
7.30000
7.40000
7.50000
7.60000
7.70000
7.80000
7.90000
8.00000
0.45555
0.46108
0.45325
0.45054
0.45200
0.45043
0.45282
0.44287
0.44909
0.44294
0.44558
0.45417
0.46038
0.47128
0.47439
0.48604
0.50637
0.52172
0.53342
0.53716
0.55804
0.56362
0.58268
0.59248
0.61066
0.61830
0.61633
0.61673
0.60597
0.58376
0.57673
0.58157
0.60040
0.61332
0.62927
0.63938
0.65320
0.65804
159.680
164.916
168.452
173.462
176.697
178.824
174.947
170.237
166.617
162.786
158.766
153.195
147.721
139.760
132.657
125.782
121.110
115.400
107.705
101.572
97.5379
93.0936
89.2227
86.3300
83.0956
80.8843
78.0872
75.3727
73.9456
73.5883
74.1975
76.2136
77.1545
76.1122
74.8359
74.0546
72.0061
69.9926
Freq
MAGS11
ANGS11
FREQ UNIT:
GHz
KEYWORD: R
PARAM TYPE:
s
DATA FORMAT: MA
Freq
MAGS11
ANGS11
06
01
5-
0
04
Figure 5. S Parameter Data for the RF Input
0
35
30
25
20
15
10
5
1
9
8
7
6
5
4
3
2
RF
I
N
P
UT
P
O
W
E
R (
d
B
m
)
RF INPUT FREQUENCY (GHz)
V
DD
= 3.3V
T
A
= +85°C
T
A
= +25°C
T
A
= 40°C
06
01
5-
00
5
Figure 6. RF Input Sensitivity
50
150
140
130
120
110
100
90
80
70
60
1kHz
10MHz
FREQUENCY OFFSET
PH
A
S
E N
O
I
SE (
d
B
c
/
H
z
)
V
DD
= 3.3V, V
P
= 5V
I
CP
= 5mA
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 50kHz
PHASE NOISE = 82dBc/Hz @ 1kHz
HMC506LP4 VCO
06
01
5-
0
10
Figure 7. Phase Noise at 7.9 GHz Phase Noise
0
120
100
80
60
40
20
2MHz
1MHz
7900MHz
1MHz
2MHz
FREQUENCY
O
UT
P
UT
P
O
W
E
R (
d
B)
06
01
5-
01
1
61dBc
V
DD
= 3.3V, V
P
= 5V
I
CP
= 5mA
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 50kHz
RES BANDWIDTH = 3kHz
VIDEO BANDWIDTH = 3kHz
AVERAGES = 1
OUTPUT POWER = 0.3dBm
HMC506LP4 VCO
0.3dBm
Figure 8. Reference Spurs at 7.9 GHz
Note: The spurs are dominated by the leakage current of the tuning port on
the HMC506LP4 VCO. The leakage current was measured to be 27 nA.
6
6
5
4
3
2
1
0
1
2
3
4
5
5.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
V
CP
(V)
I
CP
(m
A
)
V
PP
= 5V
I
CP
SETTLING = 5mA
06
01
5-
0
15
Figure 9. Charge Pump Output Characteristics
120
180
170
160
150
140
130
100M
10k
100k
1M
10M
PHASE FREQUENCY DETECTOR (Hz)
P
HAS
E
NO
I
S
E
(
d
B
c
/
Hz
)
V
DD
= 3V
V
P
= 5V
06
01
5-
01
4
Figure 10. Phase Noise (Referred to CP Output) vs. PFD Frequency
ADF4108
Rev. 0 | Page 9 of 20
THEORY OF OPERATION
REFERENCE INPUT STAGE
The reference input stage is shown in Figure 11. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
IN
pin
on power-down.
100k
NC
REF
IN
NC
NO
SW1
SW2
BUFFER
SW3
TO R COUNTER
POWER-DOWN
CONTROL
0
60
15
-
01
6
Figure 11. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 12. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
500
1.6V
500
AGND
RF
IN
A
RF
IN
B
AV
DD
BIAS
GENERATOR
0
60
15
-
01
7
Figure 12. RF Input Stage
PRESCALER (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the A and B
counters, enables the large division ratio, N, to be realized (N =
BP + A). The dual-modulus prescaler, operating at CML levels,
takes the clock from the RF input stage and divides it down to a
manageable frequency for the CMOS A and B counters. The
prescaler is programmable. It can be set in software to 8/9,
16/17, 32/33, or 64/65. It is based on a synchronous 4/5 core. A
minimum divide ratio is possible for contiguous output
frequencies. This minimum is determined by P, the prescaler
value, and is given by: (P
2
P).
A AND B COUNTERS
The A and B CMOS counters combine with the dual-modulus
prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The counters are specified to work when the
prescaler output is 300 MHz or less. Thus, with an RF input
frequency of 4.0 GHz, a prescaler value of 16/17 is valid but a
value of 8/9 is not valid.
Pulse Swallow Function
The A and B counters, in conjunction with the dual-modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the reference frequency divided by R. The
equation for the VCO frequency is as follows:
(
)
[
]
R
f
A
B
P
f
REFIN
VCO
×
+
×
=
where:
f
VCO
is the output frequency of external voltage controlled
oscillator (VCO).
P is the preset modulus of dual-modulus prescaler (8/9, 16/17,
and so on.).
B is the preset divide ratio of binary 13-bit counter (3 to 8191).
A is the preset divide ratio of binary 6-bit swallow counter (0 to
63).
f
REFIN
is the external reference frequency oscillator.
LOAD
LOAD
FROM RF
INPUT STAGE
PRESCALER
P/P + 1
13-BIT B
COUNTER
TO PFD
6-BIT A
COUNTER
N DIVIDER
MODULUS
CONTROL
N = BP + A
06
015
-
01
8
Figure 13. A and B Counters
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
PHASE FREQUENCY DETECTOR AND CHARGE
PUMP
The phase frequency detector (PFD) takes inputs from the R
counter and N counter (N = BP + A) and produces an output
proportional to the phase and frequency difference between
them. Figure 14 is a simplified schematic. The PFD includes a
programmable delay element that controls the width of the
antibacklash pulse. This pulse ensures that there is no dead zone
in the PFD transfer function and minimizes phase noise and
reference spurs. Two bits in the reference counter latch, ABP2
and ABP1, control the width of the pulse. (See Figure 17.)
ADF4108
Rev. 0 | Page 10 of 20
HI
HI
D1
D2
Q1
Q2
CLR2
CP
U1
U2
UP
DOWN
ABP2
ABP1
CPGND
U3
R DIVIDER
PROGRAMMABLE
DELAY
N DIVIDER
V
P
CHARGE
PUMP
CLR1
0
601
5-
0
19
Figure 14. PFD Simplified Schematic and Timing (in Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4108 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. Figure 19 shows the full truth table. Figure 15 shows the
MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Digital lock detect is active high. When the lock detect
precision (LDP) bit in the R counter latch is set to 0, digital lock
detect is set high when the phase error on three consecutive
phase detector (PD) cycles is less than 15 ns. With LDP set to 1,
five consecutive cycles of less than 15 ns are required to set the
lock detect. It will stay set high until a phase error of greater
than 25 ns is detected on any subsequent PD cycle.
The N-channel open-drain analog lock detect should be
operated with an external pull-up resistor of 10 k nominal.
When lock has been detected, this output will be high with
narrow, low-going pulses.
DGND
DV
DD
CONTROL
MUX
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
MUXOUT
0
6015-
020
Figure 15. MUXOUT Circuit
INPUT SHIFT REGISTER
The ADF4108 digital section includes a 24-bit input shift
register, a 14-bit R counter, and a 19-bit N counter, comprising a
6-bit A counter and a 13-bit B counter. Data is clocked into the
24-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the 2 LSBs, DB1 and DB0, as
shown in the timing diagram of Figure 2. The truth table for
these bits is shown in Table 5.
Figure 16 shows a summary of how the latches are
programmed.
Table 5. C2 and C1 Truth Table
Control Bits
C2 C1 Data Latch
0 0 R
counter
0
1
N counter (A and B)
1
0
Function latch (Including prescaler)
1 1 Initialization
latch
ADF4108
Rev. 0 | Page 11 of 20
LATCH SUMMARY
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0) C1 (0)
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
ABP1
ABP2
T1
T2
LDP
DB21
DB22
DB23
0
0
X
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0) C1 (1)
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
A6
DB21
DB22
DB23
G1
X
X
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (1) C1 (0)
F1
PD1
M1
M2
M3
F3
P1
P2
CPI1
CPI2
CPI5
CPI6
TC4
PD2
F2
CPI3
CPI4
DB21
TC3
TC2
TC1
DB22
DB23
F4
F5
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (1) C1 (1)
F1
PD1
M1
M2
M3
F3
P1
P2
CPI1
CPI2
CPI5
CPI6
TC4
PD2
F2
CPI3
CPI4
DB21
TC3
TC2
TC1
DB22
DB23
F4
F5
REFERENCE COUNTER LATCH
RESERVED
LOC
K
DE
T
E
CT
PR
EC
I
S
I
O
N
TEST
MODE BITS
ANTI-
BACKLASH
WIDTH
14-BIT REFERENCE COUNTER
CONTROL
BITS
RESERVED
13-BIT B COUNTER
6-BIT A COUNTER
CONTROL
BITS
N COUNTER LATCH
CP
G
AI
N
FUNCTION LATCH
PRESCALER
VALUE
PO
W
E
R
-
DO
W
N 2
CURRENT
SETTING
2
CURRENT
SETTING
1
TIMER COUNTER
CONTROL
FA
S
TL
O
C
K
MO
D
E
FA
S
TL
O
C
K
E
NAB
L
E
CP
T
HRE
E
-
ST
A
T
E
PD
PO
L
A
R
I
T
Y
MUXOUT
CONTROL
PO
W
E
R
-
DO
W
N
1
CO
UNT
E
R
R
E
SET
CONTROL
BITS
PRESCALER
VALUE
PO
W
E
R
-
DO
W
N 2
CURRENT
SETTING
2
CURRENT
SETTING
1
TIMER COUNTER
CONTROL
FA
S
TL
O
C
K
MO
D
E
FA
S
TL
O
C
K
E
NABL
E
C
P T
H
R
EE-
ST
A
T
E
PD
PO
L
A
R
I
T
Y
MUXOUT
CONTROL
PO
W
E
R
-
DO
W
N
1
CO
UNT
E
R
R
E
SET
CONTROL
BITS
INITIALIZATION LATCH
06
01
5-
0
21
Figure 16. Latch Summary
ADF4108
Rev. 0 | Page 12 of 20
REFERENCE COUNTER LATCH MAP
LDP
0
1
ABP2
ABP1
0
0
2.9ns
0
1
1.3ns
1
0
6.0ns
1
1
2.9ns
R14
R13
R12
..........
R3
R2
R1
0
0
0
..........
0
0
1
1
0
0
0
..........
0
1
0
2
0
0
0
..........
0
1
1
3
0
0
0
..........
1
0
0
4
.
.
.
..........
.
.
.
.
.
.
.
..........
.
.
.
.
.
.
.
..........
.
.
.
.
1
1
1
..........
1
0
0
16380
1
1
1
..........
1
0
1
16381
1
1
1
..........
1
1
0
16382
1
1
1
..........
1
1
1
16383
X
= DON'T CARE
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0) C1 (0)
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
ABP1
ABP2
T1
T2
LDP
DB21
DB22
DB23
0
0
X
RESERVED
LOC
K
DE
T
E
CT
P
R
E
C
IS
ION
TEST
MODE BITS
ANTI-
BACKLASH
WIDTH
14-BIT REFERENCE COUNTER
CONTROL
BITS
DIVIDE RATIO
ANTIBACKLASH PULSE WIDTH
TEST MODE BITS
SHOULD BE SET
TO 00 FOR NORMAL
OPERATION.
OPERATION
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
BOTH OF THESE BITS
MUST BE SET TO 0 FOR
NORMAL OPERATION.
06
01
5-
0
22
Figure 17. Reference Counter Latch Map
ADF4108
Rev. 0 | Page 13 of 20
AB COUNTER LATCH MAP
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0) C1 (1)
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
A6
DB21
DB22
DB23
G1
0
0
0
1
1
0
F4 (FUNCTION LATCH)
FASTLOCK ENABLE
1
1
A6
A5
..........
A2
A1
0
0
..........
0
0
0
0
0
..........
0
1
1
0
0
..........
1
0
2
0
0
..........
1
1
3
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
60
1
1
..........
0
1
61
1
1
..........
1
0
62
1
1
..........
1
1
63
X
X
B13
B12
B11
B3
B2
B1
0
0
0
..........
0
0
0
0
0
0
..........
0
0
1
0
0
0
..........
0
1
0
0
0
0
..........
0
1
1
3
.
.
.
..........
.
.
.
.
.
.
.
..........
.
.
.
.
.
.
.
..........
.
.
.
.
1
1
1
..........
1
0
0
8188
1
1
1
..........
1
0
1
8189
1
1
1
..........
1
1
0
8190
1
1
1
..........
1
1
1
8191
X = DON'T CARE
RESERVED
13-BIT B COUNTER
6-BIT A COUNTER
CONTROL
BITS
C
P
G
A
IN
A COUNTER
DIVIDE RATIO
B COUNTER DIVIDE RATIO
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BITS.
OPERATION
G1
CP GAIN
CHARGE PUMP CURRENT
SETTING 1 IS PERMANENTLY USED.
CHARGE PUMP CURRENT
SETTING 2 IS PERMANENTLY USED.
CHARGE PUMP CURRENT
SETTING 1 IS USED.
CHARGE PUMP CURRENT IS
SWITCHED TO SETTING 2. THE
TIME SPENT IN SETTING 2 IS
DEPENDENT ON WHICH FASTLOCK
MODE IS USED. SEE FUNCTION
LATCH DESCRIPTION.
N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION
LATCH. B MUST BE GREATER THAN OR EQUAL TO A. FOR
CONTINUOUSLY ADJACENT VALUES OF (N × F
REF
), AT THE
OUTPUT, N
MIN
IS (P
2
P).
0
6
015-
023
Figure 18. AB Counter Latch Map
ADF4108
Rev. 0 | Page 14 of 20
FUNCTION LATCH MAP
P2
P1
0
0
8/9
0
1
16/17
1
0
32/33
1
1
64/65
PD2
PD1
MODE
0
X
X
1
X
0
1
0
1
1
1
1
CPI6
CPI5
CPI4
CPI3
CPI2
CPI1
3k
5.1k
11k
0
0
0
1.06
0.625
0.289
0
0
1
2.12
1.25
0.580
0
1
0
3.18
1.875
0.870
0
1
1
4.24
2.5
1.160
1
0
0
5.30
3.125
1.450
1
0
1
6.36
3.75
1.730
1
1
0
7.42
4.375
2.020
1
1
1
8.50
5.0
2.320
TC4
TC3
TC2
TC1
0
0
0
0
3
0
0
0
1
7
0
0
1
0
11
0
0
1
1
15
0
1
0
0
19
0
1
0
1
23
0
1
1
0
27
0
1
1
1
31
1
0
0
0
35
1
0
0
1
39
1
0
1
0
43
1
0
1
1
47
1
1
0
0
51
1
1
0
1
55
1
1
1
0
59
1
1
1
1
63
F4
0
1
1
M3
M2
M1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
F3
0
1
F2
0
1
F1
0
1
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (1) C1 (0)
F1
PD1
M1
M2
M3
F3
P1
P2
CPI1
CPI2
CPI5
CPI6
TC4
PD2
F2
CPI3
CPI4
DB21
TC3
TC2
TC1
DB22
DB23
F4
F5
F5
X
0
1
NEGATIVE
POSITIVE
PRESCALER
VALUE
PO
W
E
R-
DO
W
N
2
CURRENT
SETTING
2
CURRENT
SETTING
1
TIMER COUNTER
CONTROL
FA
S
T
LOC
K
MO
D
E
FA
S
T
LO
C
K
EN
A
B
L
E
CP T
HREE
-
ST
AT
E
MUXOUT
CONTROL
POW
E
R
-
DO
W
N
1
CO
U
N
T
E
R
RES
E
T
CONTROL
BITS
PHASE DETECTOR
POLARITY
COUNTER
OPERATION
NORMAL
R, A, B COUNTERS
HELD IN RESET
CHARGE PUMP
OUTPUT
NORMAL
THREE-STATE
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE 2
FASTLOCK MODE
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DV
DD
R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN
LOCK DETECT
SERIAL DATA OUTPUT
DGND
OUTPUT
TIMEOUT
(PFD CYCLES)
I
CP
(mA)
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
CE PIN
PRESCALER VALUE
PD
PO
L
ARI
T
Y
0
6015-
024
Figure 19. Function Latch Map
ADF4108
Rev. 0 | Page 15 of 20
INITIALIZATION LATCH MAP
P2
P1
0
0
8/9
0
1
16/17
1
0
32/33
1
1
64/65
PD2
PD1
MODE
0
X
X
1
X
0
1
0
1
1
1
1
CPI6
CPI5
CPI4
CPI3
CPI2
CPI1
3k
5.1k
11k
0
0
0
1.06
0.625
0.289
0
0
1
2.12
1.25
0.580
0
1
0
3.18
1.875
0.870
0
1
1
4.24
2.5
1.160
1
0
0
5.30
3.125
1.450
1
0
1
6.36
3.75
1.730
1
1
0
7.42
4.375
2.020
1
1
1
8.50
5.0
2.320
TC4
TC3
TC2
TC1
0
0
0
0
3
0
0
0
1
7
0
0
1
0
11
0
0
1
1
15
0
1
0
0
19
0
1
0
1
23
0
1
1
0
27
0
1
1
1
31
1
0
0
0
35
1
0
0
1
39
1
0
1
0
43
1
0
1
1
47
1
1
0
0
51
1
1
0
1
55
1
1
1
0
59
1
1
1
1
63
F4
0
1
1
M3
M2
M1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
F3
0
1
F2
0
1
F1
0
1
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (1) C1 (1)
F1
PD1
M1
M2
M3
F3
P1
P2
CPI1
CPI2
CPI5
CPI6
TC4
PD2
F2
CPI3
CPI4
DB21
TC3
TC2
TC1
DB22
DB23
F4
F5
THREE-STATE
F5
X
0
1
NEGATIVE
POSITIVE
PRESCALER
VALUE
PO
W
E
R-
DO
W
N
2
CURRENT
SETTING
2
CURRENT
SETTING
1
TIMER COUNTER
CONTROL
FA
S
T
LOC
K
MO
D
E
FA
S
T
LO
C
K
EN
A
B
L
E
CP T
H
REE
-
ST
AT
E
MUXOUT
CONTROL
POW
E
R
-
DO
W
N
1
C
O
UNT
ER
RES
E
T
CONTROL
BITS
PHASE DETECTOR
POLARITY
COUNTER
OPERATION
NORMAL
R, A, B COUNTERS
HELD IN RESET
CHARGE PUMP
OUTPUT
NORMAL
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE 2
FASTLOCK MODE
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DV
DD
R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN
LOCK DETECT
SERIAL DATA OUTPUT
DGND
OUTPUT
TIMEOUT
(PFD CYCLES)
I
CP
(mA)
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
CE PIN
PRESCALER VALUE
PD
PO
L
A
RI
T
Y
0
6015-
025
Figure 20. Initialization Latch Map
ADF4108
Rev. 0 | Page 16 of 20
FUNCTION LATCH
The on-chip function latch is programmed with C2 and C1 set
to 1 and 0, respectively. Figure 19 shows the input data format
for programming the function latch.
Counter Reset
DB2 (F1) is the counter reset bit. When this bit is 1, the R
counter and the AB counters are reset. For normal operation,
this bit should be 0. Upon powering up, the F1 bit needs to be
disabled (set to 0). Then, the N counter resumes counting in
close alignment with the R counter. (The maximum error is one
prescaler cycle.)
Power-Down
DB3 (PD1) and DB21 (PD2) provide programmable power-
down modes. They are enabled by the CE pin.
When the CE pin is low, the device is immediately disabled
regardless of the states of PD2 and PD1.
In the programmed asynchronous power-down, the device
powers down immediately after latching a 1 into the PD1 bit,
with the condition that PD2 has been loaded with a 0.
In the programmed synchronous power-down, the device
power-down is gated by the charge pump to prevent unwanted
frequency jumps. Once the power-down is enabled by writing a
1 into PD1 (on condition that a 1 has also been loaded to PD2),
then the device will go into power-down on the occurrence of
the next charge pump event.
When a power-down is activated (either synchronous or
asynchronous mode, including CE pin activated power-down),
the following events occur:
·
All active dc current paths are removed.
·
The R, N, and timeout counters are forced to their load
state conditions.
·
The charge pump is forced into three-state mode.
·
The digital lock detect circuitry is reset.
·
The RF
IN
input is debiased.
·
The reference input buffer circuitry is disabled.
·
The input register remains active and capable of loading
and latching data.
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, and M1 on
the ADF4108. Figure 19 shows the truth table.
Fastlock Enable Bit
DB9 of the function latch is the fastlock enable bit. Fastlock is
enabled only when this bit is 1.
Fastlock Mode Bit
DB10 of the function latch is the fastlock mode bit. When
fastlock is enabled, this bit determines which fastlock mode is
used. If the fastlock mode bit is 0, then Fastlock Mode 1 is
selected; and if the fastlock mode bit is 1, then Fastlock Mode 2
is selected.
Fastlock Mode 1
The charge pump current is switched to the contents of Current
Setting 2.
The device enters fastlock by having a 1 written to the CP gain
bit in the AB counter latch. The device exits fastlock by having a
0 written to the CP gain bit in the AB counter latch.
Fastlock Mode 2
The charge pump current is switched to the contents of Current
Setting 2.
The device enters fastlock by having a 1 written to the CP gain
bit in the AB counter latch. The device exits fastlock under the
control of the timer counter. After the timeout period
determined by the value in TC4:TC1, the CP gain bit in the AB
counter latch is automatically reset to 0 and the device reverts to
normal mode instead of fastlock. See Figure 19 for the timeout
periods.
Timer Counter Control
The user has the option of programming two charge pump
currents. The intent is that Current Setting 1 is used when the
RF output is stable and the system is in a static state. Current
Setting 2 is meant to be used when the system is dynamic and in
a state of change (that is, when a new output frequency is
programmed).
The normal sequence of events is as follows:
The user initially decides what the preferred charge pump
currents are going to be. For example, the choice may be 2.5 mA
as Current Setting 1 and 5 mA as Current Setting 2.
At the same time it must be decided how long the secondary
current is to stay active before reverting to the primary current.
This is controlled by the timer counter control bits, DB14:DB11
(TC4:TC1) in the function latch. The truth table is given in
Figure 19.
Now, to program a new output frequency, the user simply
programs the AB counter latch with new values for A and B. At
the same time, the CP gain bit can be set to 1, which sets the
charge pump with the value in CPI6:CPI4 for a period of time
determined by TC4TC1. When this time is up, the charge
pump current reverts to the value set by CPI3:CPI1. At the
same time, the CP gain bit in the AB counter latch is reset to 0
and is now ready for the next time the user wishes to change the
frequency.
Note that there is an enable feature on the timer counter. It is
enabled when Fastlock Mode 2 is chosen by setting the fastlock
mode bit (DB10) in the function latch to 1.
ADF4108
Rev. 0 | Page 17 of 20
Charge Pump Currents
CPI3, CPI2, and CPI1 program Current Setting 1 for the charge
pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the
charge pump. The truth table is given in Figure 19.
Prescaler Value
P2 and P1 in the function latch set the prescaler values. The
prescaler value should be chosen so that the prescaler output
frequency is always less than or equal to 300 MHz. Thus, with
an RF frequency of 4 GHz, a prescaler value of 16/17 is valid but
a value of 8/9 is not valid.
PD Polarity
This bit sets the phase detector polarity bit. See Figure 19.
CP Three-State
This bit controls the CP output pin. With the bit set high, the
CP output is put into three-state. With the bit set low, the CP
output is enabled.
INITIALIZATION LATCH
The initialization latch is programmed when C2 and C1 are set
to 1 and 1. This is essentially the same as the function latch
(programmed when C2, C1 = 1, 0).
However, when the initialization latch is programmed, an
additional internal reset pulse is applied to the R and AB
counters. This pulse ensures that the AB counter is at load point
when the AB counter data is latched and the device will begin
counting in close phase alignment.
If the latch is programmed for synchronous power-down (CE
pin is high; PD1 bit is high; PD2 bit is low), the internal pulse
also triggers this power-down. The prescaler reference and the
oscillator input buffer are unaffected by the internal reset pulse
and so close phase alignment is maintained when counting
resumes.
When the first AB counter data is latched after initialization, the
internal reset pulse is again activated. However, successive AB
counter loads after this will not trigger the internal reset pulse.
Device Programming after Initial Power-Up
After initially powering up the device, there are three ways to
program the device.
Initialization Latch Method
1.
Apply V
DD
.
2.
Program the initialization latch (11 in 2 LSBs of input
word). Make sure that the F1 bit is programmed to 0.
3.
Next, do a function latch load (10 in 2 LSBs of the control
word), making sure that the F1 bit is programmed to a 0.
4.
Then do an R load (00 in 2 LSBs).
5.
Then do an AB load (01 in 2 LSBs).
When the initialization latch is loaded, the following occurs:
·
The function latch contents are loaded.
·
An internal pulse resets the R, AB, and timeout counters to
load-state conditions and also three-states the charge pump.
Note that the prescaler band gap reference and the oscillator
input buffer are unaffected by the internal reset pulse, allowing
close phase alignment when counting resumes.
·
Latching the first AB counter data after the initialization word
will activate the same internal reset pulse. Successive AB loads
will not trigger the internal reset pulse unless there is another
initialization.
CE Pin Method
1.
Apply V
DD
.
2.
Bring CE low to put the device into power-down. This is an
asynchronous power-down in that it happens immediately.
3.
Program the function latch (10).
4.
Program the R counter latch (00).
5.
Program the AB counter latch (01).
6.
Bring CE high to take the device out of power-down. The R
and AB counters will now resume counting in close
alignment.
Note that after CE goes high, a duration of 1 s may be required
for the prescaler band gap voltage and oscillator input buffer
bias to reach steady state.
CE can be used to power the device up and down to check for
channel activity. The input register does not need to be
reprogrammed each time the device is disabled and enabled as
long as it has been programmed at least once after V
DD
was
initially applied.
Counter Reset Method
1.
Apply V
DD
.
2.
Do a function latch load (10 in 2 LSBs). As part of this,
load 1 to the F1 bit. This enables the counter reset.
3.
Do an R counter load (00 in 2 LSBs).
4.
Do an AB counter load (01 in 2 LSBs).
5.
Do a function latch load (10 in 2 LSBs). As part of this,
load 0 to the F1 bit. This disables the counter reset.
This sequence provides the same close alignment as the
initialization method. It offers direct control over the internal
reset. Note that counter reset holds the counters at load point
and three-states the charge pump, but does not trigger
synchronous power-down.
POWER SUPPLY CONSIDERATIONS
The ADF4108 operates over a power supply range of 3.2 V to
3.6 V. The ADP3300ART-3.3 is a low dropout linear regulator
from Analog Devices. It outputs 3.3 V with an accuracy of 1.4%
and is recommended for use with the ADF4108.
ADF4108
Rev. 0 | Page 18 of 20
INTERFACING
The ADF4108 has a simple SPITM-compatible serial interface for
writing to the device. CLK, DATA, and LE control the data
transfer. When LE (Latch Enable) goes high, the 24 bits that
have been clocked into the input register on each rising edge of
CLK are transferred to the appropriate latch. See Figure 2 for
the timing diagram and Table 5 for the latch truth table.
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible for the device is
833 kHz or one update every 1.2 s. This is certainly more than
adequate for systems that have typical lock times in hundreds of
microseconds.
ADuC812 INTERFACE
Figure 21 shows the interface between the ADF4108 and the
ADuC812 MicroConverter®. Since the ADuC812 is based on an
8051 core, this interface can be used with any 8051 based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4108 needs a
24-bit word. This is accomplished by writing three 8-bit bytes
from the MicroConverter to the device. When the third byte
has been written, the LE input should be brought high to
complete the transfer.
On first applying power to the ADF4108, it needs four writes
(one each to the initialization latch, function latch, R counter
latch, and N counter latch) for the output to become active.
I/O port lines on the ADuC812 are also used to control power-
down (CE input) and to detect lock (MUXOUT configured as
lock detect and polled by the port input).
When operating in the mode described, the maximum
SCLOCK rate of the ADuC812 is 4 MHz. This means that the
maximum rate at which the output frequency can be changed
will be 166 kHz.
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
MOSI
ADF4108
SCLOCK
I/O PORTS
ADuC812
0
6015-
026
Figure 21. ADuC812 to ADF4108 Interface
ADSP-2181 INTERFACE
Figure 22 shows the interface between the ADF4108 and the
ADSP-21xx Digital Signal Processor. The ADF4108 needs a
24-bit serial word for each latch write. The easiest way to
accomplish this using the ADSP21xx family is to use the
autobuffered transmit mode of operation with alternate
framing. This provides a means for transmitting an entire block
of serial data before an interrupt is generated. Set up the word
length for 8 bits and use three memory locations for each 24-bit
word. To program each 24-bit latch, store the three 8-bit bytes,
enable the autobuffered mode, and then write to the transmit
register of the DSP. This last operation initiates the autobuffer
transfer.
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
MOSI
ADF4108
SCLOCK
I/O FLAGS
ADSP-21xx
TFS
0
6015-
027
Figure 22. ADSP-21xx to ADF4108 Interface
ADF4108
Rev. 0 | Page 19 of 20
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
The lands on the chip scale package (CP-20) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the
pad. This will ensure that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern. This will ensure that
shorting is avoided.
Thermal vias can be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at 1.2 mm
pitch grid. The via diameter should be between 0.3 mm and
0.33 mm and the via barrel should be plated with 1 oz. copper
to plug the via.
The user should connect the printed circuit board thermal pad
to AGND.
ADF4108
Rev. 0 | Page 20 of 20
OUTLINE DIMENSIONS
16
9
8
1
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX
0.20
0.09
0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 23. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
1
20
5
6
11
16
15
10
2.25
2.10 SQ
1.95
0.75
0.55
0.35
0.30
0.23
0.18
0.50
BSC
12° MAX
0.20
REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
1.00
0.85
0.80
SEATING
PLANE
PIN 1
INDICATOR
TOP
VIEW
3.75
BCS SQ
4.00
BSC SQ
COPLANARITY
0.08
0.60
MAX
0.60
MAX
0.25 MIN
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
PIN 1
INDICATOR
Figure 24. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm x 4 mm Body, Very Thin Quad
(CP-20-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADF4108BRUZ
1
-40°C to +85°C
16-Lead Thin Shrink Small Outline Package [TSSOP]
RU-16
ADF4108BRUZ-RL
1
-40°C to +85°C
16-Lead Thin Shrink Small Outline Package [TSSOP]
RU-16
ADF4108BRUZ-RL7
1
-40°C to +85°C
16-Lead Thin Shrink Small Outline Package [TSSOP]
RU-16
ADF4108BCPZ
1
-40°C to +85°C
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
CP-20-1
ADF4108BCPZRL
1
-40°C to +85°C
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
CP-20-1
ADF4108BCPZRL7
1
-40°C to +85°C
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
CP-20-1
EVAL-ADF4108EB1
Evaluation
Board
1
Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06015-0-4/06(0)
Document Outline
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- GENERAL DESCRIPTION
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- LATCH SUMMARY
- REFERENCE COUNTER LATCH MAP
- AB COUNTER LATCH MAP
- FUNCTION LATCH MAP
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- INTERFACING
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