ADE7768 Energy Metering IC with Integrated Oscillator and Positive Power Accumulation Preliminary Data Sheets (Rev. PrE)

Energy Metering IC with Integrated

Oscillator and Positive Power Accumulation

Preliminary Technical Data

ADE7768

Rev. PrE

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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.

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Tel: 781.329.4700

www.analog.com

Fax: 781.326.8703

FEATURES

On-chip oscillator as clock source
High accuracy, supports 50 Hz/60 Hz IEC62053-21
Less than 0.1% error over a dynamic range of 500 to 1
Supplies positive-only average real power on frequency

outputs F1 and F2

High frequency output CF calibrates and supplies

instantaneous, positive-only real power

Logic output REVP indicates potential miswiring or negative

power

Direct drive for electromechanical counters and 2-phase

stepper motors (F1 and F2)

Proprietary ADCs and DSP provide high accuracy over

large variations in environmental conditions and time

On-chip power supply monitoring
On-chip creep protection (no-load threshold)
On-chip reference 2.5 V (20 ppm/°C typical) with

external overdrive capability

Single 5 V supply, low power (20 mW typical)
Low cost CMOS process
AC input only

GENERAL DESCRIPTION

The ADE7768

is a high accuracy, electrical energy metering IC.

It is a pin reduction version of the ADE7755, enhanced with a
precise oscillator circuit that serves as a clock source to the chip.
The ADE7768 eliminates the cost of an external crystal or
resonator, thus reducing the overall cost of a meter built with
this IC. The chip directly interfaces with the shunt resistor and
operates only with ac input.

U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; others pending.

The ADE7768 specifications surpass the accuracy require-
ments of the IEC62053-21 standard. The

AN-679 Application

Note

can be used as a basis for a description of an IEC61036

(equivalent to IEC62053-21) low cost, watt-hour meter
reference design.

The only analog circuitry used in the ADE7768 is in the -
ADCs and reference circuit. All other signal processing, such as
multiplication and filtering, is carried out in the digital domain.
This approach provides superior stability and accuracy over
time and extreme environmental conditions.

The ADE7768 supplies average, positive-only, real power
information on the low frequency outputs F1 and F2. These
outputs may be used to directly drive an electromechanical
counter or interface with an MCU. The high frequency CF logic
output, ideal for calibration purposes, provides instantaneous
positive-only, real power information.

The ADE7768 includes a power supply monitoring circuit on
the V

supply pin. The ADE7768 remains inactive until the

supply voltage on V

reaches approximately 4 V. If the supply

falls below 4 V, the ADE7768 also remains inactive and the F1,
F2, and CF outputs are in their nonactive modes.

Internal phase matching circuitry ensures that the voltage and
current channels are phase matched while the HPF in the
current channel eliminates dc offsets. An internal no-load
threshold ensures that the ADE7768 does not exhibit creep
when no load is present. When REVP is logic high, the
ADE7768 does not generate any pulse on F1, F2, and CF.

The ADE7768 comes in a 16-lead, narrow-body, SOIC package.

FUNCTIONAL BLOCK DIAGRAM

MULTIPLIER

REVP

V2P

V2N

V1P

RCLKIN

REF

IN/OUT

SCF S0

PHASE

CORRECTION

...110101...

SIGNAL

PROCESSING

BLOCK

POWER

SUPPLY MONITOR

ADC

V1N

ADE7768

...11011001...

2.5V

REFERENCE

AGND

DGND

INTERNAL

OSCILLATOR

ADC

LPF

HPF

DIGITAL-TO-FREQUENCY

CONVERTER

05331-

001

Figure 1.

ADE7768

Preliminary Technical Data

Rev. PrE | Page 2 of 24

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Terminology ...................................................................................... 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 10

Power Factor Considerations.................................................... 10

Nonsinusoidal Voltage and Current ........................................ 11

Analog Inputs.................................................................................. 12

Channel V1 (Current Channel)................................................ 12

Channel V2 (Voltage Channel) ................................................ 12

Typical Connection Diagrams.................................................. 12

Power Supply Monitor ................................................................... 13

HPF and Offset Effects .............................................................. 13

Digital-to-Frequency Conversion ............................................ 14

Connecting to a Microcontroller for Energy Measurement. 14

Power Measurement Considerations....................................... 15

Internal Oscillator (OSC) .............................................................. 16

Transfer Function ........................................................................... 17

Frequency Outputs F1 and F2 .................................................. 17

Example ....................................................................................... 17

Frequency Output CF ................................................................ 17

Selecting a Frequency for an Energy Meter Application........... 18

Frequency Outputs..................................................................... 18

No-Load Threshold........................................................................ 19

Negative Power Information..................................................... 19

Evaluation Board and Reference Design Board ......................... 20

Outline Dimensions ....................................................................... 21

Ordering Guide .......................................................................... 21

REVISION HISTORY

2/05--Preliminary Version

Preliminary Technical Data

ADE7768

Rev. PrE | Page 3 of 24

SPECIFICATIONS

= 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, RCLKIN = 6.2 k, 0.5% ± 50 ppm/°C, T

MIN

to T

MAX

= -40°C to +85°C,

unless otherwise noted.

Table 1.

Parameter Value

Unit

Test

Conditions/Comments

ACCURACY

Measurement Error

on Channel V1

0.1

% reading typ

Channel V2 with full-scale signal (±165 mV),
25°C over a dynamic range 500 to 1,
line frequency = 45 Hz to 65 Hz

Phase Error

Between Channels

V1 Phase Lead 37° (PF = 0.8 Capacitive)

±0.1

Degrees (°) max

V1 Phase Lag 60° (PF = 0.5 Inductive)

±0.1

Degrees (°) max

AC Power Supply Rejection

Output Frequency Variation (CF)

0.2

% reading typ

S0 = S1 = 1, V1 = 21.2 mV rms, V2 = 116.7 mV rms @
50 Hz, ripple on V

of 200 mV rms @ 100 Hz

DC Power Supply Rejection

Output Frequency Variation (CF)

±0.3

% reading typ

S0 = S1 = 1, V1 = 21.2 mV rms, V2 = 116.7 mV rms,
V

= 5 V ± 250 mV

ANALOG INPUTS

See the Analog Inputs section

Channel V1 Maximum Signal Level

±30

mV max

V1P and V1N to AGND

Channel V2 Maximum Signal Level

±165

mV max

V2P and V2N to AGND

Input Impedance (DC)

320

min

OSC = 450 kHz, RCLKIN = 6.2 k, 0.5% ± 50 ppm/°C

Bandwidth (3 dB)

kHz nominal

OSC = 450 kHz, RCLKIN = 6.2 k, 0.5% ± 50 ppm/°C

ADC Offset Error

1, 2

±18

max

See the Terminology and the Typical Performance
Characteristics sections

Gain Error

±4

% ideal typ

External 2.5 V reference, V1 = 21.2 mV rms,
V2 = 116.7 mV rms

OSCILLATOR FREQUENCY (OSC)

450

kHz nominal

RCLKIN = 6.2 k, 0.5% ± 50 ppm/°C

Oscillator Frequency Tolerance

±12

% reading typ

Oscillator Frequency Stability

±30

ppm/°C

typ

REFERENCE INPUT

REF

IN/OUT

Input Voltage Range

2.7

V max

2.5 V + 8%

2.3

V min

2.5 V - 8%

Input Capacitance

pF max

ON-CHIP REFERENCE

Nominal 2.5 V

Reference Error

±200

mV max

Temperature Coefficient

±20

ppm/°C typ

LOGIC INPUTS

SCF, S0, S1

Input High Voltage, V

INH

2.4

V min

= 5 V ± 5%

Input Low Voltage, V

INL

0.8

V max

= 5 V ± 5%

Input Current, I

±1

µA max

Typically 10 nA, V

= 0 V to V

Input Capacitance, C

pF max

LOGIC OUTPUTS

F1 and F2

Output High Voltage, V

4.5

V min

SOURCE

= 10 mA, V

= 5 V, I

SINK

= 10 mA, V

= 5 V

Output Low Voltage, V

0.5

V max

Output High Voltage, V

V min

SOURCE

= 5 mA, V

= 5 V, I

SINK

= 5 mA, V

= 5 V

Output Low Voltage, V

0.5

V max

Frequency Output Error

1, 2

(CF)

±10

% ideal typ

External 2.5 V reference, V1 = 21.2 mV rms,
V2 = 116.7 mV rms

ADE7768

Preliminary Technical Data

Rev. PrE | Page 4 of 24

Parameter Value

Unit

Test

Conditions/Comments

POWER SUPPLY

For specified performance

4.75

V min

5 V 5%

5.25

V max

5 V + 5%

mA max

Typically 4 mA

See the Terminology section for an explanation of specifications.

See the figures in the Typical Performance Characteristics section.

Sample tested during initial release and after any redesign or process change that may affect this parameter.

TIMING CHARACTERISTICS

= 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, RCLKIN = 6.2 k, 0.5% ± 50 ppm/°C, T

MIN

to T

MAX

= 40°C to +85°C,

unless otherwise noted. Sample tested during initial release and after any redesign or process change that may affect this parameter.
See Figure 2.

Table 2.

Parameter

Specifications

Unit

Test Conditions/Comments

120

F1 and F2 pulse width (logic low)

See Table 6

sec

Output pulse period. See the Transfer Function section.

1/2 t

sec

Time between F1 falling edge and F2 falling edge.

1, 2

CF pulse width (logic high).

See Table 7

sec

CF pulse period. See the Transfer Function section.

µs

Minimum time between F1 and F2 pulses.

The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Frequency Outputs section.

The CF pulse is always 35 µs in high frequency mode. See the Frequency Outputs section and Table 7.

05331-002

Figure 2. Timing Diagram for Frequency Outputs

Preliminary Technical Data

ADE7768

Rev. PrE | Page 5 of 24

ABSOLUTE MAXIMUM RATINGS

= 25°C, unless otherwise noted.

Table 3.

Parameter Values

to AGND

-0.3 V to +7 V

to DGND

-0.3 V to +7 V

Analog Input Voltage to AGND

V1P, V1N, V2P, and V2N

-6 V to +6 V

Reference Input Voltage to AGND

-0.3 V to V

+ 0.3 V

Digital Input Voltage to DGND

-0.3 V to V

+ 0.3 V

Digital Output Voltage to DGND

-0.3 V to V

+ 0.3 V

Operating Temperature Range

Industrial (A, B Versions)

-40°C to +85°C

Storage Temperature Range

-65°C to +150°C

Junction Temperature

150°C

16-Lead Plastic SOIC, Power Dissipation

350 mW

Thermal Impedance

124.9°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec)

215°C

Infrared (15 sec)

220°C

JEDEC 1S standard (2-layer) board data.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degrada-
tion or loss of functionality.

ADE7768

Preliminary Technical Data

Rev. PrE | Page 6 of 24

TERMINOLOGY

Measurement Error
The error associated with the energy measurement made by the
ADE7768 is defined by the following formula:

100

7768

Energy

True

Energy

True

ADE

Registered

Energy

Error

Phase Error Between Channels

The high-pass filter (HPF) in the current channel (Channel V1)
has a phase-lead response. To offset this phase response and
equalize the phase response between channels, a phase-
correction network is also placed in Channel V1. The phase-
correction network matches the phase to within 0.1° over a
range of 45 Hz to 65 Hz, and 0.2° over a range 40 Hz to 1 kHz
(see Figure 23 and Figure 24).

Power Supply Rejection
This quantifies the ADE7768 measurement error as a
percentage of reading when the power supplies are varied.

For the ac PSR measurement, a reading at nominal supplies
(5 V) is taken. A 200 mV rms/100 Hz signal is then introduced
onto the supplies and a second reading is obtained under the
same input signal levels. Any error introduced is expressed as a
percentage of reading--see the Measurement Error definition.

For the dc PSR measurement, a reading at nominal supplies
(5 V) is taken. The supplies are then varied 5% and a second
reading is obtained with the same input signal levels. Any error
introduced is again expressed as a percentage of reading.

ADC Offset Error
This refers to the small dc signal (offset) associated with the
analog inputs to the ADCs. However, the HPF in Channel V1
eliminates the offset in the circuitry. Therefore, the power
calculation is not affected by this offset.

Frequency Output Error (CF)
The frequency output error of the ADE7768 is defined as the
difference between the measured output frequency (minus the
offset) and the ideal output frequency. The difference is
expressed as a percentage of the ideal frequency. The ideal
frequency is obtained from the ADE7768 transfer function.

Gain Error
The gain error of the ADE7768 is defined as the difference
between the measured output of the ADCs (minus the offset)
and the ideal output of the ADCs. The difference is expressed as
a percentage of the ideal of the ADCs.

Oscillator Frequency Tolerance
The part-to-part frequency variation in terms of percentage at
room temperature (25°C). It is measured by taking the
difference between the measured oscillator frequency and the
nominal frequency defined in the Specifications section.

Oscillator Frequency Stability
Oscillator frequency stability is defined as frequency variation
in terms of the parts-per-million drift over the operating
temperature range. In a metering application, the temperature
range is -40°C to +85°C. Oscillator frequency stability is
measured by taking the difference between the measured
oscillator frequency at -40°C and +85°C and the measured
oscillator frequency at +25°C.

Preliminary Technical Data

ADE7768

Rev. PrE | Page 7 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

V2P

V2N

V1N

DGND

V1P

REVP

AGND

RCLKIN

REF

IN/OUT

SCF

ADE7768

TOP VIEW

(Not to Scale)

05331-003

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

Power Supply. This pin provides the supply voltage for the circuitry in the ADE7768. The supply voltage
should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled with a 10 µF
capacitor in parallel with a ceramic 100 nF capacitor.

2, 3

V2P, V2N

Analog Inputs for Channel V2 (Voltage Channel). These inputs provide a fully differential input pair. The
maximum differential input voltage is ±165 mV for specified operation. Both inputs have internal ESD
protection circuitry; an overvoltage of ±6 V can be sustained on these inputs without risk of permanent
damage.

4, 5

V1N, V1P

Analog Inputs for Channel V1 (Current Channel). These inputs are fully differential voltage inputs with a
maximum signal level of ±30 mV with respect to the V1N pin for specified operation. Both inputs have
internal ESD protection circuitry and, in addition, an overvoltage of ±6 V can be sustained on these inputs
without risk of permanent damage.

AGND

This pin provides the ground reference for the analog circuitry in the ADE7768, that is, the ADCs and
reference. This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the
ground reference for all analog circuitry--antialiasing filters, current and voltage sensors, and so forth. For
accurate noise suppression, the analog ground plane should be connected to the digital ground plane at
only one point. A star ground configuration helps to keep noisy digital currents away from the analog
circuits.

REF

IN/OUT

This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 2.5 V
and a typical temperature coefficient of 20 ppm/°C. An external reference source may also be connected at
this pin. In either case, this pin should be decoupled to AGND with a 1 µF tantalum capacitor and a 100 nF
ceramic capacitor. The internal reference cannot be used to drive an external load.

SCF

Select Calibration Frequency. This logic input is used to select the frequency on the calibration output CF.
See Table 7.

9, 10

S1, S0

These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion.
With this logic input, designers have greater flexibility when designing an energy meter. See the Selecting a
Frequency for an Energy Meter Application section.

RCLKIN

To enable the internal oscillator as a clock source to the chip, a precise low temperature drift resistor at a
nominal value of 6.2 k must be connected from this pin to DGND.

REVP

This logic output goes high when negative power is detected, that is, when the phase angle between the
voltage and current signals is greater than 90°. This output is not latched and is reset when positive power is
once again detected. The output goes high or low at the same time that a pulse is issued on CF.

DGND

This pin provides the ground reference for the digital circuitry in the ADE7768, that is, the multiplier, filters,
and digital-to-frequency converter. This pin should be tied to the digital ground plane of the PCB. The digital
ground plane is the ground reference for all digital circuitry, such as counters (mechanical and digital), MCUs,
and indicator LEDs. For accurate noise suppression, the analog ground plane should be connected to the
digital ground plane at one point only--a star ground.

Calibration Frequency Logic Output. The CF logic output provides instantaneous, positive-only real power
information. This output is intended for calibration purposes. See the SCF pin description.

15, 16

F2, F1

Low Frequency Logic Outputs. F1 and F2 supply average positive-only real power information. The logic
outputs can be used to directly drive electromechanical counters and 2-phase stepper motors. See the
Transfer Function section.

ADE7768

Preliminary Technical Data

Rev. PrE | Page 8 of 24

TYPICAL PERFORMANCE CHARACTERISTICS

6.2k

V2N

200

220V

150nF

V2P

200

602k

V1P

V1N

350

40A TO

40mA

REF

IN/OUT

100nF

DGND

REVP

RCLKIN

SCF

10nF

PS2501-1

ADE7768

10k

200

150nF

AGND

150nF

820

05331-004

Figure 4. Test Circuit for Performance Curves

1.0

0.8

0.6

0.4

0.2

RROR (% of Re

ing)

0.2

0.4

0.6

05331-019

CURRENT CHANNEL (% of Full Scale)

0.1

100

0.8

1.0

+25

+85

40

Figure 5. Error as a % of Reading over Temperature

with On-Chip Reference (PF = 1)

1.0

0.8

0.6

0.4

0.2

RROR (% of Re

ing)

0.2

0.4

0.6

05331-020

CURRENT CHANNEL (% of Full Scale)

0.1

100

0.8

1.0

40

C, PF = 0.5 IND

+25

C, PF = 1

+85

C, PF = 0.5 IND

+25

C, PF = 0.5 IND

Figure 6. Error as a % of Reading over Temperature with On-Chip Reference

(PF = 0.5)

1.0

0.8

0.6

0.4

0.2

RROR (% of Re

ing)

0.2

0.4

0.6

05331-021

CURRENT CHANNEL (% of Full Scale)

0.1

100

0.8

1.0

+25

+85

40

Figure 7. Error as a % of Reading over Temperature

with External Reference (PF = 1)

1.0

0.8

0.6

0.4

0.2

RROR (% of Re

ing)

0.2

0.4

0.6

05331-022

CURRENT CHANNEL (% of Full Scale)

0.1

100

0.8

1.0

+25

C, PF = 1

40

C, PF = 0.5 IND

+25

C, PF = 0.5 IND

+85

C, PF = 0.5 IND

Figure 8. Error as a % of Reading over Temperature

with External Reference (PF = 0.5)

Preliminary Technical Data

ADE7768

Rev. PrE | Page 9 of 24

0.5

0.4

0.3

0.2

0.1

0.2

0.3

0.4

0.5

RROR (% of Re

ing)

FREQUENCY (Hz)

05331-018

PF = 0.5 IND

PF = 0.5 CAP

PF = 1

Figure 9. Error as a % of Reading over Input Frequency

1.0

0.8

0.6

0.4

0.2

RROR (% of Re

ing)

0.2

0.4

0.6

05331-023

CURRENT CHANNEL (% of Full Scale)

0.1

100

0.8

1.0

5.25V

4.75V

Figure 10. PSR with Internal Reference, PF = 1

1.0

0.8

0.6

0.4

0.2

RROR (% of Re

ing)

0.2

0.4

0.6

05331-024

CURRENT CHANNEL (% of Full Scale)

0.1

100

0.8

1.0

5.25V

4.75V

Figure 11. PSR with External Reference, PF = 1

FRE

NCY

CHANNEL V1 OFFSET (mV)

05331-025

5 4 3 2 1

EXTERNAL REFERENCE

TEMPERATURE = 25

MEAN = 2.247828

SDs = 1.367176

MIN = 2.09932

MAX = 5.28288

NO. OF POINTS = 100

Figure 12. Channel V1 Offset Distribution

FRE

NCY

CHANNEL V2 OFFSET (mV)

05331-026

12 10 8

MEAN = 1.563484

SDs = 2.040699

MIN = 6.82969

MAX = 2.6119

NO. OF POINTS = 100

EXTERNAL REFERENCE

TEMPERATURE = 25

Figure 13. Channel V2 Offset Distribution

10

200

400

600

800

1000

FRE

NCY

DEVIATION FROM MEAN (%)

05331-027

EXTERNAL REFERENCE

TEMPERATURE = 25

MEAN = 0%

SDs = 1.55%

MIN = 11.79%

MAX = 6.08%

NO. OF POINTS = 3387

Figure 14. Part-to-Part CF Distribution from Mean

ADE7768

Preliminary Technical Data

Rev. PrE | Page 10 of 24

THEORY OF OPERATION

The two ADCs in the ADE7768 digitize the voltage signals from
the current and voltage sensors. These ADCs are 16-bit -
with an oversampling rate of 450 kHz. This analog input
structure greatly simplifies sensor interfacing by providing a
wide dynamic range for direct connection to the sensor and also
simplifies the antialiasing filter design. A high-pass filter in the
current channel removes any dc component from the current
signal. This eliminates any inaccuracies in the real power
calculation due to offsets in the voltage or current signals.
Because the HPF is always enabled, the IC operates only with
ac input (see the HPF and Offset Effects section).

The real power calculation is derived from the instantaneous
power signal. The instantaneous power signal is generated by a
direct multiplication of the current and voltage signals. In order
to extract the real power component (the dc component), the
instantaneous power signal is low-pass filtered. Figure 15
illustrates the instantaneous real power signal and shows how
the real power information can be extracted by low-pass
filtering the instantaneous power signal. (In the ADE7768,
this signal is compared to 0 and only positive real power is
accumulated for F1, F2, and CF pulse outputs.) This scheme
correctly calculates real power for sinusoidal current and
voltage waveforms at all power factors. All signal processing is
carried out in the digital domain for superior stability over
temperature and time.

TIME

ADC

CH1

CH2

MULTIPLIER

F1
F2

DIGITAL-TO-

FREQUENCY

DIGITAL-TO-

FREQUENCY

INSTANTANEOUS REAL

POWER SIGNAL

INSTANTANEOUS

POWER SIGNAL p(t)

LPF

HPF

05331-005

Figure 15. Signal Processing Block Diagram

The low frequency outputs (F1, F2) of the ADE7768 are gener-
ated by accumulating positive-only real power information.
This low frequency inherently means a long accumulation
time between output pulses. Consequently, the resulting output
frequency is proportional to the average positive-only real
power. This average positive only real power information is
then accumulated (by a counter) to generate real energy
information. Conversely, due to its high output frequency
and shorter integration time, the CF output frequency is
proportional to the instantaneous positive-only real power. This
is useful for system calibration, which can be done faster under
steady load conditions.

POWER FACTOR CONSIDERATIONS

The method used to extract the real power information from
the instantaneous power signal (that is, by low-pass filtering) is
still valid even when the voltage and current signals are not in
phase. Figure 16 displays the unity power factor condition and a
displacement power factor (DPF) = 0.5 (a current signal lagging
the voltage by 60). Assuming the voltage and current waveforms
are sinusoidal, the real power component of the instantaneous
power signal (that is, the dc term) is given by

( )

cos

(1)

This is the correct real power calculation.

POWER

CURRENT

VOLTAGE

POWER

TIME

VOLTAGE

CURRENT

COS (60

)

INSTANTANEOUS

POWER SIGNAL

INSTANTANEOUS REAL

POWER SIGNAL

INSTANTANEOUS

POWER SIGNAL

INSTANTANEOUS REAL

POWER SIGNAL

05331-006

Figure 16. DC Component of Instantaneous Power Signal Conveys Real

Power Information, PF < 1

Preliminary Technical Data

ADE7768

Rev. PrE | Page 11 of 24

NONSINUSOIDAL VOLTAGE AND CURRENT

The real power calculation method also holds true for
nonsinusoidal current and voltage waveforms. All voltage and
current waveforms in practical applications have some
harmonic content. Using the Fourier Transform, instantaneous
voltage and current waveforms can be expressed in terms of
their harmonic content.

(

)

sin

)

(

(2)

where:
v(t) is the instantaneous voltage.
V

is the average value.

is the rms value of voltage harmonic h.

is the phase angle of the voltage harmonic.

(

)

sin

)

(

(3)

where:
i(t) is the instantaneous current.
I

is the dc component.

is the rms value of current harmonic h.

is the phase angle of the current harmonic.

Using Equations 2 and 3, the real power (P) can be expressed in
terms of its fundamental real power (P1) and harmonic real
power (P

) as P = P

+ P

where:

cos

(4)

and

cos

(5)

In Equation 5, a harmonic real power component is generated
for every harmonic, provided that harmonic is present in both
the voltage and current waveforms. The power factor calcul-
ation has previously been shown to be accurate in the case of a
pure sinusoid. Therefore, the harmonic real power must also
correctly account for the power factor, because it is made up of
a series of pure sinusoids.

Note that the input bandwidth of the analog inputs is 7 kHz at
the nominal internal oscillator frequency of 450 kHz.

ADE7768

Preliminary Technical Data

Rev. PrE | Page 12 of 24

ANALOG INPUTS

CHANNEL V1 (CURRENT CHANNEL)

The voltage output from the current sensor is connected to the
ADE7768 here. Channel V1 is a fully differential voltage input.
V1P is the positive input with respect to V1N.

The maximum peak differential signal on Channel V1 should
be less than ±30 mV (21 mV rms for a pure sinusoidal signal)
for specified operation.

+30mV

30mV

DIFFERENTIAL INPUT

30mV MAX PEAK

COMMON-MODE

6.25mV MAX

V1P

V1N

AGND

05331-007

Figure 17. Maximum Signal Levels, Channel V1

The diagram in Figure 17 illustrates the maximum signal levels
on V1P and V1N. The maximum differential voltage is ±30
mV. The differential voltage signal on the inputs must be
referenced to a common mode, such as AGND. The maximum
common-mode signal is ±6.25 mV, as shown in Figure 17.

CHANNEL V2 (VOLTAGE CHANNEL)

The output of the line voltage sensor is connected to the
ADE7768 at this analog input. Channel V2 is a fully differential
voltage input with a maximum peak differential signal of ±165
mV. Figure 18 illustrates the maximum signal levels that can be
connected to the ADE7768 Channel V2.

+165mV

165mV

DIFFERENTIAL INPUT

165mV MAX PEAK

COMMON-MODE

25mV MAX

V2P

V2N

AGND

05331-008

Figure 18. Maximum Signal Levels, Channel V2

Channel V2 is usually driven from a common-mode voltage--
that is, the differential voltage signal on the input is referenced
to a common mode (usually AGND). The analog inputs of the
ADE7768 can be driven with common-mode voltages of up to
25 mV with respect to AGND. However, best results are
achieved using a common mode equal to AGND.

TYPICAL CONNECTION DIAGRAMS

Figure 19 shows a typical connection diagram for Channel V1.
A shunt is the current sensor selected for this example because
of its low cost compared to other current sensors, such as the
current transformer (CT). This IC is ideal for low current
meters.

V1P

V1N

30mV

SHUNT

AGND

PHASE

NEUTRAL

05331-009

Figure 19. Typical Connection for Channel V1

Figure 20 shows a typical connection for Channel V2. Typically,
the ADE7768 is biased around the phase wire, and a resistor
divider is used to provide a voltage signal that is proportional to
the line voltage. Adjusting the ratio of R

, R

, and R

is also a

convenient way of carrying out a gain calibration on a meter.

V2P

V2N

PHASE

NEUTRAL

165mV

+ R

05331-010

Figure 20. Typical Connections for Channel V2

Preliminary Technical Data

ADE7768

Rev. PrE | Page 13 of 24

POWER SUPPLY MONITOR

The ADE7768 contains an on-chip power supply monitor. The
power supply (V

) is continuously monitored by the ADE7768.

If the supply is less than 4 V, the ADE7768 becomes inactive.
This is useful to ensure proper device operation at power-up
and power-down. The power supply monitor has built in
hysteresis and filtering that provide a high degree of immunity
to false triggering from noisy supplies.

In Figure 21, the trigger level is nominally set at 4 V. The toler-
ance on this trigger level is within ±5%. The power supply and
decoupling for the part should be such that the ripple at V

does not exceed 5 V ± 5% as specified for normal operation.

5V
4V

TIME

INACTIVE

ACTIVE

INACTIVE

INTERNAL

ACTIVATION

05331-011

Figure 21. On-Chip Power Supply Monitor

HPF AND OFFSET EFFECTS

Figure 22 illustrates the effect of offsets on the real power
calculation. As can be seen, offsets on Channel V1 and Channel
V2 contribute a dc component after multiplication. Because this
dc component is extracted by the LPF and used to generate the
real power information, the offsets contribute a constant error
to the real power calculation. This problem is easily avoided by
the built-in HPF in Channel V1. By removing the offsets from
at least one channel, no error component can be generated at dc
by the multiplication. Error terms at the line frequency () are
removed by the LPF and the digital-to-frequency conversion
(see the Digital-to-Frequency Conversion section).

Equation 6 shows how the power calculation is affected by the
dc offsets in the current and voltage channels.

( )

{

}

( )

{

}

cos

(6)

( )

cos

( )

cos

DC COMPONENT (INCLUDING ERROR TERM)

IS EXTRACTED BY THE LPF FOR REAL

POWER CALCULATION

FREQUENCY (RAD/s)

05331-012

Figure 22. Effect of Channel Offset on the Real Power Calculation

The HPF in Channel V1 has an associated phase response that
is compensated for on chip. Figure 23 and Figure 24 show the
phase error between channels with the compensation network
activated. The ADE7768 is phase compensated up to 1 kHz as
shown. This ensures correct active harmonic power calculation
even at low power factors.

FREQUENCY (Hz)

0.30

SE (

egrees)

0.25

0.20

0.15

0.10

0.05

0.10

100

200

300

400

500

600

700

800

900 1000

05331-013

Figure 23. Phase Error between Channels (0 Hz to 1 kHz)

FREQUENCY (Hz)

0.30

SE (

egrees)

0.25

0.20

0.15

0.10

0.05

0.10

05331-014

Figure 24. Phase Error between Channels (40 Hz to 70 Hz)

ADE7768

Preliminary Technical Data

Rev. PrE | Page 14 of 24

DIGITAL-TO-FREQUENCY CONVERSION

As previously described, the digital output of the low-pass filter
after multiplication contains the positive-only real power
information. However, because this LPF is not an ideal brick
wall filter implementation, the output signal also contains
attenuated components at the line frequency and its harmonics,
that is, cos(ht) where h = 1, 2, 3, . . . and so on.

The magnitude response of the filter is given by

( )

(7)

For a line frequency of 50 Hz, this gives an attenuation of
the 2 (100 Hz) component of approximately 22 dB. The
dominating harmonic is twice the line frequency (2) due to
the instantaneous power calculation.

Figure 25 shows the instantaneous positive only real power
signal at the output of the LPF that still contains a significant
amount of instantaneous power information, that is, cos(2t).
This signal is then passed to the digital-to-frequency converter
where it is compared to 0 and only positive real power is
integrated (accumulated) over time in order to produce an
output frequency. The accumulation of the signal suppresses
or averages out any non-dc components in the instantaneous
positive-only real power signal. The average value of a
sinusoidal signal is zero. Thus, the frequency generated by
the ADE7768 is proportional to the average positive-only real
power. Figure 25 shows the digital-to-frequency conversion
for steady load conditions--that is, the constant voltage and
current.

F1
F2

DIGITAL-TO-

FREQUENCY

DIGITAL-TO-

FREQUENCY

MULTIPLIER

TIME

FRE

NCY

FRE

NCY

FREQUENCY (RAD/s)

COS (2

)

ATTENUATED BY LPF

LPF TO EXTRACT

REAL POWER

(DC TERM)

INSTANTANEOUS REAL POWER SIGNAL

(FREQUENCY DOMAIN)

LPF

05331-

015

Figure 25. Positive Only Real Power-to-Frequency Conversion

In Figure 25, the frequency output CF varies over time, even
under steady load conditions. This frequency variation is
primarily due to the cos(2 t) component in the instantaneous
positive-only real power signal. The output frequency on CF
can be up to 2048 times higher than the frequency on F1 and
F2. This higher output frequency is generated by accumulating
the instantaneous positive only real power signal over a much
shorter time while converting it to a frequency. This shorter
accumulation period means less averaging of the cos(2 t)
component. Consequently, some of this instantaneous power
signal passes through the digital-to-frequency conversion. This
is not a problem in the application. Where CF is used for
calibration purposes, the frequency should be averaged by the
frequency counter, which removes any ripple. If CF is being
used to measure energy, for example in a microprocessor based
application, the CF output should also be averaged to calculate
power.

Because the outputs F1 and F2 operate at a much lower
frequency, a lot more averaging of the instantaneous positive-
only real power signal is carried out. The result is a greatly
attenuated sinusoidal content and a virtually ripple-free
frequency output.

CONNECTING TO A MICROCONTROLLER FOR
ENERGY MEASUREMENT

The easiest way to interface the ADE7768 to a microcontroller
is to use the CF high frequency output with the output
frequency scaling set to 2048 × F1, F2. This is done by setting
SCF = 0 and S0 = S1 = 1 (see Table 7). With full-scale ac
signals on the analog inputs, the output frequency on CF is
approximately 2.867 kHz. Figure 26 illustrates one scheme that
could be used to digitize the output frequency and carry out the
necessary averaging mentioned in the previous section.

TIME

10%

FREQUENCY

RIPPLE

AVERAGE

FREQUENCY

ADE7768

COUNTER

TIMER

MCU

05331-016

Figure 26. Interfacing the ADE7768 to an MCU

Preliminary Technical Data

ADE7768

Rev. PrE | Page 15 of 24

As shown in Figure 26, the frequency output CF is connected to
an MCU counter or port. This counts the number of pulses in a
given integration time, which is determined by an MCU
internal timer. The average power proportional to the average
frequency is given by

Time

Counter

Power

Average

Frequency

Average

(8)

The energy consumed during an integration period is given by

)

(

Counter

Time

Counter

Time

Power

Average

Energy

For the purpose of calibration, this integration time could be
10 seconds to 20 seconds, in order to accumulate enough
pulses to ensure correct averaging of the frequency. In normal
operation, the integration time could be reduced to one or two

seconds, depending, for example, on the required update rate of
a display. With shorter integration times on the MCU, the
amount of energy in each update may still have some small
amount of ripple, even under steady load conditions. However,
over a minute or more the measured energy has no ripple.

POWER MEASUREMENT CONSIDERATIONS

Calculating and displaying power information always has some
associated ripple that depends on the integration period used in
the MCU to determine average power and also on the load. For
example, at light loads, the output frequency may be 10 Hz.
With an integration period of two seconds, only about 20 pulses
are counted. The possibility of missing one pulse always exists,
because the ADE7768 output frequency is running asynchro-
nously to the MCU timer. This results in a 1-in-20 or 5% error
in the power measurement. When REVP is logic high, the
ADE7768 does not generate any pulse on F1, F2, and CF.

ADE7768

Preliminary Technical Data

Rev. PrE | Page 16 of 24

INTERNAL OSCILLATOR (OSC)

The nominal internal oscillator frequency is 450 kHz when
used with RCLKIN, with a nominal value of 6.2 k. The
frequency outputs are directly proportional to the oscillator
frequency, thus RCLKIN must have low tolerance and low
temperature drift to ensure stability and linearity of the chip.
The oscillator frequency is inversely proportional to the
RCLKIN, as shown in Figure 27. Although the internal
oscillator operates when used with RCLKIN values between
5.5 k and 20 k, choosing a value within the range of the
nominal value, as shown in Figure 27, is recommended.

RESISTANCE (k

)

5.8

5.9

6.1

6.3

6.7

FRE

NCY

Hz)

420

430

440

450

460

480

470

490

6.0

6.2

6.4

6.5

6.6

410

400

05331-017

Figure 27. Effect of RCLKIN on Internal Oscillator Frequency (OSC)

Preliminary Technical Data

ADE7768

Rev. PrE | Page 17 of 24

TRANSFER FUNCTION

FREQUENCY OUTPUTS F1 AND F2

The ADE7768 calculates the product of two voltage signals
(on Channel V1 and Channel V2) and then low-pass filters this
product to extract positive-only real power information. This
positive-only real power information is then converted to a
frequency. The frequency information is output on F1 and F2
in the form of active low pulses. The pulse rate at these outputs
is relatively low--for example, 0.175 Hz maximum for ac signals
with S0 = S1 = 0 (see Table 6). This means that the frequency at
these outputs is generated from positive-only real power
information accumulated over a relatively long period of time.
The result is an output frequency that is proportional to the
average positive-only real power. The averaging of the positive-
only real power signal is implicit to the digital-to-frequency
conversion. The output frequency or pulse rate is related to the
input voltage signals by the following equation:

515

REF

rms

Freq

(10)

where:
Freq = Output frequency on F1 and F2 (Hz).
V1

rms

= Differential rms voltage signal on Channel V1 (V).

rms

= Differential rms voltage signal on Channel V2 (V).

REF

= The reference voltage (2.5 V ± 8%) (V).

1-4

= One of four possible frequencies selected by using the

logic inputs S0 and S1 (see Table 5).

Table 5. F

14

Frequency Selection

OSC Relation

14

at Nominal OSC (Hz)

OSC/2

0.86

OSC/2

1.72

OSC/2

3.43

OSC/2

6.86

is a binary fraction of the internal oscillator frequency.

Values are generated using the nominal frequency of 450 kHz.

EXAMPLE

In this example, with ac voltages of ±30 mV peak applied to
V1 and ±165 mV peak applied to V2, the expected output
frequency is calculated as follows:

= OSC/2

Hz, S0 = S1 = 0

rms

= 0.03/2 V

rms

= 0.165/2 V

REF

= 2.5 V (nominal reference value)

Note that if the on-chip reference is used, actual output
frequencies may vary from device to device due to the
reference tolerance of ±8%.

175

204

165

515

Freq

(11)

Table 6. Maximum Output Frequency on F1 and F2

OSC Relation Max Frequency

or AC Inputs (Hz)

0.204 × F

0.175

0.204 × F

0.35

0.204 × F

0.70

0.204 × F

1.40

Values are generated using the nominal frequency of 450 kHz.

FREQUENCY OUTPUT CF

The pulse output CF (calibration frequency) is intended for
calibration purposes. The output pulse rate on CF can be up
to 2048 times the pulse rate on F1 and F2. The lower the F

frequency selected, the higher the CF scaling (except for the
high frequency mode SCF = 0, S1 = S0 = 1). Table 7 shows
how the two frequencies are related, depending on the states of
the logic inputs S0, S1, and SCF. Due to its relatively high pulse
rate, the frequency at the CF logic output is proportional to the
instantaneous positive-only real power. As with F1 and F2, CF
is derived from the output of the low-pass filter after multipli-
cation. However, because the output frequency is high, this
positive-only real power information is accumulated over a
much shorter time. Therefore, less averaging is carried out in
the digital-to-frequency conversion. With much less averaging
of the positive-only real power signal, the CF output is much
more responsive to power fluctuations (see the signal
processing block in Figure 15).

Table 7. Maximum Output Frequency on CF

SCF

CF Max for AC Signals (Hz)

128 × F1, F2 = 22.4

64 × F1, F2 = 11.2

64 × F1, F2 = 22.4

32 × F1, F2 = 11.2

32 × F1, F2 = 22.4

16 × F1, F2 = 11.2

16 × F1, F2 = 22.4

2048 × F1, F2 = 2.867 kHz

Values are generated using the nominal frequency of 450 kHz.

ADE7768

Preliminary Technical Data

Rev. PrE | Page 18 of 24

SELECTING A FREQUENCY FOR AN ENERGY METER APPLICATION

As shown in Table 5, the user can select one of four frequencies.
This frequency selection determines the maximum frequency
on F1 and F2. These outputs are intended for driving an energy
register (electromechanical or other). Because only four
different output frequencies can be selected, the available
frequency selection has been optimized for a meter constant
of 100 imp/kWh with a maximum current of between 10 A
and 120 A. Table 8 shows the output frequency for several
maximum currents (I

MAX

) with a line voltage of 220 V. In all

cases, the meter constant is 100 imp/kWh.

Table 8. F1 and F2 Frequency at 100 imp/kWh

MAX

(A)

F1 and F2 (Hz)

12.5

0.076

25.0

0.153

40.0

0.244

60.0

0.367

80.0

0.489

120.0

0.733

The F

frequencies allow complete coverage of this range of

output frequencies (F1, F2). When designing an energy meter,
the nominal design voltage on Channel V2 (voltage) should be
set to half-scale to allow for calibration of the meter constant.
The current channel should also be no more than half scale
when the meter sees maximum load. This allows over current
signals and signals with high crest factors to be accommodated.
Table 9 shows the output frequency on F1 and F2 when both
analog inputs are half scale. The frequencies listed in Table 9
align very well with those listed in Table 8 for maximum load.

Table 9. F1 and F2 Frequency with Half-Scale AC Inputs

S1 S0 F

14

(Hz)

Frequency on F1 and F2--
CH1 and CH2 Half-Scale AC Input

0.86

0.051 × F

0.044 Hz

1.72

0.051 × F

0.088 Hz

3.43

0.051 × F

0.176 Hz

6.86

0.051 × F

0.352 Hz

Values are generated using the nominal frequency of 450 kHz.

When selecting a suitable F

frequency for a meter design, the

frequency output at I

MAX

(maximum load) with a meter constant

of 100 imp/kWh should be compared with column four of Table
9. The closest frequency in Table 9 determines the best choice of
frequency (F

). For example, if a meter with a maximum

current of 25 A is being designed, the output frequency on F1
and F2 with a meter constant of 100 imp/kWh is 0.153 Hz at 25
A and 220 V (from Table 8). In Table 9, the closest frequency to
0.153 Hz in column four is 0.176 Hz. Therefore, as shown in
Table 5, F3 (3.43 Hz) is selected for
this design.

FREQUENCY OUTPUTS

Figure 2 shows a timing diagram for the various frequency
outputs. The outputs F1 and F2 are the low frequency outputs
that can be used to directly drive a stepper motor or electro-
mechanical impulse counter. The F1 and F2 outputs provide
two alternating low frequency pulses. The F1 and F2 pulse
widths (t

) are set such that if they fall below 240 ms (0.24 Hz)

they are set to half of their period. The maximum output
frequencies for F1 and F2 are shown in Table 6.

The high frequency CF output is intended for communications
and calibration purposes. CF produces a 90-ms-wide active
high pulse (t

) at a frequency proportional to active power. The

CF output frequencies are given in Table 7. As with F1 and F2,
if the period of CF (t

) falls below 180 ms, the CF pulse width is

set to half the period. For example, if the CF frequency is 20 Hz,
the CF pulse width is 25 ms.

When high frequency mode is selected (SCF = 0, S1 = S0 = 1),
the CF pulse width is fixed at 35 µs. Therefore, t

is always 35 µs,

regardless of output frequency on CF.

Preliminary Technical Data

ADE7768

Rev. PrE | Page 19 of 24

NO-LOAD THRESHOLD

The ADE7768 also includes a no-load threshold and start-up
current feature that eliminates any creep effects in the meter.
The ADE7768 is designed to issue a minimum output
frequency. Any load generating a frequency lower than this
minimum frequency does not cause a pulse to be issued on F1,
F2, or CF. The minimum output frequency is given as 0.00244%
for each of the F

frequency selections (see Table 5).

For example, for an energy meter with a meter constant of
100 imp/kWh on F1, F2 using F

(3.43 Hz), the minimum

output frequency at F1 or F2 would be 0.00244% of 3.43 Hz or
8.38 × 10

Hz. This would be 2.68 × 10

Hz at CF (32 × F1 Hz)

when SCF = S0 = 1, S1 = 0. In this example, the no-load

threshold would be equivalent to 3 W of load or a start-up
current of 13.72 mA at 220 V. Compare this value to the
IEC62053-21 specification which states that the meter must
start up with a load equal to or less than 0.4% Ib. For a 5 A (Ib)
meter, 0.4% of Ib is equivalent to 20 mA.

NEGATIVE POWER INFORMATION

The ADE7768 detects when the current and voltage channels
have a phase shift greater than 90°. This mechanism can detect
wrong connection of the meter or generation of negative power.
The REVP pin output goes active high when negative power is
detected and active low if positive power is detected. The REVP
pin output changes state as a pulse is issued on CF.

Preliminary Technical Data

ADE7768

Rev. PrE | Page 21 of 24

OUTLINE DIMENSIONS

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MS-012AC

4.00 (0.1575)
3.80 (0.1496)

10.00 (0.3937)

9.80 (0.3858)

1.27 (0.0500)

BSC

6.20 (0.2441)
5.80 (0.2283)

SEATING

PLANE

0.25 (0.0098)
0.10 (0.0039)

0.51 (0.0201)
0.31 (0.0122)

1.75 (0.0689)
1.35 (0.0531)

8°
0°

0.50 (0.0197)
0.25 (0.0098)

1.27 (0.0500)
0.40 (0.0157)

0.25 (0.0098)
0.17 (0.0067)

COPLANARITY

0.10

45°

Figure 28. 16-Lead Standard Small Outline Package [SOIC]

Narrow Body [R-16]

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

ADE7768AR

-40°C to +85°C

SOIC Narrow Body

R-16

ADE7768AR-RL

-40°C to +85°C

SOIC Narrow Body in Reel

R-16

ADE7768ARZ

-40°C to +85°C

Lead-Free SOIC Narrow Body

R-16

ADE7768ARZ-RL

-40°C to +85°C

Lead-Free SOIC Narrow Body in Reel

R-16

EVAL-ADE7769EB

Evaluation Board

ADE7768ARN-REF

Reference Design Board

Z = Pb-free part.

Part Number ADE7768

Document Outline