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Part Number AD9831

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AD9831 CMOS Complete DDS
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REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
CMOS
Complete DDS
AD9831
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
FEATURES
3 V/5 V Power Supply
25 MHz Speed
On-Chip SINE Look-Up Table
On-Chip 10-Bit DAC
Parallel Loading
Powerdown Option
72 dB SFDR
125 mW (5 V) Power Consumption
40 mW (3 V) Power Consumption
48-Pin TQFP
APPLICATIONS
DDS Tuning
Digital Demodulation
GENERAL DESCRIPTION
This DDS device is a numerically controlled oscillator employ-
ing a phase accumulator, a sine look-up table and a 10-bit D/A
converter integrated on a single CMOS chip. Modulation
capabilities are provided for phase modulation and frequency
modulation.
Clock rates up to 25 MHz are supported. Frequency accuracy
can be controlled to one part in 4 billion. Modulation is effected
by loading registers through the parallel microprocessor
interface.
A powerdown pin allows external control of a powerdown
mode. The part is available in a 48-pin TQFP package.
FUNCTIONAL BLOCK DIAGRAM
RESET
SLEEP
IOUT
COMP
REFIN
FS ADJUST
REFOUT
AGND
AVDD
DGND
DVDD
MCLK
D0
FSELECT
D15
WR
A0
A1
A2
PSEL0
PSEL1
12
AD9831
ON-BOARD
REFERENCE
10-BIT DAC
PHASE0 REG
PHASE1 REG
PHASE2 REG
PHASE3 REG
TRANSFER CONTROL
MPU INTERFACE
FULL-SCALE
CONTROL
SIN
ROM
PHASE
ACCUMULATOR
(32-BIT)
MUX
FREQ0 REG
FREQ1 REG
MUX
PARALLEL REGISTER
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REV. A
­2­
AD9831­SPECIFICATIONS
1
Parameter
AD9831A
Units
Test Conditions/Comments
SIGNAL DAC SPECIFICATIONS
Resolution
10
Bits
Update Rate (f
MAX
)
25
MSPS nom
I
OUT
Full Scale
4
mA
nom
5
mA max
Output Compliance
1.5
V max
DC Accuracy
Integral Nonlinearity
±
1
LSB typ
Differential Nonlinearity
±
0.5
LSB typ
DDS SPECIFICATIONS
2
Dynamic Specifications
Signal to Noise Ratio
50
dB min
f
MCLK
= 25 MHz, f
OUT
= 1 MHz
Total Harmonic Distortion
­53
dBc max
f
MCLK
= 25 MHz, f
OUT
= 1 MHz
Spurious Free Dynamic Range (SFDR)
3
f
MCLK
= 6.25 MHz, f
OUT
= 2.11 MHz
Narrow Band (
±
50 kHz)
­72
dBc min
5 V Power Supply
­70
dBc min
3 V Power Supply
Wide Band (
±
2 MHz)
­50
dBc min
Clock Feedthrough
­60
dBc typ
Wake-Up Time
4
1
ms typ
Powerdown Option
Yes
VOLTAGE REFERENCE
Internal Reference @ +25
°
C
1.21
Volts typ
T
MIN
to T
MAX
1.21
±
7%
Volts min/max
REFIN Input Impedance
10
M
typ
Reference TC
100
ppm/
°
C typ
REFOUT Output Impedance
300
typ
LOGIC INPUTS
V
INH
, Input High Voltage
V
DD
­ 0.9
V
min
V
INL
, Input Low Voltage
0.9
V
max
I
INH
, Input Current
10
µ
A
max
C
IN
, Input Capacitance
10
pF
max
POWER SUPPLIES
AVDD
2.97/5.5
V
min/V
max
DVDD
2.97/5.5
V
min/V
max
I
AA
12
mA
max
5 V Power Supply
I
DD
2.5 + 0.33/MHz
mA typ
5 V Power Supply
I
AA
+ I
DD
5
15
mA
max
3 V Power Supply
24
mA
max
5 V Power Supply
Low Power Sleep Mode
6
1
mA max
1 M
Resistor Tied Between REFOUT and AGND
NOTES
1
Operating temperature range is as follows: A Version: ­40
°
C to +85
°
C.
2
100% production tested.
3
f
MCLK
= 6.25 MHz, Frequency Word = 5671C71C HEX, f
OUT
= 2.11 MHz.
4
See Figure 11. To reduce the wake-up time at low power supplies and low temperature, the use of an external reference is suggested.
5
Measured with the digital inputs static and equal to 0 V or DVDD.
6
The Low Power Sleep Mode current is typically 2 mA when a 1 M
resistor is not tied between REFOUT and AGND.
The AD9831 is tested with a capacitive load of 50 pF. The part can be operated with higher capacitive loads, but the magnitude of the analog output will be attenu-
ated. For example, a 5 MHz output signal will be attenuated by 3 dB when the load capacitance equals 85 pF.
Specifications subject to change without notice.
(V
DD
= +3.3 V
10%; +5 V 10%; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
; REFIN =
REFOUT; R
SET
= 3.9 k
; R
LOAD
= 300
for IOUT unless otherwise noted)
IOUT
COMP
REFIN
FS
ADJUST
REFOUT
12
AD9831
ON-BOARD
REFERENCE
10-BIT DAC
SIN
ROM
FULL-SCALE
CONTROL
300
50pF
R
SET
3.9k
10nF
10nF
AVDD
Figure 1. Test Circuit with Which Specifications Are Tested
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AD9831
­3­
REV. A
TIMING CHARACTERISTICS
(V
DD
= +3.3 V 10%, +5 V 10%; AGND = DGND = 0 V, unless otherwise noted)
Limit at
T
MIN
to T
MAX
Parameter
(A Version)
Units
Test Conditions/Comments
t
1
40
ns min
MCLK Period
t
2
16
ns min
MCLK High Duration
t
3
16
ns min
MCLK Low Duration
t
4
*
8
ns min
WR
Rising Edge to MCLK Rising Edge
t
4A
*
8
ns min
WR
Rising Edge After MCLK Rising Edge
t
5
8
ns min
WR
Pulse Width
t
6
t
1
ns min
Duration between Consecutive WR Pulses
t
7
5
ns min
Data/Address Setup Time
t
8
3
ns min
Data/Address Hold Time
t
9
*
8
ns min
FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge
t
9A
*
8
ns min
FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge
t
10
t
1
ns min
RESET
Pulse Duration
*See Pin Description section.
Guaranteed by design but not production tested.
t
1
t
4
MCLK
WR
t
2
t
3
t
4 A
t
6
t
5
Figure 2. Clock Synchronization Timing
A0, A1, A2
DATA
WR
t
8
t
5
t
7
t
6
VALID DATA
VALID DATA
Figure 3. Parallel Timing
VALID DATA
VALID DATA
VALID DATA
MCLK
FSELECT
PSEL0, PSEL1
RESET
t
9
t
1 0
t
9 A
Figure 4. Control Timing
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AD9831
­4­
REV. A
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Option*
AD9831AST
­ 40
°
C to +85
°
C
48-Pin TQFP ST-48
EVAL-AD9831EB Evaluation Board
*ST = Thin Quad Flatpack (TQFP).
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25
°
C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . ­0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . ­0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . ­0.3 V to +0.3 V
AGND to DGND. . . . . . . . . . . . . . . . . . . . . . ­0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . ­0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND . . . . . ­0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . ­40
°
C to +85
°
C
Storage Temperature Range . . . . . . . . . . . . ­65
°
C to +150
°
C
Maximum Junction Temperature . . . . . . . . . . . . . . . . +150
°
C
TQFP
JA
Thermal Impedance . . . . . . . . . . . . . . . . . 75
°
C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215
°
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220
°
C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 4500 V
*Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PIN CONFIGURATION
48 47 46 45 44
39 38 37
43 42 41 40
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
NC
AVDD
FS ADJUST
IOUT
NC
AGND
NC
COMP
AVDD
NC
AVDD
REFIN
AGND
RESET
A0
A1
A2
DB0
DB1
DGND
DB2
DB3
DB4
DVDD
AGND
REFOUT
SLEEP
DVDD
DVDD
DGND
MCLK
WR
DVDD
FSELECT
PSEL0
PSEL1
NC = NO CONNECT
DB9
DB11
DGND
DB15
DB14
DB13
DB12
DB10
DB8
DB7
DB6
DB5
AD9831
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AD9831
­5­
REV. A
PIN DESCRIPTION
Mnemonic
Function
POWER SUPPLY
AVDD
Positive power supply for the analog section. A 0.1
µ
F decoupling capacitor should be connected between AVDD
and AGND. AVDD can have a value of +5 V
±
10% or +3.3 V
±
10%.
AGND
Analog Ground.
DVDD
Positive power supply for the digital section. A 0.1
µ
F decoupling capacitor should be connected between DVDD
and DGND. DVDD can have a value of +5 V
±
10% or +3.3 V
±
10%.
DGND
Digital Ground.
ANALOG SIGNAL AND REFERENCE
IOUT
Current Output. This is a high impedance current source. A load resistor should be connected between IOUT
and AGND.
FS ADJUST
Full-Scale Adjust Control. A resistor (R
SET
) is connected between this pin and AGND. This determines the
magnitude of the full-scale DAC current. The relationship between R
SET
and the full-scale current is as follows:
IOUT
FULL-SCALE
= 12.5
×
V
REFIN
/R
SET
V
REFIN
= 1.21 V nominal, R
SET
= 3.9 k
typical
REFIN
Voltage Reference Input. The AD9831 can be used with either the on-board reference, which is available from pin
REFOUT, or an external reference. The reference to be used is connected to the REFIN pin. The AD9831
accepts a reference of 1.21 V nominal.
REFOUT
Voltage Reference Output. The AD9831 has an on-board reference of value 1.21 V nominal. The reference is
made available on the REFOUT pin. This reference is used as the reference to the DAC by connecting REFOUT
to REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND.
COMP
Compensation pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling ceramic
capacitor should be connected between COMP and AVDD.
DIGITAL INTERFACE AND CONTROL
MCLK
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The
output frequency accuracy and phase noise are determined by this clock.
FSELECT
Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase
accumulator. FSELECT is sampled on the rising MCLK edge. FSELECT needs to be in steady state when an
MCLK rising edge occurs. If FSELECT changes value when a rising edge occurs, there is an uncertainty of one
MCLK cycle as to when control is transferred to the other frequency register. To avoid any uncertainty, a change
on FSELECT should not coincide with an MCLK rising edge.
WR
Write, Edge-Triggered Digital Input. The WR pin is used when writing data to the AD9831. The data is loaded
into the AD9831 on the rising edge of the WR pulse. This data is then loaded into the destination register on the
MCLK rising edge. The WR pulse rising edge should not coincide with the MCLK rising edge as there will be an
uncertainty of one MCLK cycle regarding the loading of the destination register with the new data. The WR rising
edge should occur before an MCLK rising edge. The data will then be loaded into the destination register on the
MCLK rising edge. Alternatively, the WR rising edge can occur after the MCLK rising edge and the destination
register will be loaded on the next MCLK rising edge.
D0­D15
Data Bus, Digital Inputs for destination registers.
A0­A2
Address Digital Inputs. These address bits are used to select the destination register to which the digital data is to
be written.
PSEL0, PSEL1 Phase Select Input. The AD9831 has four phase registers. These registers can be used to alter the value being
input to the SIN ROM. The contents of the phase register can be added to the phase accumulator output, the
inputs PSEL0 and PSEL1 selecting the phase register to be used. Like the FSELECT input, PSEL0 and PSEL1
are sampled on the rising MCLK edge. Therefore, these inputs need to be in steady state when an MCLK rising
edge occurs or there is an uncertainty of one MCLK cycle as to when control is transferred to the selected phase
register.
SLEEP
Low Power Control, active low digital input. SLEEP puts the AD9831 into a low power mode. Internal clocks
are disabled and the DAC's current sources and REFOUT are turned off. The AD9831 is re-enabled by taking
SLEEP
high.
RESET
Reset, active low digital input. RESET resets the phase accumulator to zero which corresponds to an analog
output of midscale.
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AD9831
­6­
REV. A
±
2 MHz about the fundamental frequency. The narrow band
SFDR gives the attenuation of the largest spur or harmonic in a
bandwidth of
±
50 kHz about the fundamental frequency.
Clock Feedthrough
There will be feedthrough from the MCLK input to the analog
output. Clock feedthrough refers to the magnitude of the
MCLK signal relative to the fundamental frequency in the
AD9831's output spectrum.
Table I. Control Registers
Register
Size
Description
FREQ0 REG
32 Bits
Frequency Register 0. This de-
fines the output frequency, when
FSELECT = 0, as a fraction of the
MCLK frequency.
FREQ1 REG
32 Bits
Frequency Register 1. This de-
fines the output frequency, when
FSELECT = 1, as a fraction of the
MCLK frequency.
PHASE0 REG
12 Bits
Phase Offset Register 0. When
PSEL0 = PSEL1 = 0, the contents
of this register are added to the
output of the phase accumulator.
PHASE1 REG
12 Bits
Phase Offset Register 1. When
PSEL0 = 1 and PSEL1 = 0, the con-
tents of this register are added to
the output of the phase accumulator.
PHASE2 REG
12 Bits
Phase Offset Register 2. When
PSEL0 = 0 and PSEL1 = 1, the con-
tents of this register are added to
the output of the phase accumulator.
PHASE3 REG
12 Bits
Phase Offset Register 3. When
PSEL0 = PSEL1 = 1, the contents
of this register are added to the
output of the phase accumulator.
Table II. Addressing the Control Registers
A2
A1
A0
Destination Register
0
0
0
FREQ0 REG 16 LSBs
0
0
1
FREQ0 REG 16 MSBs
0
1
0
FREQ1 REG 16 LSBs
0
1
1
FREQ1 REG 16 MSBs
1
0
0
PHASE0 REG
1
0
1
PHASE1 REG
1
1
0
PHASE2 REG
1
1
1
PHASE3 REG
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale, a point 0.5
LSB below the first code transition (000 . . . 00 to 000 . . . 01)
and full scale, a point 0.5 LSB above the last code transition
(111 . . . 10 to 111 . . . 11). The error is expressed in LSBs.
Differential Nonlinearity
This is the difference between the measured and ideal 1 LSB
change between two adjacent codes in the DAC.
Signal to (Noise + Distortion)
Signal to (Noise + Distortion) is measured signal to noise at the
output of the DAC. The signal is the rms magnitude of the
fundamental. Noise is the rms sum of all the nonfundamental
signals up to half the sampling frequency (f
MCLK
/2) but exclud-
ing the dc component. Signal to (Noise + Distortion) is
dependent on the number of quantization levels used in the
digitization process; the more levels, the smaller the quantiza-
tion noise. The theoretical Signal to (Noise + Distortion) ratio
for a sine wave input is given by
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
where N is the number of bits. Thus, for an ideal 10-bit con-
verter, Signal to (Noise + Distortion) = 61.96 dB.
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the rms sum
of harmonics to the rms value of the fundamental. For the
AD9831, THD is defined as
THD
=
20 log
(V
2
2
+
V
3
2
+
V
4
2
+
V
5
2
+
V
6
2
V
1
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
, V
5
and V
6
are the rms amplitudes of the second through the
sixth harmonic.
Output Compliance
The output compliance refers to the maximum voltage which
can be generated at the output of the DAC to meet the specifi-
cations. When voltages greater than that specified for the
output compliance are generated, the AD9831 may not meet
the specifications listed in the data sheet.
Spurious Free Dynamic Range
Along with the frequency of interest, harmonics of the funda-
mental frequency and images of the MCLK frequency are
present at the output of a DDS device. The spurious free dy-
namic range (SFDR) refers to the largest spur or harmonic
which is present in the band of interest. The wide band SFDR
gives the magnitude of the largest harmonic or spur relative to
the magnitude of the fundamental frequency in the bandwidth
Table III. Frequency Register Bits
D15
D0
MSB
LSB
Table IV. Phase Register Bits
D15
D14
D13
D12
D11
D0
X
X
X
X
MSB
LSB
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­7­
REV. A
MCLK FREQUENCY ­ MHz
TOTAL CURRENT ­ mA
25
0
5
10
15
20
25
20
15
10
5
T
A
= +25
°
C
+5V
+3.3V
Figure 5. Typical Current Consumption vs. MCLK
Frequency
MCLK FREQUENCY ­ MHz
SFDR (
±
50kHz) ­ dB
­80
­75
10
15
20
25
­50
­55
­60
­65
­70
f
OUT
/f
MCLK
= 1/3
AVDD = DVDD = +3.3V
Figure 6. Narrow Band SFDR vs. MCLK Frequency
MCLK FREQUENCY ­ MHz
­65
25
10
SFDR (
±
2
M
Hz) ­ dB
15
20
­50
­55
­60
­40
­45
f
OUT
/f
MCLK
= 1/3
AVDD = DVDD = +3.3V
Figure 7. Wide Band SFDR vs. MCLK Frequency
f
OUT
/f
MCLK
­40
­45
­80
0
0.4
0.1
SFDR (
±
2
M
Hz) ­ dB
0.2
0.3
­60
­65
­70
­75
­50
­55
25MHz
10MHz
AVDD = DVDD = +3.3V
Figure 8. Wide Band SFDR vs. f
OUT
/f
MCLK
for Various
MCLK Frequencies
MCLK FREQUENCY ­ MHz
60
55
40
10
25
15
SNR ­ dB
20
50
45
AVDD = DVDD = +3.3V
f
OUT
= f
MCLK
/3
Figure 9. SNR vs. MCLK Frequency
f
OUT
/f
MCLK
60
55
40
0
0.4
0.1
SNR ­ dB
0.2
50
45
AVDD = DVDD = +3.3V
0.3
10MHz
25MHz
Figure 10. SNR vs. f
OUT
/f
MCLK
for Various MCLK
Frequencies
Typical Performance Characteristics­AD9831
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AD9831­Typical Performance Characteristics
­8­
REV. A
TEMPERATURE ­
°
C
10
7.5
0
­40
0
­30
WAKE-UP TIME ­ ms
­20
5.0
2.5
AVDD = DVDD = +2.97V
­10
Figure 11. Wake-Up Time vs. Temperature
0
­10
­100
­20
­30
­40
­50
­60
­70
­80
­90
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
10dB/DIV
VBW 1kHz
Figure 12. f
MCLK
= 25 MHz, f
OUT
= 1.1 MHz, Frequency
Word = B439581
0
­10
­100
­20
­30
­40
­50
­60
­70
­80
­90
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
10dB/DIV
VBW 1kHz
Figure 13. f
MCLK
= 25 MHz, f
OUT
= 2.1 MHz, Frequency
Word = 15810625
0
­10
­100
­20
­30
­40
­50
­60
­70
­80
­90
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
10dB/DIV
VBW 1kHz
Figure 14. f
MCLK
= 25 MHz, f
OUT
= 3.1 MHz, Frequency
Word = 1FBE76C9
0
­10
­100
­20
­30
­40
­50
­60
­70
­80
­90
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
10dB/DIV
VBW 1kHz
Figure 15. f
MCLK
= 25 MHz, f
OUT
= 4.1 MHz, Frequency
Word = 29FBE76D
0
­10
­100
­20
­30
­40
­50
­60
­70
­80
­90
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
10dB/DIV
VBW 1kHz
Figure 16. f
MCLK
= 25 MHz, f
OUT
= 5.1 MHz, Frequency
Word = 34395810
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AD9831
­9­
REV. A
0
­10
­100
­20
­30
­40
­50
­60
­70
­80
­90
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
10dB/DIV
VBW 1kHz
Figure 17. f
MCLK
= 25 MHz, f
OUT
= 6.1 MHz, Frequency
Word = 3E76C8B4
0
­10
­100
­20
­30
­40
­50
­60
­70
­80
­90
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
10dB/DIV
VBW 1kHz
Figure 18. f
MCLK
= 25 MHz, f
OUT
= 7.1 MHz, Frequency
Word = 48B43958
0
­10
­100
­20
­30
­40
­50
­60
­70
­80
­90
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
10dB/DIV
VBW 1kHz
Figure 19. f
MCLK
= 25 MHz, f
OUT
= 8.1 MHz, Frequency
Word = 52F1A9FC
0
­10
­100
­20
­30
­40
­50
­60
­70
­80
­90
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
10dB/DIV
VBW 1kHz
Figure 20. f
MCLK
= 25 MHz, f
OUT
= 9.1 MHz, Frequency
Word = 5D2F1AA0
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AD9831
­10­
REV. A
Numerical Controlled Oscillator + Phase Modulator
This consists of two frequency select registers, a phase accumu-
lator and four phase offset registers. The main component of the
NCO is a 32-bit phase accumulator which assembles the phase
component of the output signal. Continuous time signals have a
phase range of 0 to 2
. Outside this range of numbers, the
sinusoid functions repeat themselves in a periodic manner. The
digital implementation is no different. The accumulator simply
scales the range of phase numbers into a multibit digital word.
The phase accumulator in the AD9831 is implemented with 32
bits. Therefore, in the AD9831, 2
= 2
32
. Likewise, the
Phase
term is scaled into this range of numbers 0 <
Phase < 2
32
­ 1.
Making these substitutions into the equation above
f =
Phase
×
f
MCLK
/2
32
where 0 <
Phase < 2
32
With a clock signal of 25 MHz and a phase word of 051EB852
hex
f = 51EB852
×
25 MHz/2
32
= 0.500000000465 MHz
The input to the phase accumulator (i.e., the phase step) can be
selected either from the FREQ0 Register or FREQ1 Register
and this is controlled by the FSELECT pin. NCOs inherently
generate continuous phase signals, thus avoiding any output
discontinuity when switching between frequencies.
Following the NCO, a phase offset can be added to perform
phase modulation using the 12-bit PHASE Registers. The con-
tents of this register are added to the most significant bits of the
NCO. The AD9831 has four PHASE registers, the resolution
of these registers being 2
/4096.
Sine Look-Up Table (LUT)
To make the output useful, the signal must be converted from
phase information into a sinusoidal value. Since phase informa-
tion maps directly into amplitude, a ROM LUT converts the
phase information into amplitude. To do this, the digital phase
information is used to address a sine ROM LUT. Although the
NCO contains a 32-bit phase accumulator, the output of the
NCO is truncated to 12 bits. Using the full resolution of the
phase accumulator is impractical and unnecessary as this would
require a look-up table of 2
32
entries.
It is necessary only to have sufficient phase resolution in the
LUTs such that the dc error of the output waveform is domi-
nated by the quantization error in the DAC. This requires the
look-up table to have two more bits of phase resolution than the
10-bit DAC.
Digital-to-Analog Converter
The AD9831 includes a high impedance current source 10-bit
DAC, capable of driving a wide range of loads at different
speeds. Full-scale output current can be adjusted, for optimum
power and external load requirements, through the use of a
single external resistor (R
SET
).
The DAC is configured for single ended operation. The load
resistor can be any value required, as long as the full-scale volt-
age developed across it does not exceed the voltage compliance
range. Since full-scale current is controlled by R
SET
, adjust-
ments to R
SET
can balance changes made to the load resistor.
However, if the DAC full-scale output current is significantly
less than 4 mA, the DAC's linearity may degrade.
CIRCUIT DESCRIPTION
The AD9831 provides an exciting new level of integration for
the RF/Communications system designer. The AD9831 com-
bines the Numerical Controlled Oscillator (NCO), SINE Look-
Up Table, Frequency and Phase Modulators, and a Digital-to-
Analog Converter on a single integrated circuit.
The internal circuitry of the AD9831 consists of three main
sections. These are:
Numerical Controlled Oscillator (NCO) + Phase Modulator
SINE Look-Up Table
Digital-to-Analog Converter
The AD9831 is a fully integrated Direct Digital Synthesis
(DDS) chip. The chip requires one reference clock, one low
precision resistor and eight decoupling capacitors to provide
digitally created sine waves up to 12.5 MHz. In addition to the
generation of this RF signal, the chip is fully capable of a broad
range of simple and complex modulation schemes. These
modulation schemes are fully implemented in the digital domain
allowing accurate and simple realization of complex modulation
algorithms using DSP techniques.
THEORY OF OPERATION
Sine waves are typically thought of in terms of their magnitude
form a(t) = sin (
t). However, these are nonlinear and not easy
to generate except through piece wise construction. On the
other hand, the angular information is linear in nature. That is,
the phase angle rotates through a fixed angle for each unit of
time. The angular rate depends on the frequency of the signal
by the traditional rate of
= 2
f.
MAGNITUDE
PHASE
+1
0
­1
2
0
Figure 21. Sine Wave
Knowing that the phase of a sine wave is linear and given a
reference interval (clock period), the phase rotation for that
period can be determined.
Phase =
t
Solving for
=
Phase/
t = 2
f
Solving for f and substituting the reference clock frequency for
the reference period (1/f
MCLK
=
t)
f =
Phase
×
f
MCLK
/2
The AD9831 builds the output based on this simple equation.
A simple DDS chip can implement this equation with three
major subcircuits.
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AD9831
­11­
REV. A
MCLK cycle introduced otherwise. When these inputs change
value, there will be a pipeline delay before control is transferred
to the selected register--there will be a pipeline delay before the
analog output is controlled by the selected register. There is a
similar delay when a new word is written to a register. PSEL0,
PSEL1, FSELECT and WR have latencies of six MCLK cycles.
The flow chart in Figure 22 shows the operating routine for the
AD9831. When the AD9831 is powered up, the part should be
reset using RESET. This will reset the phase accumulator to
zero so that the analog output is at midscale. RESET does not
reset the phase and frequency registers. These registers will
contain invalid data and, therefore, should be set to zero by the
user.
The registers to be used should be loaded, the analog output
being f
MCLK
/2
32
×
FREG where FREG is the value loaded into
the selected frequency register. This signal will be phase shifted
by the amount specified in the selected phase register (2
/4096
×
PHASEREG where PHASEREG is the value contained in the
selected phase register). When FSELECT, PSEL0 and PSEL1
are programmed, there will be a pipeline delay of approximately
6 MCLK cycles before the analog output reacts to the change
on these inputs.
DATA WRITE
FREG<0, 1> = 0
PHASEREG<0, 1, 2, 3> = 0
DATA WRITE
FREG<0> = f
OUT0
/f
MCLK
*2
32
FREG<1> = f
OUT1
/f
MCLK
*2
32
SELECT DATA SOURCES
SET FSELECT
SET PSEL0, PSEL1
DAC OUTPUT
V
OUT
= V
REFIN
*6.25*R
OUT
/R
SET*
(1 + SIN(2
(FREG*f
MCLK
*t/2
32
+ PHASEREG/2
12
)))
WAIT 6 MCLK CYCLES
CHANGE PHASE?
CHANGE F
OUT
?
CHANGE FREG?
YES
CHANGE PHASEREG?
CHANGE PSEL0, PSEL1
YES
NO
NO
YES
NO
YES
NO
RESET
PHASEREG<3:0> = DELTA PHASE<0, 1, 2, 3>
CHANGE FSELECT
Figure 22. Flow Chart for AD9831 Initialization and Operation
DSP and MPU Interfacing
The AD9831 has a parallel interface, with 16 bits of data being
loaded during each write cycle.
The frequency or phase registers are loaded by asserting the WR
signal. The destination register for the 16 bit data is selected
using the address inputs A0, A1 and A2. The phase registers
are 12 bits wide so, only the 12 LSBs need to be valid--the
4 MSBs of the 16 bit word do not have to contain valid data.
Data is loaded into the AD9831 by pulsing WR low, the data
being latched into the AD9831 on the rising edge of WR. The
values of inputs A0, A1 and A2 are also latched into the
AD9831 on the WR rising edge. The appropriate destination
register is updated on the next MCLK rising edge. If the WR
rising edge coincides with the MCLK rising edge, there is an
uncertainty of one MCLK cycle regarding the loading of the
destination register--the destination register may be loaded
immediately or the destination register may be updated on the
next MCLK rising edge. To avoid any uncertainty, the times
listed in the specifications should be complied with.
FSELECT, PSEL0 and PSEL1 are sampled on the MCLK
rising edge. Again, these inputs should be valid when an
MCLK rising edge occurs as there will be an uncertainty of one
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AD9831
­12­
REV. A
APPLICATIONS
The AD9831 contains functions which make it suitable for
modulation applications. The part can be used to perform
simple modulation such as FSK. More complex modulation
schemes such as GMSK and QPSK can also be implemented
using the AD9831. In an FSK application, the two frequency
registers of the AD9831 are loaded with different values; one
frequency will represent the space frequency while the other will
represent the mark frequency. The digital data stream is fed to
the FSELECT pin which will cause the AD9831 to modulate
the carrier frequency between the two values.
The AD9831 has four phase registers; this enables the part to
perform PSK. With phase shift keying, the carrier frequency is
phase shifted, the phase being altered by an amount which is
related to the bit stream being input to the modulator. The
presence of four shift registers eases the interaction needed
between the DSP and the AD9831.
The frequency and phase registers can be written to continu-
ously, if required. The maximum update rate equals the
frequency of the MCLK. However, if a selected register is
loaded with a new word, there will be a delay of 6 MCLK cycles
before the analog output will change accordingly.
The AD9831 is also suitable for signal generator applications.
With its low current consumption, the part is suitable for appli-
cations in which it can be used as a local oscillator. In addition,
the part is fully specified for operation with a +3.3 V
±
10%
power supply. Therefore, in portable applications where current
consumption is an important issue, the AD9831 is perfect.
Grounding and Layout
The printed circuit board that houses the AD9831 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes which can be separated easily. A mini-
mum etch technique is generally best for ground planes as it
gives the best shielding. Digital and analog ground planes
should only be joined in one place. If the AD9831 is the only
device requiring an AGND to DGND connection, then the
ground planes should be connected at the AGND and DGND
pins of the AD9831. If the AD9831 is in a system where mul-
tiple devices require AGND to DGND connections, the
connection should be made at one point only, a star ground
point that should be established as close as possible to the
AD9831.
Avoid running digital lines under the device as these will couple
noise onto the die. The analog ground plane should be allowed
to run under the AD9831 to avoid noise coupling. The power
supply lines to the AD9831 should use as large a track as is
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching signals such
as clocks should be shielded with digital ground to avoid radiat-
ing noise to other sections of the board. Avoid crossover of
digital and analog signals. Traces on opposite sides of the board
should run at right angles to each other. This will reduce the
effects of feedthrough through the board. A microstrip tech-
nique is by far the best but is not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground planes while signals are placed
on the other side.
Good decoupling is important. The analog and digital supplies
to the AD9831 are independent and separately pinned out to
minimize coupling between analog and digital sections of the
device. All analog and digital supplies should be decoupled to
AGND and DGND respectively with 0.1
µ
F ceramic capacitors
in parallel with 10
µ
F tantalum capacitors. To achieve the best
from the decoupling capacitors, they should be placed as close
as possible to the device, ideally right up against the device. In
systems where a common supply is used to drive both the
AVDD and DVDD of the AD9831, it is recommended that the
system's AVDD supply be used. This supply should have the
recommended analog supply decoupling between the AVDD
pins of the AD9831 and AGND and the recommended digital
supply decoupling capacitors between the DVDD pins and
DGND.
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AD9831
­13­
REV. A
AD9831 Evaluation Board
The AD9831 Evaluation Board allows designers to evaluate the
high performance AD9831 DDS Modulator with a minimum of
effort.
To prove that this device will meet the user's waveform synthe-
sis requirements, the user only requires a 3.3 V or 5 V power
supply, an IBM-compatible PC and a spectrum analyzer along
with the evaluation board. The evaluation setup is shown
below.
The DDS Evaluation kit includes a populated, tested AD9831
printed circuit board along with the software which controls the
AD9831 in a Windows environment.
AD9831.EXE
IBM COMPATIBLE PC
PARALLEL PORT
CENTRONICS
PRINTER CABLE
AD9831
EVALUATION
BOARD
Figure 23. AD9831 Evaluation Board Setup
Using the AD9831 Evaluation Board
The AD9831 Evaluation kit is a test system designed to simplify
the evaluation of the AD9831. Provisions to control the
AD9831 from the printer port of an IBM-compatible PC are
included along with the necessary software. An application note
is also available with the evaluation board which gives informa-
tion on operating the evaluation board.
Prototyping Area
An area is available on the evaluation board where the user can
add additional circuits to the evaluation test set. Users may
want to build custom analog filters for the output or add buffers
and operational amplifiers which are to be used in the final
application.
XO vs. External Clock
The AD9831 can operate with master clocks up to 25 MHz. A
25 MHz oscillator is included on the evaluation board. How-
ever, this oscillator can be removed and an external CMOS
clock connected to the part, if required.
Power Supply
Power to the AD9831 Evaluation Board must be provided ex-
ternally through the pin connections. The power leads should
be twisted to reduce ground loops.
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AD9831
­14­
REV. A
C15
0.1µF
LATCH
DVDD
22
31
CK
V
DD
U3
74HC574
D7
D0
C14
0.1µF
LOAD
DVDD
14
21
D15
D8
CK
V
DD
U2
74HC574
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LATCH
D0
D1
D2
D3
D4
D5
D6
D7
LOAD
WR
RESET
WR
RESET
J1
PC
INTERFACE
D7
D0
LATCH
LOAD
32
34
R3
10k
R1
10k
R2
10k
WR
RESET
8
35
WR
RESET
12
11
10
7
3
PSEL1
FSELECT
MCLK
SLEEP
DVDD
SW
LK1
LK2
LK3
PSEL1
PSEL0
FSELECT
AVDD
DVDD
C10
10µF
C9
0.1µF
C11
0.1µF
C12
10µF
J2
J3
MCLK
DGND
AGND
6, 13, 29
1, 36, 46
MCLK
DVDD
LK4
COMP
REFIN
REFOUT
FSADJUST
IOUT
39
IOUT
R6
300
DVDD
4, 5, 9, 25
AVDD
38, 43, 47
C1, C2, C3
0.1µF
DVDD
C4, C5, C6
0.1µF
AVDD
AD9831
U4
AVDD
42
C7
10nF
C8
10nF
41
2
LK5
REFIN
R5
3.9k
40
XTAL1
A2
A0
PSEL0
C13
0.1µF
DVDD
U1
DVDD
DGND
OUT
R4
50
D7
D0
D15
D8
Figure 24. AD9831 Evaluation Board Layout
COMPONENT LIST
Integrated Circuits
XTAL1
OSC XTAL 25 MHz
U2, U3
74HC574 Latches
U4
AD9831 (48-Pin TQFP)
Capacitors
C1­C6
0.1
µ
F Ceramic Chip Capacitor
C7, C8
10 nF Ceramic Capacitor
C9, C11, C13­C15
0.1
µ
F Ceramic Capacitor
C10, C12
10
µ
F Tantalum Capacitor
Resistors
R1­R3
10 k
Resistor
R4
50
Resistor
R5
3.9 k
Resistor
R6
300
Resistor
Links
LK1­LK4
Three Pin Link
LK5
Two Pin Link
Switch
SW
End Stackable Switch (SDC
Double Throw)
Sockets
MCLK, PSEL0,
Sub-Miniature BNC Connector
PSEL1, FSELECT,
IOUT, REFIN
Connectors
J1
36-Pin Edge Connector
J2, J3
PCB Mounting Terminal Block
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AD9831
­15­
REV. A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Thin Quad Flatpack (TQFP)
ST-48
0.354 (9.00) BSC
0.276 (7.0) BSC
1
12
13
25
24
36
37
48
TOP VIEW
(PINS DOWN)
0.276 (7.0) BSC
0.354 (9.00) BSC
0.011 (0.27)
0.006 (0.17)
0.019 (0.5)
BSC
SEATING
PLANE
0.063 (1.60) MAX
0
°
MIN
0
°
­ 7
°
0.006 (0.15)
0.002 (0.05)
0.030 (0.75)
0.018 (0.45)
0.057 (1.45)
0.053 (1.35)
0.030 (0.75)
0.018 (0.45)
0.007 (0.18)
0.004 (0.09)
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C2171­12­9/96
PRINTED IN U.S.A.
­16­