FUNCTIONAL BLOCK DIAGRAM

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

AD9660

FEATURES
1.5 ns Rise/2.0 ns Fall Times
Output Current: 180 mA @ 3 V, 200 mA @ 2.5 V

Bias Current: 90 mA @ 3 V
Modulation Current: 60 mA @ 3 V
Offset Current: 30 mA @ 3 V

Single +5 V Power Supply
Switching Rate: 200 MHz
Onboard Light Power Control Loops

APPLICATIONS
Laser Printers and Copiers
Optical Disk Drives
FO Datacomm

GENERAL DESCRIPTION

The AD9660 is a highly integrated driver for laser diode appli-
cations such as optical disk drives, printers, and copiers. The
AD9660 gets feedback from an external photo detector and in-
cludes two analog feedback loops to allow users to set "bias"
and "write" (for optical disk drives) power levels of the laser,
and switch between the two power levels at up to 200 MHz.
Output rise and fall times are typically 1.5 ns and 2.0 ns to
complement printer applications that use image enhancing tech-
niques such as pulse width modulation to achieve gray scale,
and allow disk drive applications to improve density and take
advantage of pulsed write formats. Control signals are TTL/
CMOS compatible.

Š Analog Devices, Inc., 1995

One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700

Fax: 617/326-8703

200 MHz Laser Diode Driver

with Light Power Control

The driver output provides up to 180 mA of current @ 3 V,
90 mA of BIAS current, 60 mA of modulation current, and
30 mA of offset current. The onboard disable circuit turns off
the output drivers and returns the light power control loops to a
safe state.

The AD9660 can also be used in closed loop applications in
which the output power level follows an analog WRITE LEVEL
voltage input. By optimizing the external hold capacitor, and
the photo detector, the write loop can achieve bandwidths as
high as 25 MHz.

The AD9660 is offered in a 28-pin plastic SOIC for operation
over the commercial temperature range (0

C to +70

C).

TRANSIMPEDANCE

AMPLIFIER

OUTPUT

DRIVER

AD9660

LASER
DIODE

PHOTO

DETECTOR

DIODE

OUTPUT

SENSE

INPUT

WRITE
LEVEL

BIAS

LEVEL

BIAS

CAL

V:1

BIAS

T/H

V:1

T/H

OUTPUT

DRIVER

WRITE

PULSE

WRITE

CALIBRATE

Test

AD9660KR

Parameter

Level

Temp

Min

Typ

Max

Units

Conditions

ANALOG INPUTS
(WRITE LEVEL, BIAS LEVEL)

Input Voltage Range

Full

REF

+ 1.6

Input Bias Current

+25

+50

Analog Bandwidth

Full

MHz

External Hold Cap = 20 pF

OUTPUTS

Maximum Output Current, I

OUT

+25

200

OUT

= 2.5 V

OUT

+25

180

OUT

= 3.0 V

Bias Current, I

BIAS

+25

OUT

= 3.0 V

Modulation Current, I

MODULATION

+25

OUT

= 3.0 V

Offset Current, I

OFFSET

+25

OUT

= 3.0 V

Output Compliance Range

+25

3.0

Idle Current

+25

WRITE PULSE = LOW,
DISABLE = HIGH

SWITCHING PERFORMANCE

Maximum Pulse Rate

+25

200

250

MHz

3 dB Reduction in I

OUT

Output Propagation Delay (t

), Rising

Full

1.6

3.0

Output Propagation Delay (t

), Falling

Full

1.6

2.5

Output Current Rise Time

Full

1.1

1.5

1.7

Output Current Fall Time

Full

1.4

2.0

2.8

WRITE CAL Aperture Delay

+25

Disable Time

+25

HOLD NODES
(WRITE HOLD, BIAS HOLD)

Input Bias Current

+25

200

HOLD

= 2.5 V

Input Voltage Range

Full

REF

+ 1.6

Open Loop Application Only

Minimum External Hold Cap

Full

TTL INPUTS

Logic "1" Voltage

+25

2.0

DISABLE = LOW

Logic "1" Voltage

Full

2.0

While Other

Logic "0" Voltage

+25

0.8

TTL Inputs Are

Logic "0" Voltage

Full

0.8

Tested

Logic "1" Current

+25

Logic "0" Current

+25

1.5

BANDGAP REFERENCE

Output Voltage V

REF

+25

1.55

1.75

1.90

Temperature Coefficient

0.2

mV/

Output Current

+25

0.5

1.0

SENSE IN

Current Gain

+25

1.85

mA/mA

Voltage

+25

3.7

4.0

4.3

MONITOR

= 2 mA

Input Resistance

+25

<150

POWER SUPPLY (DISABLE = HIGH)

Voltage

+25

4.75

5.00

5.25

DISABLE = HIGH

Current

+25

110

150

Power Dissipation

+25

550

OFFSET CURRENT

OFFSET SET Voltage

+25

1.1

1.4

1.7

MONITOR

= 4.0 mA

NOTES

Propagation delay measured from the 50% of the rising/falling transition of WRITE PULSE to 50% point of the rising/falling edge of the output modulation current.

Rise time measured between the 10% and 90% points of the rising transition of the modulation current.

Fall time measured between the 10% and 90% points of the falling transition of the modulation current.

Aperture Delay is measured from the 50% point of the rising edge of WRITE PULSE to the time when the output modulation begins to recalibrate, WRITE CAL is

held during this test.

Disable Time is measured from the 50% point of the rising edge of DISABLE to the 50% point of the falling transition of the output current. Fall time during disable

is similar to fall time during normal operation.

WRITE PULSE, WRITE CAL, BIAS CAL, OFFSET PULSE are TTL compatible inputs.

Specifications subject to change without notice.

AD9660SPECIFICATIONS

REV. 0

(+V

= +5 V, Temperature = +25

C unless otherwise noted. Sourced currents defined

as positive.)

AD9660

REV. 0

ABSOLUTE MAXIMUM RATINGS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V

REF

Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA

WRITE LEVEL, BIAS LEVEL . . . . . . . . . . . . . 0.5 V to +V

TTL INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to +V

Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 mA
Operating Temperature

AD9660KR . . . . . . . . . . . . . . . . . . . . . . . . . . 0

C to +70

Storage Temperature . . . . . . . . . . . . . . . . . . 65

C to +150

Maximum Junction Temperature

. . . . . . . . . . . . . . . . +150

Lead Soldering Temp (10 sec) . . . . . . . . . . . . . . . . . . . +300

Absolute maximum ratings are limiting values, to be applied individually, and

beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure of
absolute maximum rating conditions for extended periods of time may affect
device reliability.

Typical thermal impedance is

= 45

C/W,

= 41

C/W.

EXPLANATION OF TEST LEVELS
Test Level

100% Production Tested.

II.

100% production tested at +25

C, and sample tested at

specified temperatures. AC testing done on sample basis.

III. Sample Tested Only.

IV. Parameter is guaranteed by design and characterization

testing.

Parameter is a typical value only.

VI. All devices are 100% production tested at +25

C, sample

tested at temperature extremes.

100

450

1250

BANDGAP

REF

1mA

SENSE

T/H

WRITE

HOLD

BIAS

HOLD

OUTPUT

OFFSET

SET

TTL

INPUT

Equivalent Circuits

WARNING!

ESD SENSITIVE DEVICE

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9660 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

PIN ASSIGNMENTS

WRITE CAL

WRITE PULSE

WRITE LEVEL

REF

WRITE HOLD

GROUND

SENSE IN

GAIN

POWER MONITOR

GROUND

BIAS HOLD

BIAS LEVEL

GROUND

OFFSET SET

OFFSET PULSE

OUTPUT

BIAS CAL

GROUND

OUTPUT

DISABLE

TOP VIEW

(Not to Scale)

AD9660KR

ORDERING GUIDE

Model

Temperature Range

Package Option

AD9660KR

C to +70

R-28

AD9660KR-REEL

C to +70

R-28 (1000/reel)

REV. 0

AD9660

PIN DESCRIPTIONS

Pin

Function

OUTPUT

Analog laser diode current output. Connect to anode of laser diode, cathode connected to GROUND externally.

BIAS LEVEL

Analog voltage input, V

REF

to V

REF

+ 1.6 V. Bias current is set proportional to the BIAS LEVEL during calibra-

tion as follows:

MONITOR

BIAS LEVEL

REF

1.85

GAIN

(

)

BIAS CAL

TTL/CMOS compatible, Bias loop T/H control signal. Logic HIGH enables calibration mode, and the bias loop
T/H immediately goes into track mode. Logic LOW disables the bias loop T/H and immediately places it in hold
mode. WRITE PULSE should be held logic LOW while calibrating. Floats logic HIGH.

BIAS HOLD

External hold capacitor for the bias loop T/H. Approximate droop in the bias current while BIAS CAL is logic

LOW is:

BIAS

BIAS HOLD

. Bandwidth of the loop is:

(550

) C

BIAS HOLD

WRITE PULSE

TTL/CMOS compatible, current control signal. Logic HIGH supplies I

MODULATION

to the laser diode. Logic

LOW turns I

MODULATION

off. Floats logic HIGH.

WRITE CAL

TTL/CMOS compatible, write loop T/H control signal. Logic HIGH enables calibration mode; before enabling
calibration the bias loop should be calibrated and OFFSET PULSE driven to an appropriate state. In calibration
mode, 13 ns after the WRITE PULSE goes logic HIGH, the write loop T/H goes into track mode (there is no de-
lay if WRITE PULSE is HIGH before WRITE CAL transitions to a HIGH level). The write loop T/H immedi-
ately goes into hold mode when the WRITE PULSE goes Logic LOW. WRITE CAL LOW disables the write
loop T/H and places it in hold mode. Floats logic HIGH.

WRITE LEVEL

Analog voltage input, V

REF

to V

REF

+1.6 V. Write current is set proportional to the input voltage during calibra-

tion as follows:

MONITOR

WRITE LEVEL

REF

1.85

( R

GAIN

)

WRITE HOLD

External hold capacitor for the write loop T/H. Approximate droop in I

MODULATION

current while WRITE CAL is

logic LOW is:

MODULATED

WRITE HOLD

. Bandwidth of the loop is:

(550

) C

BIAS HOLD

SENSE IN

Analog current input, I

MONITOR

, from PIN photo detector diode. SENSE IN should be connected to the cathode

of the PIN diode, with the PIN anode connected to GROUND or a negative voltage. Voltage at SENSE IN var-
ies slightly with temperature and current, but is typically 4.0 V.

GAIN

External connection for the feedback network of the transimpedance amplifier. External feedback network, R

GAIN

and C

GAIN

, should be connected between GAIN and POWER MONITOR. See text for choosing values.

POWER

Output voltage monitor of the internal feedback loop. Voltage is proportional to feedback current from photo

MONITOR

diode.

OFFSET

Set resistor connection for the offset current source. Resistor between OFFSET CURRENT SET and +V

CURRENT SET determines offset current level. The input voltage at this node varies slightly with temperature and current, but is

typically 1.4 V. See curves. Can also be driven with a current out DAC.

OFFSET

TTL/CMOS compatible, OFFSET current control signal. Logic HIGH adds I

OFFSET

to I

OUT

. Logic LOW

PULSE

turns off I

OFFSET

. Floats logic HIGH.

DISABLE

TTL/CMOS compatible, current output disable circuit. Logic LOW for normal operation; logic HIGH disables
the current outputs to the laser diode, and drives the voltage on the hold capacitors close to V

REF

(minimizes the

output current when the device is re-enabled). DISABLE floats logic HIGH.

REF

Analog Voltage Output, internal bandgap voltage reference, ~1.75 V, provided to user for power level offset.

Positive Power Supply. Nominally +5 V, pin connections should be tied together externally.

GROUND

Ground Reference. All grounds should be tied together externally.

REV. 0

Typical Performance CharacteristicsAD9660

2ns

20mV

6.25mV

193.8mV

120V

ML64116R

OUTPUT

TEK 11802

O'SCOPE

AD9660

ANTEL

ARS1

PHOTO DETECTOR

Figure 1. Driving ML64116R Laser @ 30 mW

OFFSET

 k

OFFSET

Figure 2. I

OFFSET

vs. R

OFFSET

DELAY

VOLT

REF

OUTPUT

LASER
DIODE

PHOTO
DETECTOR

WRITE LOOP

WRITE HOLD

WRITE PULSE

WRITE CAL

GAIN

BIAS LEVEL

BIAS CAL

BIAS HOLD

OFFSET PULSE

ANALOG

REF

5pF

ANALOG

TTL

REF

OUT

4.0V

1:10

V:1

TZA

2* I

MONITOR

1.85:1

MODULATION

GAIN

POWER

MONITOR

DISABLE

CIRCUIT

WRITE LEVEL

GAIN

OUT

MONITOR

SENSE IN

V:1

ANALOG

1:10

REF

TTL

1:10

BIAS

OFFSET

1.4V

OFFSET CURRENT

SET

BIAS LOOP

AD9660

10ns DELAY ON RISING

EDGE; 0ns ON FALLING

TTL

5pF

Figure 3. Functional Block Diagram

THEORY OF OPERATION

The AD9660 combines a very fast output current switch with
onboard analog light power control loops to provide the user
with a complete laser diode driver solution. The block diagram
illustrates the key internal functions. The control loops of the
AD9660, the bias loop and the write loop, adjust the output
current level, I

OUT

, so that the photo diode feedback current,

MONITOR

, out of SENSE IN is proportional to the analog input

voltage at BIAS LEVEL or WRITE LEVEL. Since the monitor

current is proportional to the laser diode light power, the loops
effectively control laser power to a level proportional to the ana-
log inputs. The control loops should be periodically calibrated
independently (see Choosing C

BIAS HOLD

and C

WRITE HOLD

The offset current generator produces an open loop output cur-
rent, I

OFFSET

. Its level is controlled by an external set resistor or

a current out DAC (see Figure 2). While I

OFFSET

is not cali-

brated as the currents from the bias and write loops are, it can
be very versatile (see Offset Current below).

REV. 0

AD9660

RECALIBRATE THE BIAS LOOP

POWER-UP

OR LASER

NOT IN USE

BIAS

CAL

TIME

WRITE

LOOP

CAL

TIME

RECALIBRATE WRITE LOOP

LASER POWER

MODULATED

BETWEEN

BIAS AND WRITE LEVELS

DISABLE

BIAS CAL

WRITE CAL

WRITE PULSE

LASER

OUTPUT POWER

CALIBRATED WRITE

CALIBRATED BIAS

WRITE LOOP

HOLD TIME

Figure 4. Normal Operating Mode

The disable circuit turns off I

OUT

and returns the hold capacitor

voltages to their minimum levels (minimum output current)
when DISABLE = logic HIGH. It is used during initial power-
up of the AD9660 or during time periods when the laser is inac-
tive. When the AD9660 is re-enabled the control loops must be
recalibrated.

Normal operation of the AD9660 involves (in order, see figure):

1. The AD9660 is enabled (DISABLE = logic LOW).

2. The input voltages (BIAS LEVEL and WRITE LEVEL) are

driven to the appropriate levels to set the calibrated laser di-
ode output power levels.

3. The bias loop is closed for calibration (BIAS CAL = logic

HIGH), and then opened (BIAS CAL = logic LOW).

4. The write loop is closed for calibration (WRITE PULSE and

WRITE CAL = logic HIGH) and then opened.

5. While both loops are open, the laser is pulsed between the

two calibrated levels by WRITE PULSE.

6. The bias and write loops are periodically recalibrated as

needed.

7. The AD9660 is disabled when the laser will not be pulsed for

an indefinite period of time.

Control Loop Transfer Functions

The relationship between I

MONITOR

and V

BIAS LEVEL

MONITOR

BIAS LEVEL

REF

1.85

( R

GAIN

)

once the bias loop is calibrated. When the bias loop is open
(BIAS CAL = logic LOW), its output current, I

BIAS

, is propor-

tional to the held voltage at BIAS HOLD; the external hold ca-
pacitor on this pin determines the droop error in the output bias
current between calibrations.

The relationship between I

MONITOR

and V

WRITE LEVEL

MONITOR

WRITE LEVEL

REF

1.85

( R

GAIN

)

once the write loop is calibrated. The current supplied by the write
loop output is referred to as the modulation current, I

MODULATION

When the write loop is open (WRITE CAL logic LOW),
I

MODULATION

is proportional to the held voltage at WRITE HOLD.

The external hold capacitor (WRITE HOLD) determines the
droop error between calibrations. I

MODULATION

may be switched

on and off by WRITE PULSE when the write loop is open.

120

100

OPTICAL OUTPUT mW

CONSTANT WRITE POWER

BIAS CALIBRATION POWER

C CASE

CASE

C CASE

BIAS

MOD

FORWARD CURRENT mA

Figure 5. Typical Laser Diode Current-to-Optical
Power Curve

The sections below discuss choosing the external components in
the feedback loops for a particular application.

Choosing R

GAIN

The gain resistor, R

GAIN

, allows the user to match the feedback

loop's transfer function to the laser diode/photo diode
combination.

The user should define the maximum laser diode output power
for the intended application, P

LD MAX

, and the corresponding

photo diode monitor current, I

MONITOR MAX

. A typical laser di-

ode transfer function is illustrated in Figure 5. R

GAIN

should be

chosen as:

GAIN

1.6 V

1.85

MONITOR MAX

The laser diode's output power will then vary from 0 to P

MAX

for an input range of V

REF

to V

REF

+1.6 V @ the BIAS LEVEL

and WRITE LEVEL inputs.

AD9660

REV. 0

Choosing C

BIAS HOLD

and C

WRITE HOLD

Choosing values for the hold capacitors, C

WRITE

and C

HOLD

, is a

tradeoff between output current droop when the control loops
are open, and the time it takes to calibrate and recalibrate the
laser power when the loops are closed.

The amount of output current droop is determined by the value
of the hold capacitor and the leakage current at that node.
When either of the two control loops are open (WRITE CAL or
BIAS CAL logic LOW), the pin connections for the hold
capacitors (WRITE HOLD and BIAS HOLD) are high imped-
ance inputs. Leakage currents will range from

200 nA; this

low current minimizes the droop in the output power level. As-
suming the worst case current of

200 nA, the output current

will change as follows:

BIAS

BIAS HOLD

MODULATED

WRITE HOLD

To choose a value, the user will need to determine the amount
of time the loop will be in hold mode, t

WRITE HOLD

or t

BIAS HOLD

the maximum change in laser output power the application can
tolerate, and the laser efficiency (defined as the change in laser
output power to the change in laser diode current). As an ex-
ample, if an application requires 5 mW of laser power

5%, and

the laser diode efficiency is 0.25 mW/mA, then

MAX

5 mW

(5% ) / 0. 25

1. 0 mA

If the same application had a hold time requirement of 250

then the minimum value of the hold capacitor would be:

HOLD

250

1.0 mA

4.5 nF

When determining the calibration time, the T/H and the exter-
nal hold capacitor can be modeled using the simple RC circuit
illustrated in Figure 7.

HOLD

AD9660

TZA

T/H

WRITE LEVEL

OR BIAS LEVEL

POWER MONITOR

WRITE HOLD
OR BIAS HOLD

EXTERNAL HOLD
CAPACITOR

Figure 7. Circuit Model for Determining Calibration Times

Minimum specifications for I

MONITOR MAX

should be used when

choosing R

GAIN

. Users are cautioned that laser diode/photo di-

ode combinations that produce monitor currents that are less
than I

MONITOR MAX

in the equation above will produce higher la-

ser output power than predicted, which may damage the laser
diode. Such a condition is possible if R

GAIN

is calculated using

typical instead of minimum monitor current specifications. In
that case the input range to the AD9660 BIAS LEVEL and
WRITE LEVEL inputs should be limited to avoid damaging
laser diodes.

Although not recommended, another approach would be to
use a potentiometer for R

GAIN

. This allows users to optimize

the value of R

GAIN

for each laser diode/photo diode combina-

tion's monitor current. The drawback to this approach is that
potentiometer's stray inductance and capacitance may cause the
transimpedance amplifier to overshoot and degrade its settling,
and the value of C

GAIN

may not be optimized for the entire

potentiometer's range.

GAIN

optimizes the response of the transimpedance amplifier

and should be chosen as from the table below. Choosing C

GAIN

larger than the recommended value will slow the response of the
amplifier. Lower values improve TZA bandwidth but may cause
the amplifier to oscillate.

Table I.

Recommended

GAIN

2.5 k

2 pF

1.5 k

3 pF

1 k

4 pF

500

8 pF

The circuit in Figure 6 allows an adjustable gain with low vari-
ance in bandwidth, but requires several external components.

REF

INTERNAL

GAIN

POWER

MONITOR

REF

R3
1.7k

2I PIN

1:2

MONITOR

SENSE

AD9660

EQUIVALENT

CIRCUIT

REF

INTERNAL

+ 50

= (R

+ 50

)

(1+ + )

R2
R1

R1
R

Figure 6. Adjustable Gain Configuration

REV. 0

AD9660

Initial calibration is required after power-up or any other time
the laser has been disabled. Disabling the AD9660 drives the
hold capacitors back down to V

REF

. In this case, or in any case

where the output current is more than 10% out of calibration, R
will range from 300

to 550

for the model above; the higher

value should be used for calculating the worst case calibration
time. Following the example above, if C

HOLD

were chosen as

4.5 nF, then

= RC = 550

4.5 nF would be 2.5

s. For an

initial calibration error <1%, the initial calibration time should
be >5

= 12.4

Initial calibration time will actually be better than this calcula-
tion indicates, as a significant portion of the calibration time will
be within 10% of the final value, and the output resistance in
the AD9660's T/H decreases as the hold voltage approaches its
final value.

Recalibration is functionally identical to initial calibration, but
the loop need only correct for droop. Because droop is assumed
to be a small percentage of the initial calibration (<10%), the
resistance for the model above will be in the range of 75

140

. Again, the higher value should be used to estimate the

worst case time needed for recalibration.

Continuing with the example above, since the error during hold
time was chosen as 5%, we meet the criteria for recalibration
and

= RC = 140

4.5 nF = 0.63

s. To get a final error of

1% after recalibration, the 5% droop must be corrected to
within a 20% error (20%

5% = 1%). A 2

recalibration time

of 1.26

s is sufficient.

Continuous Recalibration

In applications where the hold capacitor is small (<500 pF) and
the WRITE PULSE signals always have a pulse width >25 ns,
the user may continuously calibrate the write loop. In such an
application, the WRITE CAL signal should be held logic
HIGH, and the WRITE PULSE signal will control write loop
calibration via the internal AND gate.

The bias loop may be continuously recalibrated whenever
WRITE PULSE is logic LOW.

Using this model, the voltage at the hold capacitor is

HOLD

( V

) 1

where t

is when the calibration begins (WRITE CAL or BIAS

CAL goes logic HIGH), V

t = 0

is the voltage on the hold cap at

t = 0, V

t =

is the steady state voltage at the hold cap with the

loop closed, and

= R

CHOLD

is the time constant. With this

model the error in V

CHOLD

for a finite calibration time, as com-

pared to V

t =

, can be estimated from the following table and

chart:

Table II.

CALIBRATION

% Final Value

Error %

99.9

0.09

99.7

0.25

99.2

0.79

98.1

1.83

95.0

4.97

86.5

13.5

63.2

36.8

CALIBRATION TIME Time Constants =

100

% FINAL VALUE % of Volts

Figure 8. Calibration Time Curve

AD9660

REV. 0

Example Calculations

The example below (in addition to the one included in the sec-
tions above) should guide users in choosing R

GAIN

, C

GAIN

, the

hold capacitor values, and worst case calibration times.

System Requirements:

Bias laser power: 4 mW Bias

Write laser power: 25 mW

0.5%

Bias Hold Time: 1 ms

Write Hold Time: 1

Laser diode/photo diode characteristics:

Laser efficiency 0.5 mA/mA

Monitor current: 5

A/mA

From the laser power requirements and efficiency we can

estimate:

BIAS MAX

4 mW

(5% ) / 0. 5

400. 0

and

WRITE MAX

25 mW

0. 5%

(

)

/ 0. 5

250

Choosing hold caps based on these:

BIAS HOLD

1 ms

400

0.045

and

WRITE HOLD

250

72 pF

The bias loop initial calibration time for a <1% error:

= 5

RC = 5

550

0.045

F = 123.75

Bias loop recalibration for a 1% error after 5% droop (need to

correct within 20%):
2

= 2

RC = 2

140

0.045

F = 12.6

The write loop initial calibration time for <0.1% error:

= 7

RC = 7

550

72 pF = 277.2 ns

Write loop re-calibration for a 0.1% error after 0.5% droop

(need to correct within 20%):
2

= RC = 2

140

72 pF = 20.2 ns

From the monitor current specification and the max power

specified:

MONITOR MAX

25 mW

125

and

GAIN

1.6 V

1.85

MONITOR MAX

6.9 k

GAIN

would be chosen as 2 pF (see Table I).

Driving the Analog Inputs

The BIAS LEVEL and WRITE LEVEL inputs of the AD9660
drive the track and hold amplifiers and allow the user to adjust
the amount of output current as described above. The input
voltage range on both inputs is V

REF

to V

REF

+ 1.6 V, requiring

the user to create an offset of V

REF

for a ground based signal.

The circuit in Figure 9 will perform the level shift and scale the
output of a DAC whose output is from ground to a positive
voltage. This solution is attractive because both the DAC and
the op amp can run off a single +5 V supply, and the op amp
doesn't have to swing rail to rail.

DAC1

DAC2

DAC1

DAC2

OP291

+5V

REF

DAC1

= V

BIAS LEVEL

R2
R1

REF

DAC2

= V

WRITE LEVEL

R4
R3

BIAS LEVEL

REF

WRITE LEVEL

AD9660

Figure 9. Driving the Analog Inputs

REV. 0

AD9660

Offset Current Generator

The offset current source allows the user to inject a fixed,
uncalibrated current into the laser diode. The offset current
source is set by an external resistor connected between OFF-
SET CURRENT SET and +V

, and is controlled by OFFSET

PULSE. See Figure 2 for a transfer function of the offset cur-
rent source.

The offset current may be used to increase the output current
provided by the bias and/or write loops after calibration. Alter-
natively, the offset current may be added during the calibration
of the bias loop and switched off after calibration to drop the
bias current below the knee of the laser diode power curve.
This is illustrated in Figure 10.

120

OPTICAL OUTPUT mW

100

CONSTANT WRITE POWER

BIAS CALIBRATION POWER

C CASE

CASE

C CASE

BIAS

OFFSET

WITH OFFSET CURRENT TURNED OFF,

BIAS CURRENT IS BELOW THE KNEE OF THE LASER DIODE

OFFSET CURRENT TURNED ON DURING BIAS-CAL

MOD

BIAS

FORWARD CURRENT mA

OPERATING
BIAS LEVEL

Figure 10. Laser Diode Current-to-Optical Power Curve
Illustrating Bias Below Diode Knee

AD9660 Layout Considerations

As in all high speed applications, proper layout is critical; it is
particularly important when both analog and digital signals are
involved. Analog signal paths should be kept as short as pos-
sible, and isolated from digital signals to avoid coupling in noise.
In particular, digital lines should be isolated from OUTPUT,
PIN SENSE, WRITE LEVEL, and BIAS LEVEL traces. Digi-
tal signal paths should also be kept short, and run lengths
matched to avoid propagation delay mismatch.

Layout of the ground and power supply circuits is also critical.
A single, low impedance ground plane will reduce noise on the
circuit ground. Power supplies should be capacitively coupled
to the ground plane to reduce noise in the circuit. 0.1

F sur-

face mount capacitors, placed as close as possible to the
AD9660 +V

connections meet this requirement. Multilayer

circuit boards allow designers to lay out signal traces without
interrupting the ground plane, and provide low impedance
power planes to further reduce noise.

Minimizing the Impedance of the Output Current Path

Because of the very high current slew that the AD9660 is
capable of producing (70+ mA in 1.5 ns), the inductance of the
output current path to and from the laser diode is critical. A
good layout of the output current path will yield high quality
light pulses with rise times of about 1.5 ns and less than 5%
overshoot. A poor layout can result in significant overshoot and
ringing. The most important guideline for the layout is to mini-
mize the impedance (mostly inductance) of the output current
path to the laser. It is important to recognize that the laser cur-
rent path is a closed loop. The figure illustrates the path that
current travels: (1) from the output pins of the AD9660 to the
anode of the laser, (2) through the laser to the cathode
(ground), (3) through the return path, (4) through the 0.1

bypass capacitors back to the +V

pins of the AD9660 where (5)

the current travels through the output driver circuitry of the
AD9660, and back to the output pins. The inductance of this
loop can be minimized by placing the laser as close to the
AD9660 as possible to keep the loop short, and by placing the
send and return paths on adjacent layers of the PC board to take
advantage of mutual coupling of the path inductances. This
mutual coupling effect is the most important factor in reducing
inductance in the current path.

AD9660

REV. 0

The trace from the output pins of the AD9660 to the anode of
the laser (send trace) should be several millimeters wide and
should be as direct as possible. The return current will choose
the path of least resistance. If the return path is the ground
plane, it should have an unbroken path, under the output trace,
from the laser cathode back to the AD9660. If the return path is
not the ground plane (such as on a two layer board, or on the
+V

plane), it should still be on the board plane adjacent to the

plane of the output trace. If the current cannot return along a
path that follows the output trace, the inductance will be drasti-
cally increased and performance will be degraded.

Optimizing the Feedback Layout

In applications where the dynamic performance of the analog
feedback loop is important, it is necessary to optimize the layout
of the gain resistor, R

GAIN

, as well as the monitor current path to

SENSE IN. Such applications include MOD systems which
recalibrate the write loop on pulses as short as 25 ns, and closed
loop applications.

The best possible TZA settling will be achieved by using a
single carbon surface mount resistor (usually 5% tolerance) for
R

GAIN

and small surface mount capacitor for C

GAIN

. Because the

GAIN pin (Pin 9) is essentially connected to the inverting input
of the TZA, it is very sensitive to stray capacitance. R

GAIN

should be placed between Pin 9 and Pin 10, as close as possible
to Pin 9. Small traces should be used, and the ground and +V

planes adjacent to the trace should be removed to further mini-
mize stray capacitance.

The trace from SENSE IN to the cathode of the PIN photo-
detector should be thin and routed away from the laser anode
trace.

GROUND PLANE

BYPASS CAPS

GROUND PIN

CONNECTIONS

OUTPUT PIN CONNECTIONS

PIN ASSIGNMENTS

PIN CONNECTIONS

MUTUAL COUPLING

REDUCES INDUCTANCE

LASER DIODE CURRENT

PATH SEGMENTS

(SEE TEXT)

AD9660

Figure 11. Laser Diode Current Loop

Part Number AD9660