/home/web/htmldatasheet/RUSSIAN/html/ad/164431

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

AD9410

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 2000

10-Bit, 210 MSPS

A/D Converter

FUNCTIONAL BLOCK DIAGRAM

T/H

ENCODE

ADC

10-BIT

CORE

TIMING AND

SYNCHRONIZATION

PORT

DFS

I/P

REF

OUT

REFERENCE

DGND V

AGND

D0

DCO

D0

DCO

AD9410

PORT

FEATURES
SNR = 54 dB with 99 MHz Analog Input
500 MHz Analog Bandwidth
On-Chip Reference and Track/Hold
1.5 V p-p Differential Analog Input Range
5.0 V and 3.3 V Supply Operation
3.3 V CMOS/TTL Outputs
Power: 2.1 W Typical at 210 MSPS
Demultiplexed Outputs Each at 105 MSPS
Output Data Format Option
Data Sync Input and Data Clock Output Provided
Interleaved or Parallel Data Output Option

APPLICATIONS
Communications and Radar
Local Multipoint Distribution Service (LMDS)
High-End Imaging Systems and Projectors
Cable Reverse Path
Point-to-Point Radio Link

GENERAL DESCRIPTION

The AD9410 is a 10-bit monolithic sampling analog-to-digital
converter with an on-chip track-and-hold circuit and is opti-
mized for high-speed conversion and ease of use. The product
operates at a 210 MSPS conversion rate, with outstanding
dynamic performance over its full operating range.

The ADC requires a 5.0 V and 3.3 V power supply and up to a
210 MHz differential clock input for full performance operation.
No external reference or driver components are required for many
applications. The digital outputs are TTL/CMOS-compatible,
and separate output power supply pins also support interfacing
with 3.3 V logic.

The clock input is differential and TTL/CMOS-compatible. The
10-bit digital outputs can be operated from 3.3 V (2.5 V to 3.6 V)
supplies. Two output buses support demultiplexed data up to
105 MSPS rates, and binary or two's complement output coding
format is available. A data sync function is provided for timing-
dependent applications. An output clock simplifies interfacing to
external logic. The output data bus timing is selectable for parallel
or interleaved mode, allowing for flexibility in latching output data.

Fabricated on an advanced BiCMOS process, the AD9410
is available in an 80-lead surface-mount plastic package
(PowerQuad

2) specified over the industrial temperature range

(40

°C to +85°C).

PowerQuad is a registered trademark of Amkor Electronics, Inc.

PRODUCT HIGHLIGHTS

High Resolution at High Speed--The architecture is specifically
designed to support conversion up to 210 MSPS with outstand-
ing dynamic performance.

Demultiplexed Output--Output data is decimated by two and
provided on two data ports for ease of data transport.

Output Data Clock--The AD9410 provides an output data
clock synchronous with the output data, simplifying the timing
between data and other logic.

Data Synchronization--A DS input is provided to allow for
synchronization of two or more AD9410s in a system, or
to synchronize data to a specific output port in a single
AD9410 system.

REV. 0

AD9410SPECIFICATIONS

DC SPECIFICATIONS

Test

Parameter

Temp

Level

Min

Typ

Max

Unit

RESOLUTION

Bits

DC ACCURACY

No Missing Codes

Full

Guaranteed

Differential Nonlinearity

°C

1.0

±0.5

+1.25

LSB

Full

1.0

+1.5

LSB

Integral Nonlinearity

°C

2.5

±1.65

+2.5

LSB

Full

3.0

+3.0

LSB

Gain Error

°C

6.0

+6.0

% FS

Gain Tempco

Full

130

ppm/

°C

ANALOG INPUT

Input Voltage Range (With Respect to

AIN)

Full

±768

mV p-p

Common-Mode Voltage

Full

3.0

Input Offset Voltage

°C

+15

Full

+20

Reference Voltage

Full

2.4

2.5

2.6

Reference Tempco

Full

ppm/

°C

Input Resistance

Full

610

875

1250

Input Capacitance

°C

Analog Bandwidth, Full Power

°C

500

MHz

POWER SUPPLY

Power Dissipation AC

°C

2.1

Power Dissipation DC

Full

2.0

2.4

VCC

Full

128

145

Full

401

480

Power Supply Rejection Ratio PSRR

°C

7.5

+0.5

+7.5

mV/V

NOTES

Package heat slug should be attached when operating at greater than 70

°C ambient temperature.

Encode = 210 MSPS, A

= 0.5 dBFS 10 MHz sine wave, I

VDD

= 31 mA typical at C

LOAD

= 5 pF.

Encode = 210 MSPS, A

= dc, outputs not switching.

Specifications subject to change without notice.

SWITCHING SPECIFICATIONS

Test

Parameter

Temp

Level

Min

Typ

Max

Unit

SWITCHING PERFORMANCE

Maximum Conversion Rate

Full

210

MSPS

Minimum Conversion Rate

Full

100

MSPS

Encode Pulsewidth High (t

)

°C

1.2

2.4

Encode Pulsewidth Low (t

)

°C

1.2

2.4

Aperture Delay (t

)

°C

1.0

Aperture Uncertainty (Jitter)

°C

0.65

ps rms

Output Valid Time (t

)

Full

3.0

Output Propagation Delay (t

)

Full

7.4

Output Rise Time (t

)

°C

1.8

Output Fall Time (t

)

°C

1.4

CLKOUT Propagation Delay

CPD

)

Full

2.6

4.8

6.4

Data to DCO Skew (t

CPD

)

Full

DS Setup Time (t

SDS

)

Full

0.5

DS Hold Time (t

HDS

)

Full

Interleaved Mode (A, B Latency)

Full

A = 6, B = 6

Cycles

Parallel Mode (A, B Latency)

Full

A = 7, B = 6

Cycles

NOTES

LOAD

= 5 pF.

Specifications subject to change without notice.

= 3.3 V, V

= 5.0 V; 2.5 V external reference; A

= 0.5 dBFS; Clock

input = 210 MSPS; T

= 25 C; unless otherwise noted.)

= 3.3 V, V

= 5.0 V; 2.5 V external reference; A

= 0.5 dBFS; Clock input = 210 MSPS;

= 25 C; unless otherwise noted.)

REV. 0

AD9410

DIGITAL SPECIFICATIONS

Test

Parameter

Temp

Level

Min

Typ

Max

Unit

DIGITAL INPUTS

DFS, Input Logic "1" Voltage

Full

DFS, Input Logic "0" Voltage

Full

DFS, Input Logic "1" Current

Full

µA

DFS, Input Logic "0" Current

Full

µA

I/P Input Logic "1" Current

Full

400

µA

I/P Input Logic "0" Current

Full

µA

ENCODE,

ENCODE Differential Input Voltage

Full

0.4

ENCODE,

ENCODE Differential Input Resistance

Full

1.6

ENCODE,

ENCODE Common-Mode Input Voltage

Full

1.5

DS,

DS Differential Input Voltage

Full

0.4

DS,

DS Common-Mode Input Voltage

Full

1.5

Digital Input Pin Capacitance

°C

DIGITAL OUTPUTS

Logic "1" Voltage (V

= 3.3 V)

Full

0.05

Logic "0" Voltage (V

= 3.3 V)

Full

0.05

Output Coding

Binary or Two's Complement

NOTES

I/P pin Logic "1" = 5 V, Logic "0" = GND. It is recommended to place a series 2.5 k

(±10%) resistor to V

when setting to Logic "1" to limit input current.

See Encode Input section in Applications section.

Specifications subject to change without notice.

AC SPECIFICATIONS

Test

Parameter

Temp

Level

Min

Typ

Max

Unit

DYNAMIC PERFORMANCE

Transient Response

°C

Overvoltage Recovery Time

°C

Signal-to-Noise Ratio (SNR)

(Without Harmonics)
f

= 10.3 MHz

°C

52.5

= 82 MHz

°C

= 160 MHz

°C

Signal-to-Noise Ratio (SINAD)

(With Harmonics)
f

= 10.3 MHz

°C

= 82 MHz

°C

= 160 MHz

°C

Effective Number of Bits

= 10.3 MHz

°C

8.3

8.8

Bits

= 82 MHz

°C

8.1

8.6

Bits

= 160 MHz

°C

8.4

Bits

Second Harmonic Distortion

= 10.3 MHz

°C

dBc

= 82 MHz

°C

dBc

= 160 MHz

°C

dBc

Third Harmonic Distortion

= 10.3 MHz

°C

dBc

= 82 MHz

°C

dBc

= 160 MHz

°C

dBc

Spurious Free Dynamic Range (SFDR)

= 10.3 MHz

°C

dBc

= 82 MHz

°C

dBc

= 160 MHz

°C

dBc

Two-Tone Intermod Distortion IMD

IN1

= 80.3 MHz, f

IN2

= 81.3 MHz

°C

dBFS

NOTES

IN1, IN2 level = 7 dBFS.

Specifications subject to change without notice.

= 3.3 V, V

= 5.0 V; 2.5 V external reference; A

= 0.5 dBFS;

Clock input = 210 MSPS; T

= 25 C; unless otherwise noted.)

= 3.3 V, V

= 5.0 V; 2.5 V external reference; A

= 0.5 dBFS; Clock input = 210 MSPS;

= 25 C; unless otherwise noted.)

REV. 0

AD9410

ORDERING GUIDE

Temperature

Package

Model

Range

Description

Option

AD9410BSQ

°C to +85°C

PowerQuad 2

SQ-80

AD9410/PCB

°C

Evaluation Board

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9410 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

EXPLANATION OF TEST LEVELS
Test Level

100% production tested.

II.

100% production tested at 25

°C and sample tested at

specified temperatures.

III. Sample tested only.

IV. Parameter is guaranteed by design and characterization

testing.

Parameter is a typical value only.

VI. 100% production tested at 25

°C; guaranteed by design and

characterization testing for industrial temperature range.

ABSOLUTE MAXIMUM RATINGS

, V

CC,

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V

Analog Inputs . . . . . . . . . . . . . . . . . . . . . 0 V to V

+ 0.5 V

Digital Inputs . . . . . . . . . . . . . . . . . . . . . 0 V to V

+ 0.5 V

VREF IN . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to V

+ 0.5 V

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . 55

°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . 65

°C to +150°C

Maximum Junction Temperature

. . . . . . . . . . . . . . . . 150

°C

NOTES

Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability. Stresses
above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions outside of those indicated in the operation sections
of this specification is not implied.

Typical

= 22

°C/W (heat slug not soldered), typical

= 16

°C/W (heat slug

soldered), for multilayer board in still air with solid ground plane.

REV. 0

AD9410

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

Function

1, 2, 8, 9, 12, 13, 16, 17, 20, 21, 24,

AGND

Analog Ground.

27, 28, 29, 30, 71, 72, 73, 74, 77, 78

3, 7, 14, 15

5 V Supply. (Regulate to within

±5%.)

REF

OUT

Internal Reference Output.

REF

Internal Reference Input.

DNC

Do Not Connect.

Analog Input--True.

AIN

Analog Input--Complement.

ENCODE

Clock Input--True.

ENCODE

Clock Input--Complement.

Data Sync (Input)--True. Tie LOW if not used.

Data Sync (Input)--Complement. Float and decouple with 0.1

µF

capacitor if not used.

25, 26, 31, 32, 69, 70, 75, 76

3.3 V Analog Supply. (Regulate to within

±5%.)

33, 40, 49, 52, 59, 68

DGND

Digital Ground.

34, 41, 48, 53, 60, 67

3.3 V Digital Output Supply. (2.5 V to 3.6 V)

3539

Digital Data Output for Channel B. (LSB = D

4246

Digital Data Output for Channel B. (MSB = D

Data Overrange for Channel B.

DCO

Clock Output--Complement.

DCO

Clock Output--True.

5458

Digital Data Output for Channel A. (LSB = D

6165

Digital Data Output for Channel A. (MSB = D

Data Overrange for Channel A.

DFS

Data Format Select. HIGH = Two's Complement, LOW = Binary.

I/P

Interleaved or Parallel Output Mode. Low = Parallel Mode, High =
Interleaved Mode. If tying high, use a current limiting series resistor
(2.5 k

) to the 5 V supply.

REV. 0

AD9410

PIN CONFIGURATION

PIN 1
IDENTIFIER

TOP VIEW

80-Lead PowerQuad2

(Not to Scale)

AD9410

AGND

REF

OUT

REF

DNC

AGND

ENCODE

AGND

DGND

(LSB) D

DGND

(MSB)

DGND

DCO

DGND

(LSB)

DGND

(MSB)

DGND

AGND

DFS

I/P

DNC

DO NOT CONNECT

REV. 0

AD9410

DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth

The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.

Aperture Delay

The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog
input is sampled.

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance

The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capaci-
tance and differential input impedances are measured with a
network analyzer.

Differential Analog Input Voltage Range

The peak-to-peak differential voltage that must be applied to the
converter to generate a full-scale response. Peak differential voltage
is computed by observing the voltage on a single pin and subtract-
ing the voltage from the other pin, which is 180 degrees out of
phase. Peak-to-peak differential is computed by rotating the
inputs phase 180 degrees and taking the peak measurement
again. The difference is then computed between both peak
measurements.

Differential Nonlinearity

The deviation of any code width from an ideal 1 LSB step.

Effective Number of Bits

The effective number of bits (ENOB) is calculated from the
measured SINAD based on the equation.

ENOB

SINAD

Full Scale Amplitude

Input Amplitude

MEASURED

log

1 76

6 02

Encode Pulsewidth/Duty Cycle

Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic 1 state to achieve
rated performance; pulsewidth low is the minimum time
ENCODE pulse should be left in low state. See timing implica-
tions of changing t

ENCH

in text. At a given clock rate, these specs

define an acceptable ENCODE duty cycle.

Full-Scale Input Power

Expressed in dBm. Computed using the following equation:

POWER

FULL SCALE

INPUT

rms

0 001

log

Harmonic Distortion, Second

The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.

Harmonic Distortion, Third

The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.

Integral Nonlinearity

The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a "best straight line"
determined by a least-square curve fit.

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog
signal frequency drops by no more than 3 dB below the
guaranteed limit.

Maximum Conversion Rate

The encode rate at which parametric testing is performed.

Output Propagation Delay

The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.

Out-of-Range Recovery Time

Out-of-range recovery time is the time it takes for the ADC to
reacquire the analog input after a transient from 10% above
positive full scale to 10% above negative full scale, or from 10%
below negative full scale to 10% below positive full scale.

Noise (For Any Range Within the ADC)

NOISE

SIGNAL

dBm

dBFS

| |

0 001 10

Where Z is the input impedance, FS is the full scale of the device
for the frequency in question, SNR is the value for the particular
input level, and SIGNAL is the signal level within the ADC
reported in dB below full scale. This value includes both thermal
and quantization noise.

Power Supply Rejection Ratio

The ratio of a change in input offset voltage to a change in
power supply voltage.

Signal-to-Noise-and-Distortion (SINAD)

The ratio of the rms signal amplitude (set 0.5 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics, but excluding dc.

Signal-to-Noise Ratio (Without Harmonics)

The ratio of the rms signal amplitude (set at 0.5 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.

Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered), or dBFS (always
related back to converter full scale).

Transient Response Time

Transient response time is defined as the time it takes for the
ADC to reacquire the analog input after a transient from 10%
above negative full scale to 10% below positive full scale.

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.

Two-Tone SFDR

The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).

Worst Other Spur

The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic) reported in dBc.

REV. 0

AD9410

1.5k

2.25k

1.5k

2.25k

Figure 2. Equivalent Analog Input Circuit

VREFIN

Figure 3. Equivalent Reference Input Circuit

17k

ENCODE

100

ENCODE

450

Figure 4 Equivalent Encode Input Circuit

DIGITAL

OUTPUT

Figure 5. Equivalent Digital Output Circuit

Table I. Output Coding (V

REF

= 2.5 V)

Digital Outputs

Step

Offset Binary

Two's Complement

, OR

> 0.768

11 1111 1111

01 1111 1111

1023

0.768

11 1111 1111

01 1111 1111

513

0.0015

10 0000 0001

00 0000 0001

512

0.0

10 0000 0000

00 0000 0000

511

0.0015

01 1111 1111

11 1111 1111

0.768

00 0000 0000

10 0000 0000

< 0.768

00 0000 0000

10 0000 0000

VREFOUT

Figure 6. Equivalent Reference Output Circuit

100k

DFS

Figure 7. Equivalent DFS Input Circuit

7.5k

300

17.5k

300

Figure 8. Equivalent DS Input Circuit

7.5k

I/P

300

17.5k

Figure 9. Equivalent I/P Input Circuit

REV. 0

AD9410

MHz

20

40

60

80

100

120

105

ENCODE = 210MSPS
A

= 40MHz @ 0.5dBFS

SNR = 54.5dB
SINAD = 53.5dB

TPC 1. Single Tone at 40 MHz, Encode = 210 MSPS

MHz

20

40

60

80

100

120

105

ENCODE = 210MSPS
A

= 100MHz @ 0.5dBFS

SNR = 53.5dB
SINAD = 52.5dB

TPC 2. Single Tone at 100 MHz, Encode = 210 MSPS

MHz

20

40

60

80

100

120

105

ENCODE = 210MSPS
A

= 160MHz @ 0.5dBFS

SNR = 53dB
SINAD = 52dB

TPC 3. Single Tone at 160 MHz, Encode = 210 MSPS

Typical Performance Characteristics

 MHz

100

150

200

250

SNR

SINAD

TPC 4. SNR/SINAD vs. A

Encode = 210 MSPS

MHz

53.0

100

dB 52.5

52.0

51.5

51.0

50.5

50.0

120

140

160

200

240

54.0

55.0

SNR

SINAD

53.5

54.5

180

220

TPC 5. SNR/SINAD vs. F

= 70 MHz

0.5

1.0

1.5

2.5

4.0

2.0

3.5

3.0

SINAD

SNR

TPC 6. SNR/SINAD vs. Encode Positive Pulsewidth
(F

= 210 MSPS, A

= 70 MHz)

REV. 0

AD9410

MHz

20

40

60

80

100

120

105

ENCODE = 210MSPS
A

1, A

2 = 7dBFS

SFDR = 62dBFS

TPC 7. Two Tone Test A

1 = 80.3 MHz, A

2 = 81.3 MHz

TEMPERATURE C

54.5

40

54.0

53.5

53.0

52.5

52.0

51.5

20

100

120

55.0

55.5

SNR

SINAD

TPC 8. SNR/SINAD vs. Temperature,
Encode = 210 MSPS, A

= 70 MHz

TEMPERATURE C

40

20

100

120

TPC 9. Second and Third Harmonics vs. Temperature;
A

= 70 MHz, Encode = 210 MSPS

ANALOG SUPPLY

2.48

4.0

VOLTS

2.47

2.46

4.2

4.4

4.6

5.0

5.6

2.51

2.52

2.50

4.8

5.4

2.49

5.2

TPC 10. VREF

OUT

vs. Analog 5 V Supply

MSPS

110

100

120

140

160

200

260

310

210

180

160

220

360

410

460

IAhi3

IAhi5

Ivdd

TPC 11. Power Supply Currents vs. Encode

2.35

VOLTS

2.30

2.25

0.5

1.0

2.0

1.5

2.40

2.5

2.45

2.50

2.55

TPC 12. VREF

OUT

vs. I

LOAD

REV. 0

AD9410

APPLICATION NOTES

THEORY OF OPERATION

The AD9410 architecture is optimized for high speed and ease
of use. The analog inputs drive an integrated high bandwidth
track-and-hold circuit that samples the signal prior to quantiza-
tion by the flash 10-bit core. For ease of use the part includes
an onboard reference and input logic that accepts TTL, CMOS,
or PECL levels.

USING THE AD9410
ENCODE Input

Any high-speed A/D converter is extremely sensitive to the
quality of the sampling clock provided by the user. A Track/Hold
circuit is essentially a mixer, and any noise, distortion, or timing
jitter on the clock will be combined with the desired signal at the
A/D output. For that reason, considerable care has been taken
in the design of the ENCODE input of the AD9410, and the
user is advised to give commensurate thought to the clock source.
To limit SNR degradation to less than 1 dB, a clock source with
less than 1.25 ps rms jitter is required for sampling at Nyquist.
(Valpey Fisher VF561 is an example.) Note that required jitter
accuracy is a function of input frequency and amplitude. Consult
Analog Devices' application note AN-501, "Aperture Uncer-
tainty and ADC System Performance," for more information.

The ENCODE input is fully TTL/CMOS-compatible. The
clock input can be driven differentially or with a single-ended
signal. Best performance will be obtained when driving the clock
differentially. Both ENCODE inputs are self-biased to 1/3

× V

by a high impedance resistor divider. (See Equivalent Circuits
section.) Single-ended clocking, which may be appropriate for
lower frequency or nondemanding applications, is accomplished
by driving the ENCODE input directly and placing a 0.1

µF

capacitor at

ENCODE.

0.1 F

ENCODE

AD9410

TTL/CMOS

GATE

Figure 10. Driving Single-Ended Encode Input at
TTL/CMOS Levels

An example where the clock is obtained from a PECL driver is
shown in Figure 11. Note that the PECL driver is ac-coupled to
the ENCODE inputs to minimize input current loading. The
AD9410 can be dc-coupled to PECL logic levels resulting in the
ENCODE input currents increasing to approximately 8 mA
typically. This is due to the difference in dc bias between the
ENCODE inputs and a PECL driver. (See Equivalent Cir-
cuits section.)

PECL

GATE

GND

510

0.1 F

ENCODE

AD9410

Figure 11. Driving the Encode Inputs Differentially

Analog Input

The analog input to the AD9410 is a differential buffer. For
best dynamic performance, impedances at A

and

AIN should

match. The analog input has been optimized to provide superior
wideband performance and requires that the analog inputs be
driven differentially. SNR and SINAD performance will degrade
significantly if the analog input is driven with a single-ended
signal. A wideband transformer such as Minicircuits ADT1-1WT
can be used to provide the differential analog inputs for applica-
tions that require a single-ended-to-differential conversion. Both
analog inputs are self-biased by an on-chip resistor divider to a
nominal 3 V. (See Equivalent Circuits section.)

Special care was taken in the design of the Analog Input section
of the AD9410 to prevent damage and corruption of data when the
input is overdriven. The nominal input range is 1.5 V diff p-p.

The nominal differential input range is 768 mV p-p

× 2.

2.616

VOLTS

3.384

3.000

Figure 12. Typical Analog Input Levels

Digital Outputs

The digital outputs are TTL/CMOS-compatible for lower power
consumption. The outputs are biased from a separate supply
(V

), allowing easy interface to external logic. The outputs are

CMOS devices which will swing from ground to V

(with no

dc load). It is recommended to minimize the capacitive load the
ADC drives by keeping the output traces short (<1 inch, for a
total C

LOAD

< 5 pF). It is also recommended to place low value

(20

) series damping resistors on the data lines to reduce switch-

ing transient effects on performance.

Clock Outputs (DCO,

DCO)

The input ENCODE is divided by two and available off-chip at
DCO and

DCO. These clocks can facilitate latching off-chip,

providing a low skew clocking solution (see timing diagram).
These clocks can also be used in multiple AD9410 systems to
synchronize the ADCs. Depending on application, DCO or
DCO can be buffered and used to drive the DS inputs on a
second AD9410, ensuring synchronization. The on-chip clock
buffers should not drive more than 5 pF7 pF of capacitance to
limit switching transient effects on performance.

Voltage Reference

A stable and accurate 2.5 V voltage reference is built into the
AD9410 (VREF OUT). The input range can be adjusted by
varying the reference voltage. No appreciable degradation in
performance occurs when the reference is adjusted

±5%. The full-

scale range of the ADC tracks reference voltage changes linearly
within the

±5% tolerance.

REV. 0

AD9410

Timing

The AD9410 provides latched data outputs, with six pipeline
delays in interleaved mode (see Figure 1). In parallel mode, the
A Port has one additional cycle of latency added on-chip to line
up transitions at the data ports--resulting in a latency of seven
cycles for the A Port. The length of the output data lines and
loads placed on them should be minimized to reduce transients
within the AD9410; these transients can detract from the
converter's dynamic performance.

The minimum guaranteed conversion rate of the AD9410 is
100 MSPS. At internal clock rates below 100 MSPS, dynamic
performance may degrade. Note that lower effective sampling
rates can be obtained simply by sampling just one output port--
decimating the output by two. Lower sampling frequencies can
also be accommodated by restricting the duty cycle of the clock
such that the clock high pulsewidth is a maximum of 5 ns.

EVALUATION BOARD

The AD9410 evaluation board offers an easy way to test the
AD9410. The board requires an analog input, clock, and 3 V,
5 V power supplies. The digital outputs and output clocks are
available at a standard 80-lead header P2, P3. The board has
several different modes of operation, and is shipped in the fol-
lowing configuration:

Output Timing = Parallel Mode

Output Format = Offset Binary

Internal Voltage Reference

Power Connector

Power is supplied to the board via detachable 4-pin power strips
P1, P4, P5.

VDAC Optional DAC Supply Input (3.3 V)
EXT REF Optional External VREF Input (2.5 V)
V

Logic Supply (3.3 V)

3.3 VA Analog Supply (3.3 V)
5 V Analog Supply (5 V)

Analog Inputs

The evaluation board accepts a 1.5 V p-p analog input signal
centered at ground at SMB J8. This input is terminated to 50

on the board at the transformer secondary, but can be termi-
nated at the SMB if an alternative termination is desired. The
input is ac-coupled prior to the transformer. The transformer is
band limited to frequencies between approximately 1 MHz and
400 MHz.

Encode

The encode input to the board is at SMB connector J1. The
input is terminated on the board with 50

to ground. The

(>0.5 V p-p) input is ac-coupled and drives a high-speed
differential line receiver (MC10EL16). This receiver provides
sub- nanosecond rise times at its outputs--a requirement for
the ADC clock inputs for optimum performance. The EL16
outputs are PECL levels and are ac-coupled to meet the common-
mode dc levels at the AD9410 encode inputs.

REFERENCE

The AD9410 has an on-chip reference of 2.5 V available at
REF

OUT

(Pin 4). Most applications will simply tie this output

to the REF

input (Pin 5). This is accomplished by placing a

jumper at E1, E6. An external reference can be used placing a
jumper at E1, E3.

Output Timing

The chip has two timing modes (see timing diagram). Inter-
leaved mode is selected by Jumper E11, E7. Parallel mode is
selected by Jumper E11, E14.

Data Format Select

Data Format Select sets the output data format that the ADC
outputs. Setting DFS (Pin 79) low at E12, E10 sets the output
format to be offset binary; setting DFS high at E12, E16 sets the
output to be two's complement.

DS Pin

The DS,

DS inputs are available at SMB connectors J9X and

J10X. The board is shipped with DS pulled to ground by R26.
DS is floating (R25X is not placed).

DAC Outputs

Each channel is reconstructed by an on-board dual channel
DAC, an AD9751 to assist in debug. The performance of the
DAC has not been optimized and will not give an accurate
measure of the full performance of the ADC. It is a current
output DAC with on-board 50

termination resistors. The

outputs are available at J3 and J4.

Data Sync (DS)

The Data Sync input, DS, can be used in applications requir-
ing that a given sample will appear at a specific output Port A or
B. When DS is held high, the ADC data outputs and clock do not
switch and are held static. Synchronization is accomplished by the
assertion (falling edge) of DS, within the timing constraints
T

SDS

and T

HDS

relative to an encode rising edge. (On initial

synchronization T

HDS

is not relevant.) If DS falls within the

required setup time (T

SDS

) before a given encode rising edge N,

the analog value at that point in time will be digitized and avail-
able at Port B six cycles later (interleaved mode). The very next
sample, N+1, will be sampled by the next rising encode edge and
available at Port A six cycles after that encode edge (interleaved
mode). In dual parallel mode the A Port has a seven cycle latency,
the B Port has a six cycle latency, but data is available at the
same time.

REV. 0

AD9410

DAOR

DA7

DA8

DA5

GND

DA6

DA9

C14

0.1 F

GND

3.3VA

GND

C11

0.1 F

3.3VA

C10

0.1 F

GND

3.3VA

GND

100

GND

E14

R24

100

R7
100

GND

E12

E16

R4
2.5k

E10

GND

100

VDD

E11

DBOR

GND

DCOC

DCOT

GND

DB9

DB6

DB7

DA0

DA1

DA2

DA3

DA4

GND

VDD

DB8

VDD

C21
0.1 F

GND

DGND

DCO

DGND

C12
0.1 F

GND

C22
0.1 F

GND

VDD

C18
0.1 F

DB5

GND

DB0

DB1

DB2

DB4

GND

VDD

C19

0.1 F

3.3VA

GND

C15

0.1 F

GND

3.3VA

C16

0.1 F

GND

3.3VA

GND

R25X
50

GND

R26
50

J9X

J10X

AGND

DGND

GND

ENCT

ENCC

GND

C27

0.1 F

EXT

REF

C26
0.1 F

GND

R27
50

1 : 1

GND

AIN

0.1 F

GND

C25
0.1 F

GND

R23

GND

C24
0.1 F

GND

AD9410

GND

C28
0.1 F

VBB

VCC

VEE

R14
8.2k

R9
24k

R19

8.2k

R18

24k

0.1 F

GND

C40
0.1 F

GND

R15
330

GND

R11
330

ENCT

ENCC

0.1 F

GND

MC10EL16

GND GND

GND

VDD/3.3V

GND

3.3VA

GND

VDAC

GND

EXT REF

GND

C4
10 F

3.3VA

VDD

EXT REF

VDAC

C5
10 F

C3
10 F

C2
10 F

C1
10 F

DGND

AGND

DFS

I/P

AGND

REF

OUT

REF

DNC

AGND

ENCODE

AGND

NOTE:
R3, R6, R7, R24 OPTIONAL
(CAN BE ZERO )

DB3

Figure 13a. PCB Schematic

REV. 0

AD9410

GND

DRB

GND

DN9

DN8

DN7

DN6

DN5

DN4

DN3

DN1

DN2

DN0

GND

HEADER 40

GND

DRA

GND

DM9

DM8

DM7

DM6

DM5

DM4

DM3

DM1

DM2

DM0

GND

HEADER 40

R38

DN7

DN6

DN5

DN4

DN3

DN2

DN1

DN0

D7B

D6B

D5B

D4B

D3B

D2B

D1B

D0B

RPACK

R28

DN9

DN8

RPACK

D9B

D8B

R36

DM2

DM1

DM0

RPACK

D2A

D1A

D0A

R34

DM9

DM8

DM7

DM6

DM5

DM4

DM3

D9A

D8A

D7A

D6A

D5A

D4A

D3A

RPACK

D9B

D8B

D7B

D6B

D5B

D4B

D3B

D2B

D1B

CLKB

D0B

GND

DY9

DY8

DY7

DY6

DY5

DY4

DY3

DY2

DY1

GND

DY0

VCC

CLK

GND

C39

0.1

74LCXB21

GND

VDD

D9A

D8A

D7A

D6A

D5A

D4A

D3A

D2A

D1A

CLKA

D0A

VCC

CLK

GND

C37

0.1

74LCXB21

GND

DX9

DX8

DX7

DX6

DX5

DX4

DX3

DX2

DX1

GND

DX0

R39

DY7

DY6

DY5

DY4

DY3

DY2

DY1

DY0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

RPACK

R29

DYOR

DY9

DY8

DBOR

DB9

DB8

RPACK

R40

DX2

DX1

DX0

DA2

DA1

DA0

RPACK

R32

DXOR

DX9

DX8

DX7

DX6

DX4

DX3

RPACK

DAOR

DA9

DA8

DA7

DA6

DA4

DA3

DA5

DX5

DRA

R44

74AC86

DCOTA

XORA

VDD

E24

GND

E18

E17

100

XORA

VDD

E26

GND

E28

E27

R37

100

XORB

CLKA

74AC86

DCOTA

XORB

VDD

E23

GND

E22

E25

R43

100

XORD

CLKB

DCOTA

XORD

74AC86

VDD

E20

GND

E21

E19

R42

100

XORC

DRB

R45

74AC86

DCOCA

XORC

VDD

GND

C32

0.1

DCOT

DCOTA

R16

DCOC

DCOCA

R17

Figure 13b. PCB Schematic (Continued)

REV. 0

AD9410

TROUBLESHOOTING

If the board does not seem to be working correctly, try the
following:

Verify power at IC pins.

Check that all jumpers are in the correct position for the
desired mode of operation.

Verify VREF is at 2.5 V.

· Try running encode clock and analog input at low speeds

(10 MSPS/1 MHz) and monitor latch outputs, DAC outputs,
and ADC outputs for toggling.

The AD9410 Evaluation Board is provided as a design example
for customers of Analog Devices, Inc. ADI makes no warranties,
express, statutory, or implied, regarding merchantability or
fitness for a particular purpose.

AD9751

E34

GND

E33

DCOCA

DCOTA

GND

C13
0.1 F

GND

DM9

DM8

DM7

DM6

DM5

DM4

E35

DN0

DN1

DN2

DN3

DN4

DN5

DN6

DN7

DN8

DN9

GND

C17

0.1 F

GND

VDAC

DM0

DM1

DM2

DM3

E29

E31

VDAC

E30

GND

VDAC

GND

C23

0.1 F

GND

R10

GND

C3
0.1 F

VDAC

GND

C20
0.1 F

R13
392

GND GND

R12
50

GND

R1
50

GND

VDAC

392

GND

VDAC

C33
1 F

VDAC

E32

GND

Figure 13c. PCB Schematic (Continued)

REV. 0

AD9410

AD9410 Evaluation Board Bill of Material

Quantity

Reference Description

Device

Package

Value

C1C5

Capacitor

TAJD

µF

C6C30, C32, C37, C39, C40

Capacitor

603

0.1

µF

C33

Capacitor

1206

µF

E1E7, E10E12, E14, E16E35

Ehole

J1, J3, J4, J8, J9X, J10X

SMB

P1, P4, P5

4-Pin Power

25.531.3425.0

Wieland

Connector

25.602.5453.0

P2, P3

40-Pin Header

R1, R8, R12, R23

*, R25X, R26, R27

Resistor

1206

R2, R3, R4, R6, R24, R37, R42, R43

Resistor

1206

100

R13

Resistor

1206

392

Resistor

1206

100

R9, R18

Resistor

1206

24 k

R10

Resistor

1206

2 k

R11, R15

Resistor

1206

330

R14, R19

Resistor

1206

8.2 k

R5, R16, R17, R44, R45

Resistor

1206

R28, R29, R32, R34, R36, R38R40

RPACK

766163220G

CTS

Transformer (1:1)

ADT1-1WT

Minicircuits

MC10EL16

SOIC8

AD9751

LQFP48

AD9410

LQFP80

U4, U5

74LCX821

SOIC24

74AC86

SOIC14

*Optional R23 not placed on board (50

termination resistor).

REV. 0

C016794.510/00 (rev. 0)

PRINTED IN U.S.A.

AD9410

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

80-Lead PowerQuad 2 (LQFP_ED)

(SQ-80)

PIN 1

TOP VIEW

(PINS

DOWN)

0.630 (16.00) SQ

0.551 (14.00) SQ

SEATING

PLANE

0.063 (1.60)

MAX

0.004 (0.10)

MAX

COPLANARITY

0.006 (0.15)
0.002 (0.05)

0.030 (0.75)
0.024 (0.60)
0.018 (0.45)

0.0256 (0.65)

BSC

7
0

0.008 (0.20)
0.004 (0.09)

0.015 (0.38)
0.013 (0.32)
0.009 (0.22)

0.057 (1.45)
0.055 (1.40)
0.053 (1.35)

CONTROLLING DIMENSION IN MILLIMETERS.
CENTER FIGURES ARE TYPICAL UNLESS
OTHERWISE NOTED.

BOTTOM

VIEW

NICKEL PLATED

0.120 (3.04) 45 C CHAMFER
4 PLACES

0.413 (10.50)
0.394 (10.00) REF
0.374 (9.50)

NOTE
The AD9410 has a conductive heat slug to help dissipate heat
and ensure reliable operation of the device over the full indus-
trial temperature range. The slug is exposed on the bottom of
the package. It is recommended that no PCB traces or vias be
located under the package that could come in contact with the
conductive slug. Attaching the slug to a ground plane while not
required in most applications will reduce the junction tempera-
ture of the device which may be beneficial in high temperature
environments.

Part Number AD9410/PCB