REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

Dual 8-Bit, 60 MSPS A/D Converter

AD9059

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700

Fax: 617/326-8703

FUNCTIONAL BLOCK DIAGRAM

ADC

T/H

ADC

+2.5V

T/H

ENCODE

AINA

AINB

VREF

GND

PWRDN

AD9059

D7AD0A

D7BD0B

FEATURES
Dual 8-Bit ADCs on a Single Chip
Low Power: 400 mW Typical
On-Chip +2.5 V Reference and T/Hs
1 V p-p Analog Input Range
Single +5 V Supply Operation
+5 V or +3 V Logic Interface
120 MHz Analog Bandwidth
Power-Down Mode: < 12 mW

APPLICATIONS
Digital Communications (QAM Demodulators)
RGB & YC/Composite Video Processing
Digital Data Storage Read Channels
Medical Imaging
Digital Instrumentation

PRODUCT DESCRIPTION

The AD9059 is a dual 8-bit monolithic analog-to-digital con-
verter optimized for low cost, low power, small size, and ease of
use. With a 60 MSPS encode rate capability and full-power
analog bandwidth of 120 MHz typical, the component is ideal
for applications requiring multiple ADCs with excellent dy-
namic performance.

To minimize system cost and power dissipation, the AD9059
includes an internal +2.5 V reference and dual track-and-hold
circuits. The ADC requires only a +5 V power supply and an
encode clock. No external reference or driver components are
required for many applications.

The AD9059's single encode input is TTL/CMOS compatible
and simultaneously controls both internal ADC channels. The
parallel 8-bit digital outputs can be operated from +5 V or +3 V
supplies. A power-down function may be exercised to bring to-
tal consumption to < 12 mW when ADC data is not required
for lengthy periods of time. In power-down mode the digital
outputs are driven to a high impedance state.

Fabricated on an advanced BiCMOS process, the AD9059
is available in a space saving 28-lead surface mount plastic
package (28 SSOP) and is specified over the industrial
(40

C to +85

C) temperature range.

Customers desiring single channel digitization may consider the
AD9057, a single 8-bit, 60 MSPS monolithic based on the
AD9059 ADC core. The AD9057 is available in a 20-lead sur-
face mount plastic package (20 SSOP) and is specified over the
industrial temperature range.

PIN CONFIGURATION

TOP VIEW

(Not to Scale)

AD9059

AINA

ENCODE

GND

AINB

VREF

PWRDN

D7B (MSB)

GND

D7A (MSB)

D6A

D5A

D4A

D4B

D5B

D6B

D3A

D2A

D1A

D0A (LSB)

D3B

D0B (LSB)

D1B

D2B

REV. 0

AD9059SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

AD9059BRS

Parameter

Temp

Test Level

Min

Typ

Max

Units

RESOLUTION

Bits

DC ACCURACY

Differential Nonlinearity

+25

0.75

2.0

LSB

Full

2.5

LSB

Integral Nonlinearity

+25

0.75

2.0

LSB

Full

2.5

LSB

No Missing Codes

Full

GUARANTEED

Gain Error

+25

2.5

% FS

Full

% FS

Gain Tempco

Full

ppm/

ANALOG INPUT

Input Voltage Range (Centered at +2.5 V)

+25

1.0

V p-p

Input Offset Voltage

+25

+15

Full

+25

Input Resistance

+25

150

Input Capacitance

+25

Input Bias Current

+25

Analog Bandwidth

+25

120

MHz

CHANNEL MATCHING (A to B)

Gain Delta

+25

% FS

Input Offset Voltage Delta

+25

BANDGAP REFERENCE

Output Voltage

Full

2.4

2.5

2.6

Temperature Coefficient

Full

ppm/

SWITCHING PERFORMANCE

Maximum Conversion Rate

Full

MSPS

Minimum Conversion Rate

Full

MSPS

Aperture Delay (t

)

+25

2.7

Aperture Uncertainty (Jitter)

+25

ps, rms

Output Valid Time (t

)

Full

4.0

6.6

Output Propagation Delay (t

)

Full

9.5

14.2

DYNAMIC PERFORMANCE

Transient Response

+25

Overvoltage Recovery Time

+25

Signal-to-Noise Ratio (SINAD) (with Harmonics)

= 10.3 MHz

+25

44.5

= 76 MHz

+25

43.5

Effective Number of Bits

= 10.3 MHz

+25

6.35

7.1

Bits

= 76 MHz

+25

6.9

Bits

Signal-to-Noise Ratio (SNR) (Without Harmonics)

= 10.3 MHz

+25

= 76 MHz

+25

2nd Harmonic Distortion

= 10.3 MHz

+25

dBc

= 76 MHz

+25

dBc

3rd Harmonic Distortion

= 10.3 MHz

+25

dBc

= 76 MHz

+25

dBc

Two-Tone Intermodulation Distortion (IMD)

+25

dBc

Channel Crosstalk Rejection

+25

dBc

Differential Phase

+25

0.8

Degrees

Differential Gain

+25

1.0

= +5 V, V

= +3 V; external reference; ENCODE = 60 MSPS unless otherwise noted)

AD9059BRS

Parameter

Temp

Test Level

Min

Typ

Max

Units

DIGITAL INPUTS

Logic "1" Voltage

Full

2.0

Logic "0" Voltage

Full

0.8

Logic "1" Current

Full

Logic "0" Current

Full

Input Capacitance

+25

4.5

Encode Pulse Width High (t

)

+25

6.7

166

Encode Pulse Width Low (t

)

+25

6.7

166

DIGITAL OUTPUTS

Logic "1" Voltage (V

= +3 V)

Full

2.95

Logic "1" Voltage (V

= +5 V)

Full

4.95

Logic "0" Voltage (V

= +3 V or +5 V)

Full

0.05

Output Coding

Offset Binary Code

POWER SUPPLY

Supply Current (V

= +5 V)

Full

Supply Current (V

= +3 V)

Full

Power Dissipation

5, 6

Full

400

505

Power-Down Dissipation

Full

Power Supply Rejection Ratio (PSRR)

+25

mV/V

NOTES

Gain error and gain temperature coefficient are based on the ADC only (with a fixed +2.5 V external reference).

and t

are measured from the 1.5 V level of the ENCODE to the 10%/90% levels of the digital output swing. The digital output load during test is not to exceed

an ac load of 10 pF or a dc current of

SNR/harmonics based on an analog input voltage of 0.5 dBFS referenced to a 1.0 V full-scale input range.

Digital supply current based on V

= +3 V output drive with <10 pF loading under dynamic test conditions.

Power dissipation is based on 60 MSPS encode and 10.3 MHz analog input dynamic test conditions (V

= +5 V

5%, V

= +3 V

5%).

Typical thermal impedance for the RS style (SSOP) 28-pin package:

= 39

C/W,

= 70

C/W,

= 109

C/W.

Specifications subject to change without notice.

AD9059

REV. 0

EXPLANATION OF TEST LEVELS

Test Level

100% production tested.

100% production tested at +25

C and sample tested at

specified temperatures.

III

Sample tested only.

Parameter is guaranteed by design and characteriza-
tion testing.

Parameter is a typical value only.

100% production tested at +25

C; guaranteed by

design and characterization testing for industrial tem-
perature range.

ABSOLUTE MAXIMUM RATINGS*

, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V

Analog Inputs . . . . . . . . . . . . . . . . . . . . . 0.5 V to V

+ 0.5 V

Digital Inputs . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V

+ 0.5 V

REF

Input . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V

+ 0.5 V

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . . 55

C to +125

Storage Temperature . . . . . . . . . . . . . . . . . . . 65

C to +150

*Stresses above those listed under "Absolute Maximum Ratings" may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods may affect device reliability.

ORDERING GUIDE

Model

Temperature Range

Package Option

AD9059BRS

C to +85

RS-28

AD9059/PCB

+25

Evaluation Board

WARNING!

ESD SENSITIVE DEVICE

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9059 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

AD9059

REV. 0

PIN DESCRIPTIONS

Pin No.

Name

Function

1, 28

AINA, AINB

Analog Inputs for ADC A and B.

VREF

Internal Voltage Reference (+2.5 V
Typical); Bypass with 0.1

F to

Ground or Overdrive with External
Voltage Reference.

PWRDN

Power-Down Function Select;
Logic HIGH for Power-Down
Mode (Digital Outputs Go to High-
Impedance State).

4, 25

Analog +5 V Power Supply.

5, 24, 27

GND

Ground.

6, 23

Digital Output Power Supply.
Nominally +3 V to +5 V.

714

D7AD0A

Digital Outputs of ADCA.

2215

D7BD0B

Digital Outputs of ADCB.

ENCODE

Encode Clock for ADCs A and B
(ADCs Sample Simultaneously On
the Rising Edge of ENCODE).

Table I. Digital Coding (VREF = +2.5 V)

Analog Input

Voltage Level

Digital Output

3.0 V

Positive Full Scale

1111 1111

2.502 V

Midscale + 1/2 LSB

1000 0000

2.498 V

Midscale 1/2 LSB

0111 1111

2.0 V

Negative Full Scale

0000 0000

N + 3

N + 5

N + 1

N + 2

N + 4

N 3

N 2

N 1

N + 1

N + 2

ENCODE

AIN

DIGITAL

OUTPUTS

APERTURE DELAY

PULSE WIDTH HIGH

PULSE WIDTH LOW

OUTPUT VALID TIME

OUTPUT PROP DELAY

6.7ns

4.0ns

2.7ns

6.6ns

9.5ns

166ns

14.2ns

MIN

TYP

MAX

Figure 1. Timing Diagram

PIN CONFIGURATION

TOP VIEW

(Not to Scale)

AD9059

AINA

ENCODE

GND

AINB

VREF

PWRDN

D7B (MSB)

GND

D7A (MSB)

D6A

D5A

D4A

D4B

D5B

D6B

D3A

D2A

D1A

D0A (LSB)

D3B

D0B (LSB)

D1B

D2B

AD9059

REV. 0

FREQUENCY MHz

30

90

60

20

10

80

70

50

40

ENCODE = 60MSPS
ANALOG IN = 10.3MHz, 0.5dBFS
SINAD = 43.9dB
ENOB = 7.0 BITS
SNR = 45.1dB

Figure 2. FFT Spectral Plot 60 MSPS, 10.3 MHz

FREQUENCY MHz

30

90

60

20

10

50

40

80

70

ENCODE = 60MSPS

ANALOG IN = 76MHz, 0.5dBFS

SINAD = 43.0dB

ENOB = 6.85 BITS

SNR = 44.1dB

Figure 3. Spectral Plot 60 MSPS, 76 MHz

ANALOG INPUT FREQUENCY MHz

160

100

120

140

ENCODE = 60MSPS
AIN = 0.5dBFS

SNR

SINAD

Figure 4. SINAD/SNR vs. AIN Frequency

ANALOG INPUT FREQUENCY MHz

30

70

160

100

120

140

35

50

55

60

65

40

45

2ND HARMONIC

3RD HARMONIC

ENCODE = 60MSPS
AIN = 0.5dBFS

Figure 5. Harmonic Distortion vs. AIN Frequency

FREQUENCY MHz

10

90

50

60

70

80

30

40

20

ENCODE = 60MSPS
F1 IN = 9.5MHz @ 7.0dBFS
F2 IN = 9.9MHz @ 7.0dBFS
2F1 - F2 = 52.0dBc
2F2 - F1 = 53.0dBc

Figure 6. Two-Tone IMD

ENCODE RATE MSPS

AIN = 10.3MHz, 0.5dBFS

SNR

SINAD

Figure 7. SINAD/SNR vs. Encode Rate

AD9059

REV. 0

ENCODE RATE MSPS

POWER mW

600

400

250

550

500

350

300

450

AIN = 10.3MHz, 0.5dBFS

= +5V

= +3V

Figure 8. Power Dissipation vs. Encode Rate

TEMPERATURE 

45.5

45.0

41.5

45

43.5

43.0

42.5

42.0

44.5

44.0

SNR

SINAD

ENCODE = 60MSPS
AIN = 10.3MHz, 0.5dBFS

Figure 9. SINAD/SNR vs. Temperature

TEMPERATURE 

GAIN ERROR %

0.2

1.8

45

0.8

1.2

1.4

1.6

0.4

0.6

1.0

Figure 10. ADC Gain vs. Temperature (With External
+2.5 V Reference)

TEMPERATURE 

 ns

9.5

45

8.0

6.5

6.0

9.0

8.5

7.0

7.5

= +5V

= +3V

Figure 11. t

vs. Temperature/Supply (+3 V/+5 V)

ENCODE HIGH PULSE WIDTH ns

45.5

40.5

5.8

10.9

44.5

43.5

41.5

42.5

6.7

7.5

8.35

9.2

SNR

ENCODE = 60MSPS
AIN = 10.3MHz, 0.5dBFS

SINAD

Figure 12. SINAD/SNR vs. Encode Pulse Width

ANALOG FREQUENCY MHz

ADC GAIN dB

500

100

10

ENCODE = 60MSPS
AIN = 0..5dBFS

200

Figure 13. ADC Frequency Response

AD9059

REV. 0

applied to the VREF pin to overdrive the internal voltage refer-
ence for gain adjustment of up to

10% (the VREF pin is inter-

nally tied directly to the ADC circuitry). ADC gain and offset
will vary simultaneously with external reference adjustment with
a 1:1 ratio (a 2% or 50 mV adjustment to the +2.5 V reference
varies ADC gain by 2% and ADC offset by 50 mV).

Theoretical input voltage range versus reference input voltage
may be calculated from the following equations:

RANGE

(p-p) = VREF/2.5

MIDSCALE

= VREF

TOP-OF-RANGE

= VREF + V

RANGE

BOTTOM-OF-RANGE

= VREF V

RANGE

The external reference should have a 1 mA minimum sink/
source current capability to ensure complete overdrive of the
internal voltage reference.

Digital Logic (+5 V/+3 V Systems)

The digital inputs and outputs of the AD9059 can easily be
configured to interface directly with +3 V or +5 V logic systems.
The encode and power-down (PWRDN) inputs are CMOS
stages with TTL thresholds of 1.5 V, making the inputs compat-
ible with TTL, +5 V CMOS, and +3 V CMOS logic families.
As with all high speed data converters, the encode signal should
be clean and jitter free to prevent degradation of ADC dynamic
performance.

The AD9059's digital outputs will also interface directly with
+5 V or +3 V CMOS logic systems. The voltage supply pins
(V

) for these CMOS stages are isolated from the analog V

voltage supply. By varying the voltage on these supply pins the
digital output HIGH levels will change for +5 V or +3 V sys-
tems. The V

pins are internally connected on the AD9059

die. Care should be taken to isolate the V

supply voltages

from the +5 V analog supply to minimize noise coupling into
the ADCs.

The AD9059 provides high impedance digital output operation
when the ADC is driven into power-down mode (PWRDN,
logic HIGH). A 200 ns (minimum) power-down time should
be provided before a high impedance characteristic is required.
A 200 ns power-up period should be provided to ensure accu-
rate ADC output data after reactivation (valid output data is
available three clock cycles after the 200 ns delay).

Timing

The AD9059 is guaranteed to operate with conversion rates
from 5 MSPS to 60 MSPS. At 60 MSPS the ADC is designed
to operate with an encode duty cycle of 50%, but performance
is insensitive to moderate variations. Pulse width variations of
up to

10% (allowing the encode signal to meet the minimum/

maximum HIGH/LOW specifications) will cause no degrada-
tion in ADC performance (refer to Figure 1 Timing Diagram).

Due to the linked ENCODE architecture of the ADCs, the
AD9059 cannot be operated in a two-channel ping-pong mode.

THEORY OF OPERATION

The AD9059 combines Analog Devices' proprietary MagAmp
gray code conversion circuitry with flash converter technology
to provide dual high performance 8-bit ADCs in a single low
cost monolithic device. The design architecture ensures low
power, high speed, and 8-bit accuracy.

The AD9059 provides two linked ADC channels that are
clocked from a single ENCODE input (refer to block diagram).
The two ADC channels simultaneously sample the analog in-
puts (AINA and AINB) and provide non-interleaved parallel
digital outputs (D0AD7A and D0BD7B). The voltage refer-
ence (VREF) is internally connected to both ADCs so channel
gains and offsets will track if external reference control is
desired.

The analog input signal is buffered at the input of each ADC
channel and applied to a high speed track-and-hold. The T/H
circuit holds the analog input value during the conversion pro-
cess (beginning with the rising edge of the ENCODE com-
mand). The T/H's output signal passes through the gray code
and flash conversion stages to generate coarse and fine digital
representations of the held analog input level. Decode logic
combines the multistage data and aligns the 8-bit word for
strobed outputs on the rising edge of the ENCODE command.
The MagAmp/Flash architecture of the AD9059 results in three
pipeline delays for the output data.

USING THE AD9059
Analog Inputs

The AD9059 provides independent single-ended high imped-
ance (150 k

) analog inputs for the dual ADCs. Each input

requires a dc bias current of 6

A (typical) centered near +2.5 V

(

10%). The dc bias may be provided by the user or may be

derived from the ADC's internal voltage reference. Figure 14
shows a low cost dc bias implementation allowing the user to
capacitively couple ac signals directly into the ADC without ad-
ditional active circuitry. For best dynamic performance the
VREF pin should be decoupled to ground with a 0.1

F capaci-

tor (to minimize modulation of the reference voltage), and the
bias resistor should approximately 1 k

Figure 15 shows typical connections for high performance dc bi-
asing using the ADC's internal voltage reference. All compo-
nents may be powered from a single +5 V supply (example
analog input signals are referenced to ground).

Voltage Reference

A stable and accurate +2.5 V voltage reference is built into the
AD9059 (VREF). The reference output is used to set the ADC
gain/offset and can provide dc bias for the analog input signals.
The internal reference is tied to the ADC circuitry through a
800

internal impedance and is capable of providing 300

external drive current (for dc biasing the analog input or other
user circuitry).

Some applications may require greater accuracy, improved tem-
perature performance, or gain adjustments which cannot be ob-
tained using the internal reference. An external voltage may be

AD9059

REV. 0

Power Dissipation

The power dissipation of the AD9059 is specified to reflect a
typical application setup under the following conditions: en-
code is 60 MSPS, analog input is 0.5 dBFS at 10.3 MHz, V

is +5 V, V

is +3 V, and digital outputs are loaded with 7 pF

typical (10 pF maximum). The actual dissipation will vary as
these conditions are modified in user applications. Figure 8
shows typical power consumption for the AD9059 versus ADC
encode frequency and V

supply voltage.

AINA

AINB

REF

AD9059

0.1µF

+5V

VIN

(1V p-p)

EXTERNAL V

REF

(OPTIONAL)

VIN

(1V p-p)

Figure 14. Capacitively Coupled AD9059

A power-down function allows users to reduce power dissipa-
tion when ADC data is not required. A TTL/CMOS HIGH
signal (PWRDN) shuts down portions of the dual ADC and
brings total power dissipation to less than 10 mW. The internal
bandgap voltage reference remains active during power-down
mode to minimize ADC reactivation time. If the power-down
function is not desired, Pin 3 should be tied to ground. Both
ADC channels are controlled simultaneously by the PWRDN
pin; they cannot be shut down or turned on independently.

Applications

The wide analog bandwidth of the AD9059 makes it attractive
for a variety of high performance receiver and encoder applica-
tions. Figure 16 shows the dual ADC in a typical low cost I & Q
demodulator implementation for cable, satellite, or wireless
LAN modem receivers. The excellent dynamic performance of
the ADC at higher analog input frequencies and encode rates
empowers users to employ direct IF sampling techniques (refer
to Figure 3, Spectral Plot). IF sampling eliminates or simplifies
analog mixer and filter stages to reduce total system cost and
power.

10k

AINA

AINB

REF

AD9059

0.1µF

+5V

VIN

(0.5V TO +0.5V)

10k

+5V

AD8041

Figure 15. DC Coupled AD9059 (VIN Inverted)

AD9059

BPF

VCO

IF IN

VCO

ADC

Figure 16. I and Q Digital Receiver

The high sampling rate and analog bandwidth of the AD9059
are ideal for computer RGB video digitizer applications. With a
full-power analog bandwidth of 2

the maximum sampling rate,

the ADC provides sufficient pixel-to-pixel transient settling
time to ensure accurate 60 MSPS video digitization. Figure 17
shows a typical RGB video digitizer implementation for the
AD9059.

RED

GREEN

AD9059

BLUE

AD9059

H-SYNC

PLL

PIXEL CLOCK

ADC

Figure 17. RGB Video Encoder

AD9059

REV. 0

ENCODE

PWRDN

D0D7

+3V TO +5V

500

REF

AIN

Digital Inputs

Analog Inputs

Digital Outputs

800

REF

2.5k

+2.5V

Voltage Reference

Figure 18. Equivalent Circuits

Evaluation Board

The AD9059/PCB evaluation board provides an easy-to-use
analog/digital interface for the dual 8-bit, 60 MSPS ADC. The
board includes typical hardware configurations for a variety of
high speed digitization evaluations. On-board components in-
clude the AD9059 (in the 28-pin SSOP package), optional ana-
log input buffer amplifiers, digital output latches, board timing
drivers, and configurable jumpers for ac coupling, dc coupling,
and power-down function testing. The board is configured at
shipment for dc coupling using the AD9059's internal reference.

For dc coupled analog input applications, amplifiers U3 and U4
are configured to operate as unity gain inverters with adjustable
offset for the analog input signals. For full-scale ADC drive
each analog input signal should be 1 V p-p into 50

referenced

to ground. Each amplifier offsets its analog signal by +VREF
(+2.5 V typical) to center the voltage for proper ADC input
drive. For dc coupled operation, connect E7 to E9 (analog in-
put A to R11), E14 to E13 (amplifier output to analog input A
of AD9059), E4 to E5 (analog input B to R10), and E11 to E10
(amplifier output to analog input B of AD9059) using the board
jumper connectors.

For ac coupled analog input applications, amplifiers U3 and U4
are removed from the analog signal paths. The analog signals
are coupled through capacitors C11 and C12, each terminated
to the VREF voltage through separate 1 k

resistors (providing

bias current for the AD9059 analog inputs, AINA and AINB).

Analog input signals to the board should be 1 V p-p into 50

for full-scale ADC drive. For ac coupled operation, connect E7
to E8 (analog input A to C12 feedthrough capacitor), E13 to
E15 (C12 to R15 termination resistor for channel A), E4 to E6
(analog input B to C11 feedthrough capacitor), and E10 to E12
(C11 to R14 termination resistor for channel B) using the board
jumper connectors.

The on-board reference voltage may be used to drive the ADC
or an external reference may be applied. The standard configu-
ration employs the internal voltage reference without any exter-
nal connection requirements. An external voltage reference may
be applied at board connector input REF to overdrive the lim-
ited current output of the AD9059's internal voltage reference.
The external voltage reference should be +2.5 V typical.

The power-down function of the AD9059 can be exercised
through a board jumper connection. Connect E2 to E1 (+5 V
to PWRDN) for power-down mode operation. For normal op-
eration, connect E3 to E1 (ground to PWRDN).

The encode signal source should be TTL/CMOS compatible
and capable of driving a 50

termination. The digital outputs

of the AD9059 are buffered through latches on the evaluation
board (U5 and U6) and are available for the user at connector
Pins 3037 and Pins 2229. Latch timing is derived from the
ADC ENCODE clock and a digital clocking signal is provided
for the board user at connector Pins 2 and 21.

AD9059

REV. 0

CK OE

74ACQ574

D0B

D1B

D2B

D3B

D4B

D5B

D6B

D7B

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

CK OE

74ACQ574

D7A

D6A

D5A

D4A

D3A

D2A

D1A

D0A

DA7

DA6

DA5

DA4

DA3

DA2

DA1

DA0

74AC00

R15
50

+5V

E10

E11

C12

0.1µF

E14

E15

E13

PWRDN

+5V

E12

R14
1k

DIS

AD8041Q

R11
1k

R13
50

BNC

ANALOG INA

1
2

7
8

20
21

30
31

36
37

C37DRPF

BNC

J10

ENCODE

J12, GND

C14
0.1µF

C7
0.1µF

C6
0.1µF

C15
10µF

C13
0.1µF

C5
0.1µF

C4
0.1µF

C3
0.1µF

+5V

DECOUPLING CAPS

J11, V

AD9059RS

AINA

REF

PWRDN

GND

D7A

D6A

D5A

D4A

D3A

D2A

D1A

D0A

AINB

GND

ENC

GND

D7B

D6B

D5B

D4B

D3B

D2B

D1B

D0B

D7B

D6B

D5B

D4B

D3B

D2B

D1B

D0B

0.1µF

C16
10µF

J9, V

0.1µF

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7
DA0
DA1

DA2

DA3

DA4

DA5

DA6

DA7

74AC00

C10
0.1µF

C17
10µF

R9
10k

10k

R15
1k

J1, REF

D7A

D6A

D5A

D4A

D3A

D2A

D1A

D0A

DIS

AD8041Q

R10
1k

R12
50

BNC

ANALOG INB

+5V

C11

0.1µF

+5V

Figure 19. AD9059 Dual Evaluation Board Schematic

Part Number AD9059