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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

12-Bit 25 MSPS

A/D Converter

AD9032

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700

Fax: 617/326-8703

FUNCTIONAL BLOCK DIAGRAM

ANALOG

INPUT

ENCODE

TRACK-

AND-

HOLD

SUM
AMP

FLASH

ADC/DAC

ERROR

CORR.
LOGIC

RESIDUE

ENCODER

DIGITAL
OUTPUT

DATA
READY

TIMING

CIRCUITS

AD9032

FEATURES
25.6 MSPS Conversion Speeds
On-Board T/H, References, Timing
Low Power: 3.8 W
Single 40-Pin Package
74 dB Spurious-Free Dynamic Range

to 12 MHz A

Bipolar Input: 1.024 V

APPLICATIONS
Radar
Signal Intelligence
Digital Spectrum Analyzers
Medical Imaging
Electro-Optics

EVALUATION BOARD

An evaluation board which is available for the AD9032 (part
number AD9034/PCB) provides an easy and flexible method
for evaluating the ADC's performance without (or prior to)
developing a user-specified printed circuit board. The evalua-
tion board was originally designed and used for evaluating the
AD9034 A/D converter, but is equally useful for the pin-
compatible AD9032.

The board includes a reconstruction DAC, analog input ampli-
fier, and digital output interface. Physically, it is 7.25 inches
6 inches in size and uses the layout and applications information
contained in the AD9034 data sheet.

Generous space is provided near the analog input and digital
outputs of the evaluation board to support additional signal pro-
cessing components the user may wish to add. These two proto-
typing areas include through holes with 100-mil centers to
support a variety of component additions.

For additional operating details, a schematic of the evaluation
board, and complete layout information, consult the data sheet
on the AD9034 A/D converter.

GENERAL DESCRIPTION

The AD9032 is the world's fastest 12-bit analog-to-digital con-
verter (ADC) that includes on-board T/H, voltage references,
and timing circuits. The AD9032 uses a subranging converter
architecture to achieve sample rates from dc to 25.6 MSPS. Pack-
aged in a single 40-pin hybrid, the AD9032 is pin-compatible with
the AD9034, which operates at word rates up to 20 MSPS.

This ECL-compatible ADC requires only +5 V and 5.2 V sup-
plies, an analog input, and a stable ECL clock to obtain the best
dynamic performance available in a 12-bit ADC. This kind of
performance is achieved with advanced bipolar circuits, custom
designed and manufactured by Analog Devices. The latest in
monolithic track-and-hold technology ensures accurate sam-
pling of high frequency analog inputs.

Dynamic performance has been optimized to achieve SNR of
64 dB and a spurious-free dynamic range (SFDR) of 74 dB for
analog bandwidths up to 12 MHz. All units are tested for dy-
namic performance at a sample rate of 25.6 MSPS.

The AD9032 is available in either a 40-pin ceramic DIP or
leaded flatpack. The two versions operate over an industrial
(25

C to +85

C) or military (55

C to +125

C) temperature

range.

AD9032SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Test

AD9032AD/AZ

AD9032BD/BZ

AD9032TD/TZ

Parameter (Conditions)

Temp

Level

Min Typ

Max

Min Typ

Max

Min Typ

Max

Units

RESOLUTION

Bits

DC ACCURACY

Differential Nonlinearity

+25

0.65

1.25

0.5

1.0

0.5

1.0

LSB

Full

1.75

1.5

LSB

Integral Nonlinearity

+25

1.0

LSB

Full

2.0

LSB

No Missing Codes

Full

Guaranteed

Offset Error

+25

Full

Gain Error

+25

0.5

1.0

0.5

1.0

0.5

1.0

% FS

Full

2.5

% FS

ANALOG INPUT

Input Voltage Range

+25

1.024

Input Resistance

+25

100

105

100

105

100

105

Input Capacitance

+25

Analog Bandwidth

+25

150

220

150

220

150

220

MHz

SWITCHING PERFORMANCE

Conversion Rate

Full

25.6

MSPS

Aperture Delay (t

)

Full

Aperture Uncertainty (jitter)

Full

ps, rms

Output Delay (t

)

Full

Data Ready Delay (t

)

Full

3.5

7.5

10.5

3.5

7.5

10.5

3.5

7.5

10.5

Output Time Skew

Full

ENCODE INPUT

Logic "1" Voltage

Full

1.1

Logic "0" Voltage

Full

1.5

Logic "1" Current

Full

150

300

150

300

150

300

Logic "0" Current

Full

150

300

150

300

150

300

Input Capacitance

+25

Pulse Width (High)

+25

Pulse Width (Low)

+25

DYNAMIC PERFORMANCE

Transient Response

+25

Overvoltage Recovery Time

+25

Harmonic Distortion

Analog Input @ 1.2 MHz

+25

dBc

@ 1.2 MHz

Full

dBc

@ 4.3 MHz

+25

dBc

@ 9.6 MHz

+25

dBc

@ 9.6 MHz

Full

dBc

@ 12.1 MHz

+25

dBc

Signal-to-Noise Ratio

Analog Input @ 1.2 MHz

+25

@ 1.2 MHz

Full

@ 4.3 MHz

+25

@ 9.6 MHz

+25

@ 9.6 MHz

Full

@ 12.1 MHz

+25

Two-Tone Intermodulation

Distortion Rejection

+25

dBc

(+V

= +5 V; V

= 5.2 V, Encode = 25.6 MSPS, unless otherwise noted)

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Test

AD9032AD/AZ

AD9032BD/BZ

AD9032TD/TZ

Parameter (Conditions)

Temp

Level

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Units

DIGITAL OUTPUTS (10K ECL)

Logic "1" Voltage

Full

1.1

Logic "0" Voltage

Full

1.5

Output Coding

2s Complement

POWER SUPPLY

Supply Voltage

Full

4.75

5.0

5.25

4.75

5.0

5.25

4.75

5.0

5.25

Supply Current

Full

133

160

133

160

133

160

Supply Voltage

Full

5.45 5.2

4.95 5.45 5.2

4.95

5.45 5.2

4.95

Supply Current

Full

610

672

610

672

610

672

Power Dissipation

Full

3.8

4.5

3.8

4.5

3.8

4.5

Power Supply

Rejection Ratio (PSRR)

Full

4.0

mV/V

NOTES

Outputs terminated through 510

to 5.2 V; C

< 4 pF. Typical values are valid for +25

C ambient.

RMS signal to rms noise with analog input signal 1 dB below full scale at specified frequency.

Intermodulation measured with analog input frequencies of 9.3 MHz and 9.6 MHz at 7 dB below full scale.

PSRR is sensitivity of offset error to power supply variations within the 5% limits shown.

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

to +V

Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

to 0 V

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature Range

AD9032AD/BD/AZ/BZ . . . . . . . . . . . . . . . . 25

C to +85

AD9032TD/TZ . . . . . . . . . . . . . . . . . . . . . 55

C to +125

Maximum Junction Temperature

+175

Lead Temperature (Soldering, 10 seconds) . . . . . . . . . +300

Storage Temperature Range . . . . . . . . . . . . . 65

C to +150

NOTES

Absolute maximum ratings are limiting values to be applied individually, and
beyond which the service ability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.

Typical thermal impedances:

= 13

C/W; T

= 10

C max (worst case die

junction temperature rise). See Thermal Management section.

EXPLANATION OF TEST LEVELS

Test Level
I

100% production tested.

100% production tested at +25

C, and sample tested at

specified temperatures. AC testing done on sample basis.

III Sample tested only.
IV Parameter is guaranteed by design and characterization

testing.

Parameter is a typical value only.

VI All devices are 100% production tested at +25

Devices are 100% production tested at temperature
extremes for extended temperature devices; sample
tested at temperature extremes for commercial/
industrial devices.

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

AD9032AD

C to +85

40-Pin Ceramic DIP

DH-40A

AD9032AZ*

C to +85

40-Pin Ceramic Leaded Chip Carrier

Z-40

AD9032BD

C to +85

40-Pin Ceramic DIP

DH-40A

AD9032BZ*

C to +85

40-Pin Ceramic Leaded Chip Carrier

Z-40

AD9032TD

C to +125

40-Pin Ceramic DIP

DH-40A

AD9032TZ*

C to +125

40-Pin Ceramic Leaded Chip Carrier

Z-40

AD9034/PWB

Printed Circuit Board (Only) of Evaluation Circuit

AD9034/PCB

Complete Evaluation Board, Assembled and Tested
(Order AD9032 DIP Separately)

*Ceramic leaded chip carrier packages are tested and shipped with unformed leads. Consult the factory for availability.

AD9032

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AD9032

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DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth

The analog input frequency at which the spectral power of the
fundamental frequency (as determined by FFT analysis) is re-
duced by 3 dB.

Aperture Delay (t

)

The delay between the rising edge of the ENCODE command
and the instant at which the analog input is sampled.

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Data Ready Delay (t

)

The delay between the 50% point of the change in output data
and the 50% point of the rising edge of DATA READY.

Differential Nonlinearity (DNL)

The deviation of any code width from an ideal 1 LSB step, as
determined by a histogram.

Harmonic Distortion

The rms value of the fundamental divided by the rms value of
the worst harmonic.

Integral Nonlinearity (INL)

The deviation of the transfer function from a reference line mea-
sured in fractions of 1 LSB using a "best straight line" deter-
mined by a least square curve fit, as determined by a histogram.

Output Delay (t

)

The delay between the 50% point of the rising edge of the
ENCODE command and the 50% point of the next change in
output data.

Output Time Skew

Bit-to-bit time variations among D

to D

outputs. Time skew

includes HIGH-to-LOW and LOW-to-HIGH transitions of the
digital output bits.

Overvoltage Recovery Time

The amount of time required for the converter to recover to
12-bit accuracy after an analog input signal 150% of full scale is
reduced to the midscale of the converter.

Power Supply Rejection Ratio

The ratio of a change in power supply voltage which results in a
change in input offset voltage.

Pulse Width (High and Low)

Rated performance of the ADC is assured when stated restric-
tions on ENCODE pulse width shown in Specifications table
are observed.

Signal-to-Noise Ratio (SNR)

The ratio of the rms signal amplitude to the rms value of
"noise," which is defined as the sum of all other spectral compo-
nents, including harmonics but excluding dc, with an analog in-
put signal 1 dB below full scale.

Spurious Free Dynamic Range (SFDR)

The rms value of the fundamental divided by the rms value of
the highest spurious signal. This is generally specified as a func-
tion of input signal level.

Transient Response

The time required for the converter to achieve 12-bit accuracy
when a full-scale step function is applied to the analog input.

Two-Tone Intermodulation Distortion (IMD) Rejection

The ratio of the power of either of two input signals to the
power of the strongest third-order IMD signal.

N + 1

N 2

N 1

ENCODE

DATA

OUTPUT

ANALOG

T/H

HOLD

DATA

READY

TRACK

= 3ns TYPICAL

= 13ns TYPICAL

= 7.5ns TYPICAL

Timing Diagram

AD9032

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PIN DESCRIPTIONS

Pin

Name

Description

GAIN

Can be used to null out initial gain

ADJUST

error of ADC. Normally open.

OFFSET

Can be used to null out initial off-

ADJUST

set error of ADC. Normally open.

3, 5, 6,

GROUND

All ground pins should be connect

14, 21,

ed together and to low-impedance

22, 35, 40

ground plane near AD9034.

ANALOG

Analog input to ADC,

1.024 V

INPUT

input range; 100

input resist-

ance; 7 pF input capacitance.

7, 8, 9, 15, DNC

Do not connect. Internal test

16, 36, 37

points.

OVERFLOW ECL-compatible output; normally

low. High when analog input
> +FS.

DATA

ECL-compatible output. Rising

READY

edge of signal suitable, for exter-
nally latching D

12, 17,

5.2 V supply voltage.

20, 38

13, 39

+5.0 V supply voltage.

ENCODE

Differential ECL convert command.

ENCODE

Sampling occurs on rising edge;
no internal terminations.

2334

ECL-compatible digital outputs;
2s complement coding.

THEORY OF OPERATION

The AD9032 is a digitally corrected subranging analog-to-digital
converter (ADC) optimized for fast sampling rates and dynamic
range. Refer to the block diagram on the first page. The
AD9032 is a vertically integrated structure consisting of a track-
and-hold (T/H) amplifier, a combined flash ADC and digital-to-
analog (DAC), a summation amplifier, digital error correction
logic, and timing circuits. Reference circuits to generate stable
DC voltages and currents that maintain the static accuracy of
the device are also included, but are not shown on the block
diagram.

Internally, the monolithic T/H (AD9101) provides fast settling
and acquisition times while minimizing distortion introduced by
the sampling process. The unique design of the sampling bridge
allows accurate sampling of high slew rate signals with negligible
distortion. The effects of jitter and other aperture errors have
been reduced to provide dynamic performance previously un-
available in monolithic and discrete designs.

At the output of the T/H amplifier, the analog input is converted
by the first (5-bit) ADC. This 12-bit representation of the input
value is stored in the digital error correction logic. It is also con-
verted back to an analog signal by the 14-bit-accurate DAC on
the same chip with the ADC. The 32 DAC current sources are
steered directly by the outputs of the 32 input comparators on
the 5-bit ADC. This minimizes propagation delay through the
DAC, and allows the summation of the DAC signal and the held
output of the T/H to settle quickly. The hold time of the T/H is
optimized to allow sufficient settling time without sacrificing the
acquisition time necessary to acquire the next sample.

The residue signal, representing the difference between the 5-bit
conversion (DAC output) and the input signal held by the T/H,
is amplified by the summation amplifier. During the tracking pe-
riod of the T/H, this residue signal can be much larger than the
input range of the 8-bit ADC and would saturate the output
stage of a normal amplifier. To protect the ADC and maintain
fast settling times under all conditions, the summation amplifier
is a custom design with clamping circuits that prevent satura-
tion, limit the output voltage, and preserve settling time.

The 8-bit flash ADC determines the 7 least significant bits
(LSBs) of the 12-bit conversion and generates a correction bit
for any small errors created by inaccuracies in the first 5-bit con-
version. This 8-bit signal and the 5-bit quantization are com-
bined to obtain a 12-bit-accurate representation of the analog
input voltage.

PIN DESIGNATIONS

GROUND

DNC

GROUND

(LSB)

(MSB)

GROUND

DNC

GROUND

ANALOG INPUT

GROUND

DNC

OVERFLOW

DATA READY

GROUND

DNC

ENCODE

DIGITAL

ENCODE

TOP VIEW

(Not to Scale)

AD9032

AD9032

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USING THE AD9032
Layout Information

Preserving the accuracy and dynamic performance of the
AD9032 requires that designers pay special attention to the lay-
out of the printed circuit board. Signal paths should be imped-
ance matched and properly terminated at or near the package
connections. Analog signal paths should be isolated from digital
signal paths. Capacitive and inductive coupling of digital signals
into analog signal sections can degrade the overall performance
of the A/D converter.

Analog Input

The analog input pin of the AD9032 is terminated with a 100

load. The analog input range of the AD9032 is factory trimmed
for a

1.024 V input for compatibility with the AD9034. The

signal presented to the monolithic T/H is divided in half to opti-
mize dynamic performance.

When the amplitude, bandwidth, or dc level of the analog input
requires external signal conditioning, the selection of the input
amplifier is of particular concern. The noise and distortion of
the amplifier must be taken into account to preserve the dy-
namic range of the AD9032. The AD9617 wideband, current
feedback amplifier is an excellent choice for most applications.

Timing

Internal timing for the AD9032 is trimmed at the factory to sim-
plify use. Care should be taken to ensure that the encode com-
mand to the AD9032 is free from jitter that can degrade
dynamic performance. Differential ECL inputs to the AD9032
can be derived from a single-ended source using a fast compara-
tor such as the AD96685. The encode source should be located
and terminated as close to the AD9032 as possible.

The ECL-compatible digital outputs are latched to provide valid
data for the entire conversion period (less the transition region
of latch). This data should be latched into external ECL regis-
ters located near the AD9032. External termination resistors are
required (510

recommended). The data are latched with ei-

ther the encode command or the data ready signal provided on
the AD9032. The rising edge of the data ready signal occurs
typically 7.5 ns after the data changes.

Gain and Offset Adjustment

Gain and offset pins are normally not connected. Rated perfor-
mance is guaranteed without any external connection to these
pins. In most applications, wide variations in input signal range
and offset can be accommodated using external amplifiers.
However, in those applications where a vernier adjustment is re-
quired (such as nulling out factory trim limits), the gain and off-
set pins will provide sufficient adjustment range.

Both inputs offer a 20 k

input resistance that can be driven

from a voltage source (DAC, amplifier) or the center tap of a
potentiometer. The offset pin provides a 195 mV/V sensitivity to
input offset, while the gain pin offers 120 mV/V adjustment of
the full-scale input range of the ADC. The adjustment range for
offset is limited to 10 mV and for gain is 20 mV without intro-
ducing potential dynamic errors or restricting the operating tem-
perature range of the part.

Power Supplies

The unique design of the AD9032 provides excellent dynamic
performance without a need for high voltage power supplies.
Two supplies (+5 V and 5.2 V) are all that are required to
achieve rated performance. Careful layout and decoupling of
power supplies used in conjunction with a low impedance ana-
log ground plane will reduce supply-related noise components.

Separate analog and digital supplies are not required. In applica-
tions with only limited analog supply current, a separate digital
supply source can be used for the 5.2 V supply on Pin 20. This
supply typically requires 310 mA (330 mA max) and may be
shared with other ECL logic devices when isolated with bypass
capacitors and/or ferrite bead inductors (Fair-Rite Products
Corporation part # 2743001111, Wallkill, NY). Each power
supply pin should be capacitively decoupled to the ground plane
through a good high frequency ceramic capacitor (0.1

F) and a

single large value capacitor (tantalum 10

F).

For optimum performance, "clean" linear supplies ensure that
switching noise on the supplies does not introduce distortion
products during the encoding process. Recognizing, however,
that switching power supplies may be required in power-
sensitive applications, decoupling recommendations outlined
above are critically important for using switching supplies
effectively. Elsewhere in this data sheet, a graph shows the
PSRR of the AD9032 as a function of the ripple frequency
present on the AD9032 supplies. Clearly, if they must be used,
switching power supplies with the lowest possible frequency
should be selected.

Thermal Management

The AD9032 design minimizes power dissipation; however, the
ADC does typically require 3.8 W (4.5 W max) to operate. To
ensure long life and reliable operation, the maximum junction
temperature in the AD9032 must be limited to +175

Within the hybrid, the hottest discrete die has a case to junction
temperature rise of 10

C (max). Therefore, the case tempera-

ture of the AD9032 should not exceed +165

C under worst case

operating conditions. Without airflow, the

of the hybrid

package is 13

C/W. Assuming maximum power dissipation, this

causes a 57

C rise in case temperature over the ambient air tem-

perature. The maximum still air temperature, therefore, is equal
to +108

Rated performance of the AD9032 is guaranteed for case oper-
ating temperatures of +85

C (AD9032A/B) and +125

(AD9032T). This equates to a maximum operating ambient
temperature of +28

C and +68

C, respectively, in still air. In

most applications, airflow is recommended. The following im-
provements in the thermal characteristics of the system assume
that the AD9032 is soldered to a PC board.

The

of the hybrid is reduced to 5

C/W with 500 LFPM air-

flow. This will extend the rated performance to ambient operat-
ing ranges of +63

C for the AD9032A/B and +103

C for the

AD9032T. The addition of a heat sink (Thermalloy #6087B,
Dallas, Texas; phone 214-243-0839) will further improve the
thermal transfer of the hybrid to 3

C/W (@ 500 LFPM). Using

a heat sink with airflow, the total case to ambient temperature
rise is only 13

C, which results in a maximum ambient environ-

ment of +72

C (AD9032A/B) and +112

C (AD9032T).

AD9032

REV. 0

100

12.8

83

50

67

33

17

10.2

7.7

5.1

2.6

FREQUENCY MHz

OUTPUT dB

ENCODE = 25.6 MHz
FREQ = 12.1 MHz
SNR = 64.1 dB
SFDR = 75.2 dBFS
FUND = 1.0 dBFS
2nd HARM = 74.4 dBc
3rd HARM = 82.1 dBc

AD9032 A/D Converter FFT

100

SIGNAL-TO-NOISE RATIO dB

INPUT FREQUENCY MHz

WORD RATE = 25.6 MSPS

+25

55

+125

AD9032 SNR vs. Analog Input

100

12.8

83

50

67

33

17

10.2

7.7

5.1

2.6

FREQUENCY MHz

OUTPUT dB

ENCODE = 25.6 MHz
FREQ = 1.2 MHz
SNR = 66.7 dB
SFDR = 84.8 dBFS
FUND = 1.0 dBFS
2nd HARM = 90.3 dBc
3rd HARM = 89.3 dBc

AD9032 A/D Converter FFT

100

HARMONIC DISTORTION dB

INPUT FREQUENCY MHz

+25

55

+125

WORD RATE = 25.6 MSPS

AD9032 Harmonic Distortion vs. Analog Input

0.1

SUPPLY RIPPLE FREQUENCY MHz

WORD RATE = 25.6 MSPS

+25

POWER SUPPLY REJECTION RATIO d

PSRR = 20 x LOG

( )

SUPPLY RIPPLE

EQUIV. INPUT RIPPLE

AD9032 PSRR vs. Supply Ripple Frequency

2.5k

ENCODE

200

Equivalent Encode Input
Circuit

1mA

Equivalent Analog Input
Circuit

 D

Equivalent Digital Output Circuit

Part Number AD9032