REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD8343
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
DC-to-2.5 GHz
High IP3 Active Mixer
FUNCTIONAL BLOCK DIAGRAM
14
13
12
11
10
9
8
1
2
3
4
5
6
7
BIAS
COMM
AD8343
INPP
INPM
DCPL
VPOS
PWDN
COMM
COMM
OUTP
OUTM
COMM
LOIP
LOIM
COMM
FEATURES
High-Performance Active Mixer
Broadband Operation to 2.5 GHz
Conversion Gain: 7.1 dB
Input IP3: 16.5 dBm
LO Drive: 10 dBm
Noise Figure: 14.1 dB
Input P1 dB: 2.8 dBm
Differential LO, IF and RF Ports
50
LO Input Impedance
Single-Supply Operation: 5 V @ 50 mA Typical
Power-Down Mode @ 20 A Typical
APPLICATIONS
Cellular Base Stations
Wireless LAN
Satellite Converters
SONET/SDH Radio
Radio Links
RF Instrumentation
PRODUCT DESCRIPTION
The AD8343 is a high-performance broadband active mixer.
Having wide bandwidth on all ports and very low intermodulation
distortion, the AD8343 is well suited for demanding transmit or
receive channel applications.
The AD8343 provides a typical conversion gain of 7.1 dB. The
integrated LO driver supports a 50
differential input imped-
ance with low LO drive level, helping to minimize external
component count.
The open-emitter differential inputs may be interfaced directly
to a differential filter or driven through a balun (transformer) to
provide a balanced drive from a single-ended source.
The open-collector differential outputs may be used to drive a
differential IF signal interface or converted to a single-ended
signal through the use of a matching network or transformer.
When centered on the VPOS supply voltage, the outputs may
swing
±1 V.
The LO driver circuitry typically consumes 15 mA of current.
Two external resistors are used to set the mixer core current for
required performance resulting in a total current of 20 mA to
60 mA. This corresponds to power consumption of 100 mW to
300 mW with a single 5 V supply.
The AD8343 is fabricated on Analog Devices' proprietary, high-
performance 25 GHz silicon bipolar IC process. The AD8343 is
available in a 14-lead TSSOP package. It operates over a 40
°C
to +85
°C temperature range. A device-populated evaluation
board is available to facilitate device matching.
REV. 0
2
AD8343SPECIFICATIONS
BASIC OPERATING CONDITIONS
Parameter
Conditions
Figure
Min
Typ
Max
Unit
INPUT INTERFACE (INPP, INPM)
Differential Open Emitter
DC Bias Voltage
Internally Generated
1.1
1.2
1.3
V
Operating Current Each Input (I
O
)
Current Set by R3, R4
24
5
16
20
mA
Value of Bias Setting Resistor
1
1% Bias Resistors; R3, R4
24
68.1
Port Differential Impedance
f = 50 MHz; R3 and R4 = 68.1
9
2.7 + j 6.8
OUTPUT INTERFACE (OUTP, OUTM)
Differential Open Collector
DC Bias Voltage
Externally Applied
4.5
5
5.5
V
Voltage Swing
1.65
V
S
± 1
V
S
+ 2
V
Operating Current Each Output
Same as Input Current
I
O
mA
Port Differential Impedance
f = 50 MHz
12
900 j 77
LO INTERFACE (LOIP, LOIM)
Differential Common Base Stage
DC Bias Voltage
2
Internally Generated; Port
300
360
450
mV
Typically AC-Coupled
LO Input Power
50
Impedance
17
12
10
3
dBm
Port Differential Return Loss
16
10
dB
POWER-DOWN INTERFACE (PWDN)
PWDN Threshold
Assured ON
V
S
1.5
V
Assured OFF
V
S
0.5
V
PWDN Response Time
3
Time from Device ON to OFF
4
2.2
µs
Time from Device OFF to ON
5
500
ns
PWDN Input Bias Current
PWDN = 0 V (Device ON)
85
195
µA
PWDN = 5 V (Device OFF)
0
µA
POWER SUPPLY
Supply Voltage Range
4.5
5.0
5.5
V
Total Quiescent Current
R3 and R4 = 68.1
24
50
60
mA
Over Temperature
75
mA
Powered-Down Current
V
S
= 5.5 V
20
95
µA
V
S
= 4.5 V
6
15
µA
Over Temperature, V
S
= 5.5 V
50
150
µA
NOTES
1
The balance in the bias current in the two legs of the mixer input may be important in applications were a low feedthrough of the LO is critical.
2
This voltage is proportional to absolute temperature (PTAT). Reference section on DC-Coupling the LO for more information regarding this interface.
3
Response time until device meets all specified conditions.
Specifications subject to change without notice.
(V
S
= 5.0 V, T
A
= 25 C)
REV. 0
AD8343
3
Table I. Typical AC Performance
(V
S
= 5.0 V, T
A
= 25 C; See Figure 24 and Tables III Through V.)
Input 1 dB
Input Frequency
Output Frequency Conversion Gain
SSB Noise Figure
Input IP3
Compression Point
(MHz)
(MHz)
(dB)
(dB)
(dBm)
(dBm)
RECEIVER CHARACTERISTICS
400
70
5.6
10.5
20.5
3.3
900
170
3.6
11.4
19.4
3.6
1900
170
7.1
14.1
16.5
2.8
2400
170
6.8
15.3
14.5
2.1
2400
425
5.4
16.2
16.5
2.2
TRANSMITTER CHARACTERISTICS
150
900
7.5
17.9
18.1
1.9
150
1900
0.25
16.0
13.4
0.8
Table II. Typical Isolation Performance
(V
S
= 5.0 V, T
A
= 25 C; See Figure 24 and Tables III Through V.)
Input Frequency
Output Frequency LO to Output
2
LO to Output
3
LO to Output
Input to Output
(MHz)
(MHz)
Leakage (dBm)
Leakage (dBm)
Leakage (dBm)
Leakage (dBm)
RECEIVER CHARACTERISTICS
400
70
40.1
51.0
44.0
62.4
900
170
44.4
35.5
< 75.0
56.9
1900
170
65.6
38.3
73.3
65.7
2400
170
66.7
44.4
< 75.0
73.7
2400
425
51.1
49.4
< 75.0
52.3
TRANSMITTER CHARACTERISTICS
150
900
27.6
< 75 dBm
< 75 dBm
35.3
150
1900
< 75 dBm
< 75 dBm
< 75 dBm
69.7
NOTE: Low-side LO injection used for typical performance.
ABSOLUTE MAXIMUM RATINGS
1
VPOS Quiescent Voltage . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
OUTP, OUTM Quiescent Voltage . . . . . . . . . . . . . . . . 5.5 V
INPP, INPM Voltage Differential . . . . . . . . . . . . . . . 500 mV
Internal Power Dissipation (TSSOP)
2
. . . . . . . . . . . . 320 mW
JA
(TSSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
°C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125
°C
Operating Temperature Range . . . . . . . . . . . 40
°C to +85°C
Storage Temperature Range . . . . . . . . . . . . 65
°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300
°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may effect device reliability.
2
A portion of the device power is dissipated by the external bias resistors R3 and R4.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD8343ARU
RU-14
AD8343ARU-REEL
40
°C to +85°C
14-Lead Plastic TSSOP
13" Tape and Reel
AD8343ARU-REEL7
7" Tape and Reel
AD8343-EVAL
Evaluation Board
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
14
13
12
11
10
9
8
1
2
3
4
5
6
7
COMM
AD8343
INPP
INPM
DCPL
VPOS
PWDN
COMM
COMM
OUTP
OUTM
COMM
LOIP
LOIM
COMM
REV. 0
AD8343
4
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8343 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN FUNCTION DESCRIPTIONS
TSSOP
Name
Function
Simplified Interface Schematic
2, 3
INPP/INPM
Differential input pins. Need to be dc-
biased; typically ac-coupled.
12, 13
OUTP/OUTM
Open collector differential output pins.
Need to be ac-coupled and dc-biased.
9, 10
LOIP/LOIM
Differential local oscillator (LO) input pins.
Typically ac-coupled.
6
PWDN
Power-down interface. Connect pin to
ground for normal operating mode. Connect
pin to supply for power-down mode.
4
DCPL
Bias rail decoupling capacitor connection
for LO Driver.
5
VPOS
Positive supply voltage (V
S
), 4.5 V to 5.5 V.
Ensure adequate supply bypassing for proper
device operation as shownin Figure 24.
1, 7, 8,
COMM
Connect to low impedance circuit ground.
11, 14
VPOS
5V
DC
LOIP
LOIM
OUTP
5V
DC
OUTM
5V
DC
INPP
INPM
VPOS
5V
DC
1.2V
DC
1.2V
DC
VPOS
5V
DC
LOIP
LOIM
400
VBIAS
360mV
DC
360mV
DC
400
VPOS
5V
DC
PWDN
25k
BIAS
CELL
TO
MIXER
CORE
R1
10
DCPL
VPOS
LOIP
LOIM
2V
DC
360mV
DC
360mV
DC
BIAS
CELL
LO
BUFFER
REV. 0
CONVERSION GAIN dB
60
0
5.37
PERCENTAGE
50
40
30
20
10
MEAN: 5.57dB
5.42
5.47
5.52
5.57
5.62
5.67
5.72
TPC 1. Gain Histogram f
IN
= 400 MHz, f
OUT
= 70 MHz
INPUT IP3 dBm
0
19.9
PERCENTAGE
25
20
15
10
5
MEAN: 20.5dBm
20.0 20.1 20.2 20.3 20.4 20.5 20.6 20.7 20.8 20.9 21.0
TPC 2. Input IP3 Histogram f
IN
= 400 MHz, f
OUT
= 70 MHz
INPUT 1dB COMPRESSION POINT dBm
45
0
3.24
PERCENTAGE
40
35
30
25
20
15
10
5
MEAN: 3.31dBm
60
55
50
3.26
3.28
3.30
3.32
3.34
3.36
3.38
TPC 3. Input 1 dB Compression Point Histogram
f
IN
= 400 MHz, f
OUT
= 70 MHz
TEMPERATURE C
10
4
40
CONVERSION GAIN
dB
9
8
7
6
5
0
20
40
60
80
20
TPC 4. Gain Performance Over Temperature
f
IN
= 400 MHz, f
OUT
= 70 MHz
TEMPERATURE C
24
40
INPUT IP3
dBm
22
21
20
19
18
0
20
40
60
80
20
17
16
15
23
TPC 5. Input IP3 Performance Over Temperature
f
IN
= 400 MHz, f
OUT
= 70 MHz
TEMPERATURE C
5.0
2.0
40
INPUT 1dB COMPRESSION POINT
dBm
4.5
4.0
3.5
3.0
2.5
0
20
40
60
80
20
TPC 6. Input 1 dB Compression Point Performance Over
Temperature (f
IN
= 400 MHz, f
OUT
= 70 MHz )
Typical Performance CharacteristicsAD8343
5
RECEIVER CHARACTERISTICS (f
IN
= 400 MHz, f
OUT
= 70 MHz, f
LO
= 330 MHz [Figure 24, Tables III and IV])
REV. 0
AD8343
6
CONVERSION GAIN dB
0
3.45
PERCENTAGE
35
30
25
20
15
10
5
MEAN: 3.63dB
3.40
3.50
3.55
3.60
3.65
3.70
3.75
3.80
3.85
TPC 7. Gain Histogram f
IN
= 900 MHz, f
OUT
= 170 MHz
20.4
INPUT IP3 dBm
0
18.2
PERCENTAGE
30
20
10
2
MEAN: 19.4dBm
8
6
4
12
14
16
18
22
24
26
28
18.4 18.6 18.8 19.0 19.2 19.4 19.6 19.8 20.0 20.2
TPC 8. Input IP3 Histogram f
IN
= 900 MHz, f
OUT
= 170 MHz
INPUT 1dB COMPRESSION POINT dBm
30
0
3.52
PERCENTAGE
28
26
24
22
20
2
MEAN: 3.62dBm
18
16
14
12
10
9
6
4
3.54
3.56
3.58
3.60
3.62
3.64
3.66
3.68
3.70
3.72
TPC 9. Input 1 dB Compression Point Histogram
f
IN
= 900 MHz, f
OUT
= 170 MHz
RECEIVER CHARACTERISTICS (f
IN
= 900 MHz, f
OUT
= 170 MHz, f
LO
= 730 MHz [Figure 24, Tables III and IV])
TEMPERATURE C
6
0
40
CONVERSION GAIN
dB
5
4
3
2
1
0
20
40
60
80
20
TPC 10. Gain Performance Over Temperature
f
IN
= 900 MHz, f
OUT
= 170 MHz
TEMPERATURE C
23
15
40
INPUT IP3
dBm
22
21
20
19
16
0
20
40
60
80
20
18
17
TPC 11. Input IP3 Performance Over Temperature
f
IN
= 900 MHz, f
OUT
= 170 MHz
TEMPERATURE C
5.0
2.0
40
INPUT 1dB COMPRESSION POINT
dBm
4.5
4.0
3.5
3.0
2.5
0
20
40
60
80
20
TPC 12. Input 1 dB Compression Point Performance
Over Temperature f
IN
= 900 MHz, f
OUT
= 170 MHz
REV. 0
AD8343
7
CONVERSION GAIN dB
0
6.80
PERCENTAGE
28
26
24
22
20
10
2
6.75
4
6
8
18
16
14
12
6.90
6.85
7.00
6.95
7.10
7.05
7.20
7.15
7.30
7.25
MEAN: 7.09dB
TPC 13. Gain Histogram f
IN
= 1900 MHz, f
OUT
= 170 MHz
18.5
INPUT IP3 dBm
0
14.0
PERCENTAGE
45
10
5
15
20
25
30
35
40
14.5
15.0
15.5
16.0
16.5
17.0
17.5
18.0
MEAN: 16.54dBm
TPC 14. Input IP3 Histogram f
IN
= 1900 MHz,
f
OUT
= 170 MHz
INPUT 1dB COMPRESSION POINT dBm
50
0
2.60
PERCENTAGE
45
40
35
30
25
5
20
15
10
2.65
2.70
2.75
2.80
2.85
2.90
2.95
3.00
3.05
MEAN: 2.8dBm
TPC 15. Input 1 dB Compression Point Histogram
f
IN
= 1900 MHz, f
OUT
= 170 MHz
TEMPERATURE C
10
4
40
CONVERSION GAIN
dB
9
8
7
6
5
0
20
40
60
80
20
TPC 16. Gain Performance Over Temperature
f
IN
= 1900 MHz, f
OUT
= 170 MHz
TEMPERATURE C
18
40
INPUT IP3
dBm
17
16
15
14
13
0
20
40
60
80
20
12
11
10
TPC 17. Input IP3 Performance Over Temperature
f
IN
= 1900 MHz, f
OUT
= 170 MHz
TEMPERATURE C
5.0
2.0
40
INPUT 1dB COMPRESSION POINT
dBm
4.5
4.0
3.5
3.0
2.5
0
20
40
60
80
20
TPC 18. Input 1 dB Compression Point Performance
Over Temperature f
IN
= 1900 MHz, f
OUT
= 170 MHz
RECEIVER CHARACTERISTICS (f
IN
= 1900 MHz, f
OUT
= 170 MHz, f
LO
= 1730 MHz [Figure 24, Tables III and IV])
REV. 0
AD8343
8
CONVERSION GAIN dB
0
6.0
PERCENTAGE
40
35
30
20
15
10
5
5.8
6.2
6.4
6.6
6.8
7.0
7.2
7.4
7.6
25
MEAN: 6.79dB
TPC 19. Gain Histogram f
IN
= 2400 MHz, f
OUT
= 170 MHz
INPUT IP3 dBm
0
13.0
PERCENTAGE
35
25
10
5
15
20
30
13.2 13.4 13.6 13.8 14.0 14.2 14.4 14.6 14.8 15.0 15.2 15.4 15.6
MEAN: 14.46dBm
TPC 20. Input IP3 Histogram f
IN
= 2400 MHz, f
OUT
= 170 MHz
INPUT 1dB COMPRESSION POINT dBm
45
0
1.90
PERCENTAGE
40
35
30
25
20
15
10
5
1.95
2.00
2.05
2.10
2.15
2.20
2.25
2.30
2.35
2.40
INPUT: 2.11dBm
TPC 21. Input 1 dB Compression Point Histogram
f
IN
= 2400 MHz, f
OUT
= 170 MHz
TEMPERATURE C
10
4
40
CONVERSION GAIN
dB
9
8
7
6
5
0
20
40
60
80
20
TPC 22. Gain Performance Over Temperature
f
IN
= 2400 MHz, f
OUT
= 170 MHz
TEMPERATURE C
18
40
INPUT IP3
dBm
17
16
15
14
13
0
20
40
60
80
20
12
11
10
TPC 23. Input IP3 Performance Over Temperature
f
IN
= 2400 MHz, f
OUT
= 170 MHz
TEMPERATURE C
3.0
0
40
INPUT 1dB COMPRESSION POINT
dBm 2.5
2.0
1.5
1.0
0.5
0
20
40
60
80
20
TPC 24. Input 1 dB Compression Point Performance Over
Temperature f
IN
= 2400 MHz, f
OUT
= 170 MHz
RECEIVER CHARACTERISTICS (f
IN
= 2400 MHz, f
OUT
= 170 MHz, f
LO
= 2230 MHz [Figure 24, Tables III and IV])
REV. 0
AD8343
9
CONVERSION GAIN dB
0
4.4
PERCENTAGE
24
22
20
18
16
14
2
4.2
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
6.6
12
10
8
6
4
6.2
6.4
MEAN: 5.40dB
TPC 25. Gain Histogram f
IN
= 2400 MHz, f
OUT
= 425 MHz
INPUT IP3 dBm
0
14.2
PERCENTAGE
22
12
2
8
6
4
10
14
16
18
20
15.4 15.6 15.8 16.0 16.2 16.4 16.6 16.8
17.2 17.4 17.6 17.8
MEAN: 16.50dBm
17.0
18.0
15.2
15.0
TPC 26. Input IP3 Histogram f
IN
= 2400 MHz,
f
OUT
= 425 MHz
MEAN: 2.22dBm
INPUT 1dB COMPRESSION POINT dBm
0
2.05
PERCENTAGE
65
60
55
50
45
40
5
2.00
2.10
2.15
2.20
2.25
2.30
2.35
2.40
2.45
2.50
35
30
25
20
15
10
TPC 27. Input 1 dB Compression Point Histogram
f
IN
= 2400 MHz, f
OUT
= 425 MHz
RECEIVER CHARACTERISTICS (f
IN
= 2400 MHz, f
OUT
= 425 MHz, f
LO
= 1975 MHz [Figure 24, Tables III and IV])
TEMPERATURE C
10
4
40
CONVERSION GAIN
dB
9
8
7
6
5
0
20
40
60
80
20
TPC 28. Gain Performance Over Temperature
f
IN
= 2400 MHz, f
OUT
= 425 MHz
TEMPERATURE C
18
40
INPUT IP3
dBm
17
16
15
14
13
0
20
40
60
80
20
12
11
10
TPC 29. Input IP3 Performance Over Temperature
f
IN
= 2400 MHz, f
OUT
= 425 MHz
TEMPERATURE C
3.0
0
40
INPUT 1dB COMPRESSION POINT
dBm
2.5
2.0
1.5
1.0
0.5
0
20
40
60
80
20
TPC 30. Input 1 dB Compression Point Performance Over
Temperature f
IN
= 2400 MHz, f
OUT
= 425 MHz
REV. 0
AD8343
10
TRANSMIT CHARACTERISTICS (f
IN
= 150 MHz, f
OUT
= 900 MHz, f
LO
= 750 MHz [Figure 24, Tables III and IV])
CONVERSION GAIN dB
0
7.20
PERCENTAGE
35
30
25
20
15
10
5
7.70
MEAN: 7.49dB
7.25
7.30
7.35
7.40
7.45
7.50
7.55
7.60
7.65
TPC 31. Gain Histogram f
IN
= 150 MHz, f
OUT
= 900 MHz
INPUT IP3 dBm
24
0
PERCENTAGE
22
20
18
16
14
12
10
2
MEAN: 18.1dBm
17.85
17.8
4
6
8
17.9 17.95 18.0 18.05 18.1 18.15 18.2 18.25 18.3 18.35 18.4 18.45
TPC 32. Input IP3 Histogram f
IN
= 150 MHz, f
OUT
= 900 MHz
INPUT 1dB COMPRESSION POINT dBm
24
0
PERCENTAGE
22
20
18
16
14
12
10
2
MEAN: 1.9dBm
1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20
1.55
4
6
8
TPC 33. Input 1 dB Compression Point Histogram
f
IN
= 150 MHz, f
OUT
= 900 MHz
TEMPERATURE C
10
4
40
CONVERSION GAIN
dB
9
8
7
6
5
0
20
40
60
80
20
TPC 34. Gain Performance Over Temperature
f
IN
= 150 MHz, f
OUT
= 900 MHz
TEMPERATURE C
20
40
INPUT IP3
dBm
19
18
17
16
15
0
20
40
60
80
20
14
13
12
TPC 35. Input IP3 Performance Over Temperature
f
IN
= 150 MHz, f
OUT
= 900 MHz
TEMPERATURE C
3.0
0.0
40
INPUT 1dB COMPRESSION POINT
dBm 2.5
2.0
1.5
1.0
0.5
0
20
40
60
80
20
TPC 36. Input 1 dB Compression Point Performance Over
Temperature f
IN
= 150 MHz, f
OUT
= 900 MHz
REV. 0
AD8343
11
TRANSMIT CHARACTERISTICS (f
IN
= 150 MHz, f
OUT
= 1900 MHz, f
LO
= 1750 MHz [Figure 24, Tables III and IV])
CONVERSION GAIN dB
0
1.0 0.8
PERCENTAGE
40
35
30
25
20
15
10
5
MEAN: 0.25dB
0.6 0.4 0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
TPC 37. Gain Histogram f
IN
= 150 MHz, f
OUT
= 1900 MHz
INPUT IP3 dBm
45
0
10.5
PERCENTAGE
40
35
30
25
20
15
10
5
MEAN: 13.4dBm
50
11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 17.0
TPC 38. Input IP3 Histogram f
IN
= 150 MHz,
f
OUT
= 1900 MHz
INPUT 1dB COMPRESSION POINT dBm
45
0
1
0.5
PERCENTAGE
40
35
30
25
20
15
10
5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
MEAN: 0.79dBm
TPC 39. Input 1 dB Compression Point Histogram
f
IN
= 150 MHz, f
OUT
= 1900 MHz
TEMPERATURE C
5
2
40
CONVERSION GAIN
dB
3
2
1
0
1
0
20
40
60
80
20
4
TPC 40. Gain Performance Over Temperature
f
IN
= 150 MHz, f
OUT
= 1900 MHz
TEMPERATURE C
18
9
40
INPUT IP3
dBm
17
16
15
14
13
0
20
40
60
80
20
12
11
10
TPC 41. Input IP3 Performance Over Temperature
f
IN
= 150 MHz, f
OUT
= 1900 MHz
TEMPERATURE C
2.0
1.0
40
INPUT 1dB COMPRESSION POINT
dBm
1.5
1.0
0.5
0
0.5
0
20
40
60
80
20
TPC 42. Input 1 dB Compression Point Performance Over
Temperature f
IN
= 150 MHz, f
OUT
= 1900 MHz
REV. 0
AD8343
12
CIRCUIT DESCRIPTION
The AD8343 is a mixer intended for high-intercept applications.
The signal paths are entirely differential and dc-coupled to permit
high-performance operation over a broad range of frequencies;
the block diagram (Figure 1) shows the basic functional blocks.
The bias cell provides a PTAT (proportional to absolute tem-
perature) bias to the LO Driver and Core. The LO Driver
consists of a three-stage limiting differential amplifier that pro-
vides a very fast (almost square-wave) drive to the bases of the
core transistors.
The AD8343 core utilizes a standard architecture in which the
signal inputs are directly applied to the emitters of the transistors in
the cell (Figure 7). The bases are driven by the hard-limited LO
signal that directs the transistors to steer the input currents into
periodically alternating pairs of output terminals, thus providing
the periodic polarity reversal that effectively multiplies the signal
by a square wave of the LO frequency.
BIAS
AD8343
VPOS
DCPL
PWDN
LOIP
LOIM
INPP
INPM
OUTP
OUTM
COMM
MIXER
CORE
LO
DRIVER
Q1 Q2
Q3 Q4
Figure 1. Topology
To illustrate this functionality, when LOIP is positive, Q1 and
Q4 are turned ON, and Q2 and Q3 are turned OFF. In this
condition Q1 connects I
INPP
to OUTM and Q4 connects I
INPM
to OUTP. When LOIP is negative the roles of the transistors
reverse, steering I
INPP
to OUTP and I
INPM
to OUTM. Isolation
and gain are possible because at any instant the signal passes
through a common-base transistor amplifier pair.
Multiplication is the essence of frequency mixing; an ideal multi-
plier would make an excellent mixer. The theory is expressed in
the following trigonometric identity:
sin(
sig
t)sin(
LO
t) = 1/2 [cos(
sig
t
LO
t) cos(
sig
t +
LO
t)]
This states that the product of two sine-wave signals of different
frequencies is a pair of sine waves at frequencies equal to the
sum and difference of the two frequencies being multiplied.
Unfortunately, practical implementations of analog multipliers
generally make poor mixers because of imperfect linearity and
because of the added noise that invariably accompanies attempts
to improve linearity. The best mixers to date have proven to be
those that use the LO signal to periodically reverse the polarity
of the input signal.
In this class of mixers, frequency conversion occurs as a result
of multiplication of the signal by a square wave at the LO
frequency. Because a square wave contains odd harmonics in
addition to the fundamental, the signal is effectively multiplied
by each frequency component of the LO. The output of the
mixer will therefore contain signals at F
LO
± F
sig
, 3
× F
LO
± F
sig
,
5
× F
LO
± F
sig
, 7
× F
LO
± F
sig
, etc. The amplitude of the compo-
nents arising from signal multiplication by LO harmonics falls
off with increasing harmonic order because the amplitude of a
square wave's harmonics falls off.
An example of this process is illustrated in Figure 2. The first
pane of this figure shows an 800 MHz sinusoid intended to
represent an input signal. The second pane contains a square
wave representing an LO signal at 600 MHz which has been
hard-limited by the internal LO driver. The third pane shows
the time domain representation of the output waveform and the
fourth pane shows the frequency domain representation. The
two strongest lines in the spectrum are the sum and difference
frequencies arising from multiplication of the signal by the LO's
fundamental frequency. The weaker spectral lines are the result
of the multiplication of the signal by various harmonics of the
LO square wave.
FREQUENCY
DOMAIN
LOCAL
OSCILLATOR
TIME
DOMAIN
SIGNAL
SIG LO
SIG LO
FREQUENCY
SIG
LO
SIG
LO
3
LO
SIG
5
LO
SIG
3
LO
SIG
7
LO
SIG
5
LO
SIG
Figure 2. Signal Switching Characteristics of the AD8343
REV. 0
AD8343
13
DC INTERFACES
Biasing and Decoupling (VPOS, DCPL)
VPOS is the power supply connection for the internal bias cir-
cuit and the LO driver. This pin should be closely bypassed to
GND with a capacitor in the range of 0.01
µF to 0.1 µF. The
DCPL pin provides access to an internal bias node for noise
bypassing purposes. This node should be bypassed to COMM
with 0.1
µF.
Power-Down Interface (PWDN)
The AD8343 is active when the PWDN pin is held low; other-
wise the device enters a low-power state as shown in Figure 3.
PWDN SWEPT
FROM BOTH
3V TO 5V
AND
5V TO 3V
PWDN VOLTAGE Volts
0
3.0
3.5
DEVICE CURRENT
mA
4.0
4.5
5.0
5
10
15
20
25
30
35
40
45
Figure 3. Bias Current vs. PWDN Voltage
To assure full power-down, the PWDN voltage should be within
0.5 V of the supply voltage at VPOS. Normal operation requires
that the PWDN pin be taken at least 1.5 V below the supply
voltage. The PWDN pin sources about 100
µA when pulled to
GND (refer to Pin Function Descriptions). It is not advisable to
leave the pin floating when the device is to be disabled; a resis-
tive pull-up to VPOS is the minimum suggestion.
The AD8343 requires about 2.5
µs to turn OFF when PWDN is
asserted; turn ON time is about 500 ns. Figures 4 and 5 show
typical characteristics (they will vary with bypass component
values). Figure 6 shows the test configuration used to acquire
these waveforms.
2
200nV
1.00V
CH2
M
500ns CH2
4.48V
1
CH1
Figure 4. PWDN Response Time Device ON to OFF
2
200nV
1.00V
CH2
M
100ns CH2
4.48V
1
CH1
Figure 5. PWDN Response Time Device OFF to ON
1nH
0.1 F
VPOS
0.1 F
14
13
12
11
10
9
8
1
2
3
4
5
6
7
COMM
AD8343
INPP
INPM
DCPL
VPOS
PWDN
COMM
COMM
OUTP
OUTM
COMM
LOIP
LOIM
COMM
MATCHING
NETWORK AND
TRANSFORMER
TRANSFORMER
HP8130
PULSE
GENERATOR
HP8648C
SIGNAL
GENERATOR
TEKTRONIX
TDS694C
OSCILLOSCOPE
RF INPUT
1740MHz
IF OUTPUT
170MHz
LO INPUT
1570MHz
MATCHING
NETWORK AND
TRANSFORMER
HP8648C
SIGNAL
GENERATOR
TRIGGER
Figure 6. PWDN Response Time Test Schematic
AC INTERFACES
Because of the AD8343's wideband design, there are several
points to consider in its ac implementation; the Basic AC
Signal Connection diagram shown in Figure 7 summarizes
these points. The input signal undergoes a single-ended-to-
differential conversion and is then reactively matched to the
impedance presented by the emitters of the core. The matching
network also provides bias currents to these emitters. Similarly,
the LO input undergoes a single-ended-to-differential transfor-
mation before it is applied to the 50
differential LO port. The
differential output signal currents appear at high-impedance
collectors and may be reactively matched and converted to a
single-ended signal.
REV. 0
AD8343
14
SINGLE-ENDED-
TO-DIFFERENTIAL
CONVERSION
INPUT MATCHING
NETWORK
CORE BIAS NETWORK
SINGLE-ENDED-
TO-DIFFERENTIAL
CONVERSION
SINGLE-ENDED
INPUT SIGNAL
SINGLE-ENDED
LO INPUT SIGNAL
BIAS
CELL
CORE
AD8343
VPOS
DCPL
PWDN
LOIP
LOIM
INPP
INPM
OUTM
OUTP
COMM
LO
DRIVER
SINGLE-ENDED
OUTPUT SIGNAL
OUTPUT MATCHING
NETWORK
CORE BIAS
NETWORK
DIFFERENTIAL-
TO-
SINGLE-ENDED
CONVERSION
Figure 7. Basic AC Signal Connection Diagram
INPUT INTERFACE (INPP AND INPM)
Single-Ended-to-Differential Conversion
The AD8343 is designed to accept differential input signals for
best performance. While a single-ended input can be applied,
the signal capacity is reduced by 6 dB. Further, there would be
no cancellation of even-order distortion arising from the nonlin-
ear input impedances, so the effective signal handling capacity
will be reduced even further in distortion-sensitive situations.
That is, the intermodulation intercepts are degraded.
For these reasons it is strongly recommended that differential
signals be presented to the AD8343's input. In addition to com-
mercially available baluns, there are various discrete and printed
circuit elements that can produce the required balanced wave-
forms and impedance match (i.e., rat-race baluns). These
alternate circuits can be employed to further reduce the compo-
nent cost of the mixer.
Baluns implemented in transmission line form (also known as
common-mode chokes) are useful up to frequencies of around
1 GHz, but are often excessively lossy at the highest frequencies
that the AD8343 can handle. M/A-Com manufactures these
baluns with their ETC line. Murata produces a true surface-
mount balun with their LDB20C series. Coilcraft and Toko are
also manufacturers of RF baluns.
Input Matching Considerations
The design of the input matching network should be undertaken
with two goals in mind: matching the source impedance to the
input impedance of the AD8343 and providing a dc bias current
path for the bias setting resistors.
The maximum power transfer into the device will occur when
there is a conjugate impedance match between the signal source
and the input of the AD8343. This match can be achieved with
the differential equivalent of the classic "L" network, as illustrated
in Figure 8. The figure gives two examples of the transformation
from a single-ended "L" network to its differential counterpart.
The design of "L" matching networks is adequately covered in
texts on RF amplifier design (for example: "Microwave Transis-
tor Amplifiers" by Guillermo Gonzalez).
L1
C1
L1/2
C1
L1/2
C2
L2
L2
2C2
2C2
SINGLE-ENDED
DIFFERENTIAL
Figure 8. Single-Ended-to-Differential Transformation
Figure 9 shows the differential input impedance of the AD8343
at the pins of the device. The two measurements shown in the
figure are for two different core currents set by resistors R3 and
R4; the real value impedance shift is caused by the change in tran-
sistor r
E
due to the change in current. The standard S parameter
files are available at the ADI web site (www.analog.com).
FREQUENCY (50MHz 2500MHz)
50MHz
500MHz
1000MHz
1500MHz
2500MHz
134
68
Figure 9. Input Differential Impedance (INPP, INPM) for
Two Values of R3 and R4
Figure 9 provides a reasonable starting point for the design of
the network. However, the particular board traces and pads will
transform the input impedance at frequencies in excess of about
500 MHz. For this reason it is best to make a differential input
impedance measurement at the board location where the match-
ing network will be installed, as a starting point for designing an
accurate matching network.
Differential impedance measurement is made relatively easy
through the use of a technique presented in an article by Lutz
Konstroffer in RF Design, January 1999, entitled "Finding the
Reflection Coefficient of a Differential One-Port Device." This
article presents a mathematical formula for converting from a
two-port single-ended measurement to differential impedance.
A full two-port measurement is performed using a vector network
analyzer with Port 1 and Port 2 connected to the two differential
inputs of the device at the desired measurement plane. The two-
port measurement results are then processed with Konstroffer's
formula (following), which is straightforward and can be imple-
mented through most RF design packages that can read and
analyze network analyzer data.
REV. 0
AD8343
15
s
S
S
S
S
S
S
S
S
S
S
S
S
S
S
=
×
-
(
)
-
-
(
)
+ -
-
(
)
+
- ×
(
)
-
(
)
-
-
(
)
+ -
-
(
)
+
(
)
2
11
21 1
22
12
1
11
21 1
22
2
12
2
21 1
22
12
1
11
21 1
22
This measurement can also be made using the ATN 4000 Series
Multiport Network Analyzer. This instrument, and accompa-
nying software, is capable of directly producing differential
measurements.
At low frequencies and I
O
= 16 mA, the differential input imped-
ance seen at ports INPP and INPM of the AD8343 is low
(~5
in series with parasitic inductances that total about 3 nH).
Because of this low value of impedance, it may be beneficial to
choose a transformer-type balun that can also perform all or
part of the real value impedance transformation. The turns ratio
of the transformer will remove some of the matching burden
from the differential "L" network and potentially lead to
wider bandwidth.
At frequencies above 1 GHz, the real part of the input imped-
ance rises markedly and it becomes more attractive to use a 1:1
balun and rely on the "L" network for the entire impedance
transformation.
In order to obtain the lowest distortion, the inputs of the AD8343
should be driven through external ballast resistors. At low frequen-
cies (up to perhaps 200 MHz) about 5
per side is appropriate;
above about 400 MHz, 10
per side is better. The specified RF
performance values for the AD8343 apply with these ballast
resistors in use. These resistors improve linearity because their
linear ac voltage drop partially swamps the nonlinear voltage swing
occurring on the emitters.
In cases where the use of a lossy balun is unavoidable, it may be
worthwhile to perform simultaneous matching on both the input
and output sides of the balun. The idea is to independently
characterize the balun as a two-port device and then arrange a
simultaneous conjugate match for it. Unfortunately there seems
to be no good way to determine the benefit this approach may
offer in any particular case; it remains necessary to characterize
the balun and then design and simulate appropriate matching
networks to make an optimal decision. One indication that such
effort may be worthwhile is the discovery that the adjustment of
a post-balun-only matching network for best gain, differs apprecia-
bly from that which produces best return loss at the balun's input.
A better tactic may be to try a different approach for the balun,
either purchasing a different balun or designing a discrete network.
For more information on performing the input match, see "A
Step-by-Step Approach to Impedance Matching" in the section
covering the AD8343 evaluation board.
Input Biasing Considerations
The mixer core bias current of the AD8343 is adjustable from
less than 5 mA to a safe maximum of 20 mA. It is important to
note that the reliability of the AD8343 will be compromised for
core currents set to higher than 20 mA. The AD8343 is tested
to ensure that a value of 68.1
± 1% will ensure safe operation.
Higher operating currents will reduce distortion and affect gain,
noise figure, and input impedance (Figures 10 and 11). As the
quiescent current is increased by a factor of N the real part of
the input impedance decreases by N. Assuming that a match is
maintained, the signal current increases by
N, but the signal
voltage decreases by
N, which exercises a smaller portion of the
nonlinear VI characteristic of the common base connected
mixer core transistors and results in lower distortion.
R3/R4
0
20
CONVERSION GAIN AND NOISE FIGURE
dB
16
12
8
4
200
100
120
60
80
40
140
160
180
90
80
70
60
50
40
30
20
10
0
INPUT RF = 900MHz
OUTPUT IF = 170MHz
LO LOW SIDE INJECTION
NOISE FIGURE
GAIN
TOTAL SUPPLY CURRENT
TOTAL SUPPLY CURRENT
mA
20
100
Figure 10. Effect of R3/R4 Value on Gain and Noise Figure
R3 AND R4
0
20
INPUT IP3
dBm AND P1dB
dBm
20
15
10
5
200
100
120
60
80
40
140
160
180
90
80
70
60
50
40
30
20
10
0
INPUT RF = 900MHz
OUTPUT IF = 170MHz
LO LOW SIDE INJECTION
INPUT IP3
P1dB
TOTAL SUPPLY CURRENT
TOTAL SUPPLY CURRENT
mA
25
Figure 11. Effect of R3/R4 Value on Input IP3 and Gain
Compression
At low frequencies where the magnitude of the complex input
impedance is much smaller than the bias resistor values, adequate
biasing can be achieved simply by connecting a resistor from
each input to GND. The input terminals are internally biased at
1.2 V dc (nominal), so each resistor should have a resistance
value calculated as R
BIAS
= 1.2/I
BIAS
. The resistor values should
be well matched in order to maintain full LO to output isola-
tion; 1% tolerance resistors are recommended.
At higher frequencies where the input impedance of the AD8343
rises, it is beneficial to insert an inductor in series between each
bias resistor and the corresponding input pin in order to mini-
mize signal shunting (Figure 24). Practical considerations will
limit the inductive reactance to a few hundred ohms. The best
overall choice of inductor will be that value which places the
self-resonant frequency at about the upper end of the desired
input frequency range. Note that there is an RF stability con-
cern that argues in favor of erring on the side of too small an
inductor value; reference section on Input and Output Stability
Considerations. The Murata LQW1608A series of inductors
(0603 SMT package) offers values up to 56 nH before the self-
resonant frequency falls below 2.4 GHz.
REV. 0
AD8343
16
For optimal LO-to-Output isolation it is important not to con-
nect the dc nodes of the emitter bias inductors together in an
attempt to share a single bias resistor. Doing so will cause isola-
tion degradation arising from V
BE
mismatches of the transistors
in the core.
OUTPUT INTERFACE (OUTP, OUTM)
The output of the AD8343 comprises a balanced pair of open-
collector outputs. These should be biased to about the same
voltage as is connected to VPOS (see dc specifications table).
Connecting them to an appreciably higher voltage is likely to
result in conduction of the ESD protection network on signal
peaks, which would cause high distortion levels. On the other
hand, setting the dc level of the outputs too low is also likely to
result in poor device linearity due to collector-base capacitance
modulation or saturation of the core transistors.
Output Matching Considerations
The AD8343 requires a differential load for much the same
reasons that the input needs a differential source to achieve
optimal device performance. In addition, a differential load will
provide the best LO to output isolation and the best input to
output isolation.
At low output frequencies it is usually not appropriate to
arrange a conjugate match between the device output and the
load, even though doing so would maximize the small signal
conversion gain. This is because the output impedance at low
frequencies is quite high (a high resistance in parallel with a
small capacitance). Refer to Figure 12 for a plot of the differ-
ential output impedance measured at the device pins. This
data is available in standard file format at the ADI web site
(www.analog.com).
If a matching high impedance load is used, sufficient output
voltage swing will occur to cause output clipping even at rela-
tively low input levels, which constitutes a loss of dynamic range.
The linear range of voltage swing at each output pin is about
±1 volt from the supply voltage VPOS. A good compromise is to
provide a load impedance of about 500
between the output
pins at the desired output frequency (based on 15 mA to 20 mA
bias current at each input). At output frequencies below 500 MHz,
more output power can be obtained before the onset of gross
clipping by using a lower load impedance; however, both gain
and low order distortion performance will be degraded.
500MHz
1000MHz
1500MHz
2000MHz
50MHz
FREQUENCY (50MHz 2500MHz)
Figure 12. Output Differential Impedance (OUTP, OUTM)
The output load impedance should also be kept reasonably low
at the image frequency to avoid developing appreciable extra
voltage swing, which would again reduce dynamic range.
If maintaining a good output return loss is not required, a 10:1
(impedance) flux-coupled transformer may be used to present a
suitable load to the device and to provide collector bias via a center
tap as shown in Figure 21. At all but the lowest output frequen-
cies it becomes desirable to tune out the output capacitance of
the AD8343 by connecting an inductor between the output pins.
On the other hand, when a good output return loss is desired,
the output may be resistively loaded with a shunt resistance
between the output pins in order to set the real value of output
impedance. With selection of both the transformer's impedance
ratio and the shunting resistance as required, the desired total
load (~500
) will be achieved while optimizing both signal
transfer and output return loss.
At higher output frequencies the output conductance of the
device becomes higher (Figure 12), with the consequence
that above about 900 MHz it does become appropriate to
perform a conjugate match between the load and the AD8343's
output. The device's own output admittance becomes sufficient
to remove the threat of clipping from excessive voltage swing. Just
as for the input, it may become necessary to perform differential
output impedance measurements on your board layout to effec-
tively develop a good matching network.
Output Biasing Considerations
When the output single-ended-to-differential conversion takes
the form of a transformer whose primary winding is center-
tapped, simply apply VPOS to the tap, preferably through a
ferrite bead in series with the tap in order to avoid a common-
mode instability problem (reference section on Input and Output
Stability Considerations). Refer to Figure 21 for an example of
this network. The collector dc bias voltage should be nominally
equal to the supply voltage applied to Pin 5 (VPOS).
If a 1:1 transmission line balun is used for the output, it will be
necessary to bring in collector bias through separate inductors.
These inductors should be chosen to obtain a high impedance at
the RF frequency, while maintaining a suitable self-resonant
frequency. Refer to Figure 22 for an example of this network.
INPUT AND OUTPUT STABILITY CONSIDERATIONS
The differential configuration of the input and output ports of
the AD8343 raises the need to consider both differential and
common-mode RF stability of the device. Throughout the fol-
lowing stability discussion, common mode will be used to refer
to a signal that is referenced to ground. The equivalent common-
mode impedance will be the value of impedance seen from the
node under discussion to ground. The book "Microwave Tran-
sistor Amplifiers" by Guillermo Gonzalez also has an excellent
section covering stability of amplifiers.
The AD8343 is unconditionally stable for any differential im-
pedance, so device stability need not be considered with respect
to the differential terminations. However, the device is potentially
unstable (k factor is less than one) for some common-mode
impedances. Figures 13 and 14 plot the input and output
common-mode stability regions, respectively. Figure 15
shows the test equipment configuration to measure these
stability circles.
REV. 0
AD8343
17
The plotted stability circles in Figure 14 indicate that the guiding
principle for preventing stability problems due to common-mode
output loading is to avoid high-Q common-mode inductive load-
ing. This stability concern is of particular importance when the
output is taken from the device with a center-tapped transformer.
The common-mode inductance to the center tap, which arises
from imperfect coupling between the halves of the primary wind-
ing, produces an unstable common-mode loading condition.
Fortunately, there is a simple solution: insert a ferrite bead in
series with the center tap, then provide effective RF bypassing on
the power supply side of the bead. The bead should develop sub-
stantial impedance (tens of ohms) by the time a frequency of about
200 MHz is reached. The Murata BLM21P300S is a possible
choice for many applications.
50MHz
150MHz
FREQUENCY: 50MHz TO 2500MHz
INCREMENT: 100MHz
Figure 13. Common-Mode Input Stability Circles
150MHz
50MHz
FREQUENCY: 50MHz TO 2500MHz
INCREMENT: 100MHz
Figure 14. Common-Mode Output Stability Circles
1nH
0.1 F
VPOS
HP8753C
NETWORK ANALYZER
ATN-4111B
S PARAMETER TEST SET
HP-IB
ATN-4000 SERIES
MULTIPORT
TEST SYSTEM
0.1 F
14
13
12
11
10
9
8
1
2
3
4
5
6
7
COMM
AD8343
INPP
INPM
DCPL
VPOS
PWDN
COMM
COMM
OUTP
OUTM
COMM
LOIP
LOIM
COMM
BIAS
TEE
BIAS
TEE
BIAS
TEE
BIAS
TEE
Figure 15. Impedance and Stability Circle Test Schematic
In cases where a transmission line balun is used at the output,
the solution needs more exploration. After the differential imped-
ance matching network is designed, it is possible to measure
or simulate the common-mode impedance seen by the device.
This impedance should be plotted against the stability circles to
ensure stable operation. An alternate topology for the matching
network may be required if the proposed network produces an
unacceptable common-mode impedance.
For the device input, capacitive common-mode loading produces
an unstable circuit, particularly at low frequencies (Figure 13).
Fortunately, either type of single-ended-to-differential conver-
sion (transmission line balun or flux-coupled transformer) tends
to produce inductive loading, although some matching network
topologies and/or component values could circumvent this
desirable behavior. In general, a simulation of the common-mode
termination seen by the AD8343's input port should be plotted
against the input stability circles to check stability. This is especially
recommended if the single-ended-to-differential conversion is done
with a discrete component circuit.
LO Input Interface (LOIP, LOIM)
The LO terminals of the AD8343 are internally biased; connec-
tions to these terminals should include dc blocks, except as
noted below in the DC Coupling the LO section.
The differential LO input return loss (re 50
is presented in
Figure 16. As shown, this port has a typical differential return
loss of better than 9.5 dB (2:1 VSWR). If better return loss is
desired for this port, differential matching techniques can also
be applied.
REV. 0
AD8343
18
FREQUENCY (50MHz 2500MHz)
0
30
0
500
RETURN LOSS
dB
1000
1500
2000
2500
25
20
15
10
5
Figure 16. LO Input Differential Return Loss
At low LO frequencies, it is reasonable to drive the AD8343
with a single-ended LO, connecting the undriven terminal to
GND through a dc block. This will result in an input impedance
closer to 25
at low frequencies, which should be factored
into the design. At higher LO frequencies, differential drive
is recommended.
The suggested minimum LO power level is about 12 dBm. This
can be seen in Figure 17.
LO POWER dBm
0
40
CONVERSION GAIN
dB
4
3
2
1
20
10
30
25
20
15
10
5
NOISE FIGURE
0
NOISE FIGURE
dB
5
CONVERSION GAIN
INPUT RF = 900MHz
OUTPUT IF = 170MHz
LO LOW SIDE INJECTION
Figure 17. Gain and Noise Figure vs. LO Input Power
DC Coupling the LO
The AD8343's LO limiting amplifier chain is internally dc-
coupled. In some applications or experimental situations it is
useful to exploit this property. This section addresses some ways
in which to do it.
The LO pins are internally biased at about 360 mV with respect
to COMM. Driving the LO to either extreme requires injecting
several hundred microamps into one LO pin and extracting
about the same amount of current from the other. The incre-
mental impedance at each pin is about 25
, so the voltage level
on each pin is disturbed very little by the application of external
currents in that range.
Figure 18 illustrates how to drive the LO port with continuous
dc and also from standard ECL powered by 5.2 V.
ECL
BIAS
AD8343
VPOS
DCPL
PWDN
LOIP
LOIM
INPP
INPM
OUTM
OUTP
COMM
LO
DRIVER
5.2V
5.2V
390
1.2k
1.2k
390
3.6k
3.6k
+5V
5.2V
ECL
13k
CONTINUOUS
DC
1k
BIAS
AD8343
VPOS
DCPL
PWDN
LOIP
LOIM
INPP
INPM
OUTM
OUTP
COMM
LO
DRIVER
Figure 18. DC Interface to LO Port
A Step-by-Step Approach to Impedance Matching
The following discussion addresses, in detail, the matter of
establishing a differential impedance match to the AD8343.
This section will specifically deal with the input match, and
using side "A" of the evaluation board (Figure 23). An analo-
gous procedure would be used to establish a match to the
output if desired.
Step 1: Circuit Setup
In order to do this work the AD8343 must be powered up, driven
with LO; its outputs should be terminated in a manner that
avoids the common-mode stability problem as discussed in
the Input and Output Stability section. A convenient way to
deal with the output termination is to place ferrite chokes at
L3A and L4A and omit the output matching components
altogether.
It is also important to establish the means of providing bias
currents to the input pins because this network may have
unexpected loading effects and inhibit matching progress.
Step 2: Establish Target Impedance
This step is necessary when the single-ended-to-differential
network (input balun) does not produce a 50
output imped-
ance. In order to provide for maximum power transfer, the input
impedance of the matching network, loaded with the AD8343
input impedance (including ballast resistors), should be the conju-
gate of the output impedance of the single-ended-to-differential
network. This step is of particular importance when utilizing
transmission line baluns because the differential output imped-
ance of the input balun may differ significantly from what is
expected. Therefore, it is a good idea to make a separate mea-
surement of this impedance at the desired operating frequency
before proceeding with the matching of the AD8343.
REV. 0
AD8343
19
The idea is to make a differential measurement at the output of
the balun, with the single-ended port of the balun terminated in
50
. Again, there are two methods available for making this
measurement: use of the ATN Multiport Network Analyzer to
measure the differential impedance directly, or use of a standard
two-port network analyzer and Konstroffer's transformation
equation.
In order to utilize a standard two-port analyzer, connect the two
ports of the calibrated vector network analyzer (VNA) to the
balanced output pins of the balun, measure the two-port S
parameters, then use Konstroffer's formula to convert the two-
port parameters to one-port differential
.
s
S
S
S
S
S
S
S
S
S
S
S
S
S
S
=
×
-
(
)
-
-
(
)
+ -
-
(
)
+
- ×
(
)
-
(
)
-
-
(
)
+ -
-
(
)
+
(
)
2
11
21 1
22
12
1
11
21 1
22
2
12
2
21 1
22
12
1
11
21 1
22
Step 3: Measure AD8343 Differential Impedance at Location
of First Matching Component
Once the target impedance is established, the next step in
matching to the AD8343 is to measure the differential imped-
ance at the location of the first matching component. The "A"
side of the evaluation board is designed to facilitate doing so.
Before doing the board measurements, it is necessary to perform
a full two-port calibration of the VNA at the ends of the cables
that will be used to connect to the board's input connectors,
using the SOLT (Short, Open, Load, Thru) method or equiva-
lent. It is a good idea to set the VNA's sweep span to a few
hundred MHz or more for this work because it is often useful to
see what the circuit is doing over a large range of frequencies,
not just at the intended operating frequency. This is particularly
useful for detecting stability problems.
After the calibration is completed, connect network analyzer
ports one and two to the differential inputs of the AD8343
Evaluation Board.
On the AD8343 Evaluation Board, it is necessary to temporarily
install jumpers at Z1A and Z3A if Z4A is the desired component
location. Zero ohm resistors or capacitors of sufficient value
to exhibit negligible reactance work nicely for this purpose.
Next, extend the reference plane to the location of your first
matching component. This is accomplished by solidly shorting
both pads at the component location to GND (Note: Power to the
board must be OFF for this operation!) Adjust the VNA reference
plane extensions to make the entire trace collapse to a point (or
best approximation thereof near the desired frequency) at the
zero impedance point of the Smith Chart. Do this for each port.
A reasonable way to provide a good RF short is to solder a piece
of thin copper or brass sheet on edge across the pads to the nearby
GND pads.
Now, remove the short, apply power to the board, and take
readings. Take a look at both S11 and S22 to verify that they
remain inside the unit circle of the Smith Chart over the whole
frequency range being swept. If they fail to do so, this is a sign
that the device is unstable (perhaps due to an inappropriate
common-mode load) or that the network analyzer calibration is
wrong. Either way the problem must be addressed before pro-
ceeding further.
Assuming that the values look reasonable, use Konstroffer's
formula to convert to differential
.
Step 4: Design the Matching Network
The next step is to perform a trial design of a matching network
utilizing standard impedance matching techniques. The network
may be designed using single-ended network values, then con-
verted to differential form as illustrated in Figure 8. Figure 19
shows a theoretical design of a series C/shunt C "L" network
applied between 50
and a typical load at 1.8 GHz.
0.2
0.5
1.0
2.9pF SHUNT CAPACITOR
5.0
Figure 19. Theoretical Design of Matching Network
This theoretical design is important because it establishes the
basic topology and the initial matching value for the network.
The theoretical value of 2.9 pF for the initial matching com-
ponent is not available in standard capacitor values, so a 3.0 pF
is placed in the first shunt matching location. This value may
prove to be too large, causing an overshoot of the 50
real imped-
ance circle, or too small, causing the opposite effect. Always keep
in mind that this is a measure of differential impedance. The value
of the capacitor should be modified to achieve the desired 50
real impedance.
However, it may occasionally happen that the inserted shunt
capacitor moves the impedance in completely unexpected and
undesired ways. This is almost always an indication that the
reference plane was improperly extended for the measurement.
The user should readjust the reference planes and attempt the
shunt capacitor match with another calculated value.
When a differential impedance of 50
(real part) is achieved,
the board should be deenergized and another short placed on
the board in preparation for resetting the port extensions to a
new reference plane location. This short should be placed where
next the series components are expected to be added, and it is
important that both ports one and two be extended to this point
on the board.
Another differential measurement must be taken at this point to
establish the starting impedance value for the next matching
component. Note that if 50
PCB traces of finite length are
used to connect pads, the impedance will experience an angular
rotation to another location on the Smith Chart as indicated in
Figure 20.
REV. 0
AD8343
20
0.2
0.5
1.0
5.0
2.0
0.2
0.5
1.0
2.0
5.0
0
3.3pF SHUNT CAPACITOR
5mm 50 TRACE
FREQUENCY = 1.8GHz
Figure 20. Effect of 50
PCB Trace on 50 Real
Impedance Load
With the reference plane extended to the location of the series
matching components, it may now be necessary to readjust the
shunt capacitance value to achieve the desired 50
real imped-
ance. However, this rotation will not be very noticeable if the
board traces are fairly short or the application frequency is low.
As before, calculate the series capacitance value required to
move in the direction shown as step two in Figure 19, choose
the nearest standard component remembering to perform the
differential conversion, and install on the board. Again, if any
unexpected impedance transformations occur the reference
planes were probably extended incorrectly making it necessary
to readjust these planes.
This value of series capacitance should be adjusted to obtain the
desired value of differential impedance.
The above steps may be applied to any of the previously dis-
cussed matching topologies suitable for the AD8343. Also, if a
non-50
target impedance is required, simply calculate and
adjust the components to obtain the desired load impedance.
Caution: If the matching network topology requires a differen-
tial shunt inductor between the inputs, it may be necessary to
place a series blocking capacitor of low reactance in series with
the inductor to avoid creating a low resistance dc path between
the input terminals of the AD8343. Failure to heed this warning
will result in very poor LO-output isolation
Step 5: Transfer the Matching Network to the Final Design
On the "B" side of the AD8343 evaluation board, install the
matching network and the input balun. Install the same output
network as used for the work on the "A" side, then power up
the board and measure the input return loss at the RF input
connector on the board. Strictly speaking, the above procedure
(if carried out accurately) for matching the AD8343 will obtain
the best conversion gain; this may differ materially from the
condition which results in best return loss at the board's input if
the balun is lossy.
If the result is not as expected, the balun is probably producing
an unexpected impedance transformation. If the performance is
extremely far from the desired result and it was assumed that
the output impedance of the balun was 50
, it may be neces-
sary to measure the output impedance of the balun in question.
The design process should be repeated using the balun's output
impedance instead of 50
as the target. However, if the perfor-
mance is close to the desired result it should be possible to "tweak"
the values of the matching network to achieve a satisfactory
outcome. These changes should begin with a change from one
standard value to the adjacent standard value. With these
minor modifications to the matching network, one is able to
evaluate the trend required to reach the desired result.
If the result is unsatisfactory and an acceptable compromise
cannot be reached by further adjustment of the matching net-
work, there are two options: obtain a better balun, or attempt
a simultaneous conjugate match to both ports of the balun.
Accomplishing the latter (or even evaluating the prospects for
useful improvement) requires obtaining full two-port single-
ended-to-differential S parameters for the balun, which requires
the use of the ATN 4000 or similar multiport network analyzer
test set. Gonzalez presents formulas for calculating the simulta-
neous conjugate match in the section entitled, "Simultaneous
Conjugate Match: Bilateral Case" in his book, "Microwave
Transistor Amplifiers."
At higher frequencies the measurement process described above
becomes increasingly corrupted by unaccounted for impedance
transformations occurring in the traces and pads between the
input connectors and the extended reference plane. One approach
to dealing with this problem is to access the desired measurement
points by soldering down semirigid coax cables that have been
connected to the VNA and directly calibrated at the free ends.
APPLICATIONS
Downconverting Mixer
A typical downconversion application is shown in Figure 21
with the AD8343 connected as a receive mixer. The input
single-ended-to-differential conversion is obtained through the
use of a 1:1 transmission line balun. The input matching net-
work is positioned between the balun and the input pins, while
the output is taken directly from a 4:1 impedance ratio (2:1
turns ratio) transformer. The local oscillator signal at a level of
12 dBm to 3 dBm is brought in through a second 1:1 balun.
LO IN
10dBm
1:1
V
POS
4.71
0.1 F
AD8343
VPOS
DCPL
PWDN
LOIP
LOIM
INPP
INPM
OUTM
OUTP
COMM
IF
OUT
FB
4:1
BIAS
V
POS
R1
A
68
~
L1
A
L1
B
R1
B
68
R
FIN
Z1
Z2
A
Z2
B
FERRITE
BEAD
1:1
~
Figure 21. Typical Downconversion Application
REV. 0
AD8343
21
R1A and R1B set the core bias current of 18.5 mA per side. L1A
and L1B provide the RF choking required to avoid shunting the
signal. Z1, Z2A, and Z2B comprise a typical input matching net-
work that is designed to match the AD8343's differential input
impedance to the differential output impedance of the balun.
The IF output is taken through a 4:1 (impedance ratio) trans-
former that reflects a 200
differential load to the collectors.
This output coupling arrangement is reasonably broadband,
although in some cases the user might want to consider adding a
resonator tank circuit between the collectors to provide a mea-
sure of IF selectivity. The ferrite bead (FB), in series with the
output transformer's center tap, addresses the common-mode
stability concern.
In this circuit the PWDN pin is shown connected to GND,
which enables the mixer. In order to enter power-down mode
and conserve power, the PWDN pin should be taken within
500 mV of VPOS.
The DCPL pin should be bypassed to GND with about 0.1
µF.
Failure to do so could result in a higher noise level at the output
of the device.
Upconverting Mixer
A typical upconversion application is shown in Figure 22. Both
the input and output single-ended-to-differential conversions
are obtained through the use of 1:1 transmission line baluns.
The differential input and output matching networks are designed
between the balun and the I/O pins of the AD8343. The local
oscillator signal at a level of 12 dBm to 3 dBm is brought in
through a third 1:1 balun.
R1A and R1B set the core bias current of 18.5 mA per side. Z1,
Z2A, and Z2B comprise a typical input matching network that
is designed to match the AD8343's differential input impedance
to the differential output impedance of the balun. It was assumed
for this example that the input frequency is low and that the
magnitude of the device's input impedance is therefore much
smaller than the bias resistor values, allowing the input bias
inductors to be eliminated with very little penalty in gain or
noise performance.
In this example, the output signal is taken via a differential
matching network comprising Z3 and Z4A/B, then through the
1:1 balun and dc blocking capacitors to the single-ended output.
The output frequency is assumed to be high enough that conju-
gate matching to the output of the AD8343 is desirable, so the
goal of the matching network is to provide a conjugate match
between the device's output and the differential input of the
output balun.
This circuit uses shunt feed to provide collector bias for the
transistors because the output balun in this circuit has no con-
venient center-tap. The ferrite beads, in series with the output's
bias inductors, provide some small degree of damping to ease
the common-mode stability problem. Unfortunately this type of
output balun may present a common-mode load that enters the
region of output instability, so most of the burden of avoiding
overt instability falls on the input circuit, which should present
an inductive common-mode termination over as broad a band of
frequencies as possible.
The PWDN pin is shown as tied to GND, which enables the
mixer. The DCPL pin should be bypassed to GND with about
0.1
µF in order to bypass noise from the internal bias circuit.
RF
OUT
R1
A
R
FIN
R1
B
0.1 F
V
POS
LO IN
V
POS
0.1 F
AD8343
VPOS
DCPL
PWDN
LOIP
LOIM
INPP
INPM
OUTM
OUTP
COMM
BIAS
V
POS
Z2
A
Z2
B
0.1 F
0.1 F
Z1
FB
Z3
Z4
A
FB
Z4
B
Figure 22. Typical Upconversion Application
REV. 0
AD8343
22
EVALUATION BOARD
The AD8343 Evaluation Board has two independent areas, denoted A and B. The circuit schematics are shown in Figures 23 and
24. An assembly drawing is included in Figure 25 to ease identification of components, and representations of the board layout are
included in Figures 26 through 29.
The A region is configured for ease in making device impedance measurements as part of the process of developing suitable
matching networks for a final application. The B region is designed for operating the AD8343 in a single-ended application environment
and therefore includes pads for attaching baluns or transformers at both the input and output.
The following Tables (III through V) delineate the components used for the characterization procedure used to generate TPC 1
through 42 and most other data contained in this data sheet. Table III lists the support components that are delivered with the
AD8343 evaluation board. Note that the board is shipped without any frequency specific components installed. Table IV lists
the components used to obtain the frequency selection necessary for the product receiver evaluation, and Table V lists the transmitter
evaluation components.
Table III. Values of Support Components Shipped with Evaluation Board and Used for Device Characterization
Component Designator
Value
Qty.
Part Number
C1A, C1B, C3A, C3B, C11A, C11B
0.1
µF
6
Murata GRM40Z5U104M50V
C2A, C2B, C4A, C4B, C5A, C5B, C6A, C6B, C9A,
0.01
µF
16
Murata GRM40X7R103K50V
C9B, C10A, C10B, C12A, C12B, C13A, C13B
R3A, R3B, R4A, R4B
68.1
± 1%
4
Panasonic ERJ6ENF68R1V (T and R Packaging)
R1A, R1B, R2A, R2B
3.9
± 5%
4
Panasonic ERJ6GEYJ3R9V (T and R Packaging)
R5A, R5B
0
2
Panasonic ERJ6GEYJR00V (T and R Packaging)
J1A, J1B
Ferrite Bead
2
Murata BLM21P300S (2.0 mm SMT)
T1A, T1B, T2B (Various)
1:1
3
M/A-Com ETC1-1-13 Wideband Balun
*
T3B (Various)
4:1
1
Mini-Circuits TC4-1W Transformer
R6A, R6B, R7A, R7B
10
± 1%
4
Panasonic ERJ6GEYJ100V (T and R Packaging)
L1A, L1B, L2A, L2B
56 nH
4
Panasonic ELJ-RE56NJF3
Table IV. Values of Matching Components Used for Receiver Characterization
Component Designator
Value
Qty.
Part Number
f
IN
= 400 MHz, f
OUT
= 70 MHz
T1B, T2B
1:1
2
M/A-Com ETC1-1-13 Wideband Balun
1
T3B
4:1
1
Mini-Circuits TC4-1W Transformer
R6B, R7B
10
2
Panasonic ERJ6GEYJ100V (T and R Packaging)
Z1B, Z3B
jumper
2
#30 AWG Wire Across Pads
Z2B
8.2 pF
1
Murata MA188R2J
Z5B, Z7B
150 nH
2
Murata LQW1608AR15G00
Z6B
3.4 pF
1
Murata MA182R4B || MA181R0B
L1B, L2B
56 nH
2
Panasonic ELJ-RE56NJF3
Z4B, Z8B, L3B, L4B, R9B -- Not Populated
f
IN
= 900 MHz, f
OUT
= 170 MHz
T1B, T2B
1:1
2
M/A-Com ETC1-1-13 Wideband Balun
1
T3B
4:1
1
Mini-Circuits TC4-1W Transformer
R6B, R7B
10
2
Panasonic ERJ6GEYJ100V (T and R packaging)
Z1B, Z3B
jumper
2
#30 AWG Wire Across Pads
Z4B
3.0 pF
1
Murata GRM39C0G3R0B50V
Z5B, Z7B
120 nH
2
Murata LQW1608AR12G00
Z6B
0.4 pF
1
Murata MA180R4B
L1B, L2B
56 nH
2
Panasonic ELJ-RE56NJF3
Z2B, Z8B, L3B, L4B, R9B -- Not Populated
f
IN
= 1900 MHz, f
OUT
= 425 MHz
T1B, T2B
1:1
3
M/A-Com ETC1-1-13 Wideband Balun
1
T3B
4:1
1
Mini-Circuits TC4-1W Transformer
R6B, R7B
10
2
Panasonic ERJ6GEYJ100V (T and R packaging)
Z1B, Z3B
6.8 nH
2
Murata LQW1608A6N8C00
Z2B
0.6 pF
1
Murata MA180R6B
Z5B, Z7B
39 nH
2
Murata LQW1608A39NG00
Z8B
2.0 pF
1
Murata MA182R0B
L1B, L2B
56 nH
2
Panasonic ELJ-RE56NJF3
Z6B, Z4B, L3B, L4B, R9B -- Not Populated
REV. 0
AD8343
23
Table IV. Values of Matching Components Used for Receiver Characterization (Continued)
Component Designator
Value
Qty.
Part Number
f
IN
= 1900 MHz, f
OUT
= 170 MHz
T1B, T2B
1:1
2
M/A-Com ETC1-1-13 Wideband Balun
1
T3B
4:1
1
Mini-Circuits TC4-1W Transformer
R6B, R7B
10
2
Panasonic ERJ6GEYJ100V (T and R Packaging)
Z1B, Z3B
6.8 nH
2
Murata LQW1608A6N8C00
Z4B
0.5 pF
1
Murata MA180R5B
Z5B, Z7B
100 nH
2
Murata LQW1608AR10G00
Z6B
2.4 pF
1
Murata MA182R4B
L1B, L2B
56 nH
2
Panasonic ELJ-RE56NJF3
Z2B, Z8B, L3B, L4B, R9B -- Not Populate
d
Table V. Values of Matching Components Used for Transmitter Characterization
Component Designator
Value
Qty.
Part Number
f
IN
= 150 MHz, f
OUT
= 900 MHz
T1B, T3B
1:1
2
M/A-Com ETC1-1-13 Wideband Balun
1
T2B
1:1
1
Mini-Circuits ADTL1-18-75
R6B, R7B
5.1
2
Panasonic ERJ6GEYJ510V (T and R Packaging)
Z1B, Z3B
8.2 nH
2
Murata LQW1608A8N2C00
Z2B
33 pF
1
Murata GRM39C0G330J100V
Z5B, Z7B
8.2 nH
2
Murata LQG11A8N2J00
Z8B
6.2 pF
1
Murata MA186R2C
L1B, L2B
56 nH
2
Panasonic ELJ-RE56NJF3
L3B, L4B
150 nH
2
Murata LQW1608AR15G00
Z4B, Z6B, R9B -- Not Populated
f
IN
= 150 MHz, f
OUT
= 1900 MHz
T1B, T3B
1:1
2
M/A-Com ETC1-1-13 Wideband Balun
1
T2B
1:1
1
Mini-Circuits ADTL1-18-75
R6B, R7B
5.1
2
Panasonic ERJ6GEYJ510V (T and R Packaging)
Z1B, Z3B
8.2 nH
2
Murata LQG11A8N2J00
Z2B
33 pF
1
Murata GRM39C0G330J100V
Z5B, Z7B
1.8 nH
2
Murata LQG11A1N8S00
Z8B
1.8 pF
1
Murata MA181R8B
L1B, L2B
56 nH
2
Panasonic ELJ-RE56NJF3
L3B, L4B
68 nH
2
Murata LQW1608A68NG00
Z4B, Z6B, R9B -- Not Populated
NOTES
1
The ECT1-1-13 wideband balun was chosen for ease in customer's independent evaluation. These baluns are quite acceptable for use as T1 on the LO port, but may
not be acceptable for use as T2 on the high performance RF input. It has been found that board to board performance variations become unacceptable when
this balun is used at higher (> 500 MHz) frequencies. A narrow-band balun is suggested for this critical interface. Refer to the Device Interfaces and A Step-by-Step
Approach to Impedance Matching section of this document for more information.
REV. 0
AD8343
24
L2A
VPOS_A
GND_A
PWDN_1_A
INPUT_P_A
INPUT_M_A
PWDN_A
L1A
R3A
R4A
R5A
C5A
Z1A
Z2A
Z4A
R1A
C1A
C2A
J1A
Z7A
Z5A
Z6A
Z8A
C9A
C10A
L4A
C8A
C12A
C13A
T1A
L3A
C7A
OUTPUT_P_A
OUTPUT_M_A
LO INPUT_A
14
13
12
11
10
9
8
1
2
3
4
5
6
7
COMM
AD8343
INPP
INPM
DCPL
VPOS
PWDN
COMM
COMM
OUTP
OUTM
COMM
LOIP
LOIM
COMM
C11A
DUTA
Z3A
C6A
R2A
C3A
C4A
1
2
4
3
5
Z9A
R7A
R6A
REFERENCE TABLE I FOR COMPONENT VALUES AS SHIPPED.
REFERENCE TABLE I, II, AND III FOR CHARACTERIZATION VALUES.
Figure 23. Characterization and Evaluation Board Circuit A
INPUT_B
T3B
L2B
VPOS_B
GND_B
PWDN_1_B
PWDN_B
L1B
R3B
R4B
R5B
C5B
Z1B
Z2B
Z4B
R1B
C1B
C2B
J1B
Z7B
Z5B
Z6B
Z8B
C9B
C10B
L4B
C8B
C12B
C13B
T1B
L3B
C7B
OUTPUT_B
LO_INPUT_B
14
13
12
11
10
9
8
1
2
3
4
5
6
7
COMM
AD8343
INPP
INPM
DCPL
VPOS
PWDN
COMM
COMM
OUTP
OUTM
COMM
LOIP
LOIM
COMM
C11B
DUTB
Z3B
C6B
R2B
C3B
C4B
1
2
4
3
5
1
2
4
3
5
T2B
4
2
1
3
6
Z9B
R7B
R6B
REFERENCE TABLE I FOR COMPONENT VALUES AS SHIPPED.
REFERENCE TABLE I, II, AND III FOR CHARACTERIZATION VALUES.
Figure 24. Characterization and Evaluation Board Circuit B
REV. 0
AD8343
25
ASSEMBLY BOTTOM
ASSEMBLY TOP
Figure 25. Evaluation Board Assembly Drawing
Figure 26. Evaluation Board Artwork Top
Figure 27. Evaluation Board Artwork Internal 1
REV. 0
AD8343
26
Figure 28. Evaluation Board Artwork Internal 2
Figure 29. Evaluation Board Artwork Bottom
REV. 0
AD8343
27
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead Plastic Thin Shrink Small Outline Package (TSSOP)
RU-14
14
8
7
1
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
0.201 (5.10)
0.193 (4.90)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
0.0433 (1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8
0
C0103456/00 (rev. 0)
PRINTED IN U.S.A.
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