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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

AD8321

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 1999

Gain Programmable

CATV Line Driver

FEATURES
Linear in dB Gain Response Over >53 dB Range
Drives Low Distortion >11 dBm Signal into 75 Load:

53 dBc SFDR at 42 MHz

Very Low Output Noise Level
Maintains Constant 75 Output Impedance

Power-Up and Power-Down Condition
No Line Transformer Required

Upper Bandwidth: 235 MHz (Min Gain)
9 V Single Supply Operation
Power-Down Functionality
Supports SPI Interface
Low Cost

APPLICATIONS
Gain Programmable Line Driver

HFC High Speed Data Modems
Interactive CATV Set-Top Boxes
CATV Plant Test Equipment

General Purpose IF Variable Gain Block

DESCRIPTION

The AD8321 is a low cost digitally controlled variable gain
amplifier optimized for coaxial line driving applications such as
cable modems that are designed to the DOCSIS* (upstream)
standard. An 8-bit serial word determines the desired output
gain over a 53.4 dB range, resulting in gain changes of 0.75 dB/
LSB.

The AD8321 comprises a digitally controlled variable attenuator
of 0 dB to 53.4 dB, which is preceded by a low noise, fixed
gain buffer and followed by a low distortion high power ampli-
fier. The AD8321 accepts a differential or single-ended input
signal. The output is specified for driving a 75

load, such as

coaxial cable, although the AD8321 is capable of driving other
loads. Performance of 53 dBc is achieved with an output level
up to 11 dBm at 42 MHz bandwidth using a 9 V supply.

A key performance and cost advantage of the AD8321 results
from the ability to maintain a constant 75

output impedance

during power-up and power-down conditions. This eliminates
the need for external 75

termination, resulting in twice the

effective output voltage when compared to a standard opera-
tional amplifier, thus eliminating the need for a transformer.

*Data-Over-Cable Service Interface Specifications

FUNCTIONAL BLOCK DIAGRAM

AD8321

POWER-

DOWN/

SWITCH

INTER

ATTENUATOR CORE

INV

DATA SHIFT REGISTER

DATA LATCH

PWR

AMP

DATEN

CLK

VIN+

VIN

VOUT

REVERSE

AMP

GND

VCC

SDATA

The AD8321 is packaged in a low cost 20-lead SOIC, operates
from a single +9 V supply, and has an operational temperature
range of 40

C to +85

GAIN CONTROL Decimal

DISTORTION dBc

90

80

70

60

50

40

= 42MHz

= 137mV p-p

= 15dBm)

OUT

= 11dBm @

MAX GAIN)

HD3

HD2

Figure 1. Harmonic Distortion vs. Gain Control

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AD8321SPECIFICATIONS

Parameter

Conditions

Min

Typ

Max

Units

INPUT CHARACTERISTICS

Specified AC Voltage

Output = 11 dBm, Max Gain

0.137

V p-p

Noise Figure

Max Gain, f = 10 MHz

Input Resistance

Single-Ended Input

820

Differential Input

900

Input Capacitance

2.0

GAIN CONTROL INTERFACE

Gain Range

52.4

53.4

54.4

Maximum Gain

25.25

26.75

Minimum Gain

28.15 27.4

26.4

Gain Scaling Factor

0.7526

dB/LSB

OUTPUT CHARACTERISTICS

Bandwidth (3 dB)

All Gain Codes

120

MHz

Bandwidth Roll-Off

f = 65 MHz

0.8

Bandwidth Peaking

f = 65 MHz

Output Offset Voltage

All Gain Codes, Full Temperature Range

Output Noise Spectral Density

Max Gain, f = 10 MHz

nV/

Min Gain, f = 10 MHz

nV/

Output Noise Temperature Sensitivity 0

+70

C, Min Gain

0.02

nV/

Hz/

Power-Down Spectral Density

nV/

1 dB Compression Point

Max Gain, f = 10 MHz

+19.5

dBm

Output Impedance

Power-Up and Power-Down

OVERALL PERFORMANCE

Worst Harmonic Distortion

f = 42 MHz, P

OUT

= 11 dBm, V

= +9 V

dBc

f = 65 MHz, P

OUT

= 11 dBm, V

= +9 V

dBc

Distortion Temperature Sensitivity

+85

0.03

dBc/

Gain Accuracy

f = 10 MHz, All Gain Codes

0.2

Gain Temperature Sensitivity

+70

0.004

dB/

Output Settling to 1 mV

Gain Change @ T

DATEN

= 1

Min to Max Gain, V

= 0 V

Input Change

Max Gain, V

= 0.15 V Step

Signal Feedthrough

Power Down, 65 MHz, Min Gain

dBc

= 0.137 V p-p

POWER CONTROL

Power-Down Settling Time to 1 mV

Max Gain, V

= 0

Power-Up Settling Time to 1 mV

Max Gain, V

= 0

300

Power-Up/Down Pedestal Offset

Max Gain, V

= 0

Power-Up/Down Glitch

Max Gain, V

= 0

mV p-p

POWER SUPPLY

Quiescent Current

Power-Up, V

= +9 V

Power-Down, V

= +9 V

Specifications subject to change without notice.

(@ V

= +9 V, T

= +25 C, V

= 0.137 V

p-p, single-ended input, R

= 75

, R

unless otherwise noted)

AD8321

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LOGIC INPUTS (TTL/CMOS Logic)

Parameter

Min

Typ

Max

Units

Logic "1" Voltage

2.1

5.0

Logic "0" Voltage

0.8

Logic "1" Current (V

INH

= 5 V) CLK, SDATA,

DATEN

Logic "0" Current (V

INL

= 0 V) CLK, SDATA,

DATEN

600

100

Logic "1" Current (V

INH

= 5 V)

190

Logic "0" Current (V

INL

= 0 V)

250

TIMING REQUIREMENTS

Parameter

Min

Typ

Max

Units

Clock Pulsewidth (T

)

16.0

Clock Period (T

)

32.0

Setup Time SDATA vs. Clock (T

)

5.0

Setup Time

DATEN vs. Clock (T

)

15.0

Hold Time SDATA vs. Clock (T

)

5.0

Hold Time

DATEN vs. Clock (T

)

3.0

Input Rise and Fall Times, SDATA,

DATEN, Clock (T

, T

)

VALID DATA WORD G1

MSB. . . .LSB

GAIN TRANSFER (G1)

8 CLOCK CYCLES

GAIN TRANSFER (G2)

OFF

ANALOG

OUTPUT

SIGNAL AMPLITUDE (p-p)

PEDESTAL

CLK

SDATA

DATEN

VALID DATA WORD G2

Figure 2. Serial Interface Timing

VALID DATA BIT

MSB

MSB-1

MSB-2

SDATA

CLK

Figure 3. SDATA Timing

(

DATEN, CLK, SDATA, V

= +9 V; Full Temperature Range)

(Full Temperature Range, V

= +9 V, T

= T

= 4 ns, f

CLK

= 8 MHz unless otherwise noted.)

AD8321

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CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8321 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

AD8321AR

C to +85

20-Lead SOIC

C/W*

R-20

AD8321AR-REEL

C to +85

20-Lead SOIC

C/W*

R-20

AD8321-EVAL

Evaluation Board

*Thermal Resistance measured on SEMI standard 4-layer board.

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage +V

Pins 7, 8, 9, 17, 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . +11 V

Input Voltages

Pins 18, 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0.5 V

Pins 1, 2, 3, 6 . . . . . . . . . . . . . . . . . . . . . . 0.8 V to +5.5 V

Internal Power Dissipation

Small Outline (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.90 W

Operating Temperature Range . . . . . . . . . . . 40

C to +85

Storage Temperature Range . . . . . . . . . . . . 65

C to +150

Lead Temperature, Soldering 60 seconds . . . . . . . . . . +300

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

PIN CONFIGURATION

TOP VIEW

(Not to Scale)

AD8321

VOUT

VCC

CLK

DATEN

GND

VCC

BYP1

GND

VIN

VCC

BYP2

GND

SDATA

VCC

GND

VIN+

PIN FUNCTION DESCRIPTIONS

Pin

Function

Description

SDATA

Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the internal
register with the MSB (most significant bit) first.

CLK

Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-slave
register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave.
This requires the input serial data word to be valid at or before this clock transition.

DATEN

Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-
1 transition transfers the latched data to the attenuator core (updates the gain) and simultaneously
inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previ-
ous gain state) and simultaneously enables the register for serial data load.

4, 11, 12,
13, 15, 16

GND

Common External Ground Reference.

BYP1

/2 Reference Pin. A dc output reference level that is equal to 1/2 of the supply voltage (VCC). This

port should be externally ac-decoupled (0.1

F capacitor). For external use of this reference voltage,

buffering is required.

Power-Down Low Logic Input. A Logic 0 powers down (shuts off) the power amplifier disabling the
output signal and enabling the reverse amplifier. A Logic 1 enables the output power amplifier and
disables the reverse amplifier.

7, 8, 9, 17, 20

VCC

Common Positive External Supply Voltage.

VOUT

Output Signal Port. DC-biased to approximately V

/2.

BYP2

Internal Bypass. This pin must be externally ac-decoupled (0.1

F cap).

VIN+

Noninverting Input. DC-biased to approximately V

/2. For single-ended inverting operation, use

0.1

F decoupling capacitor between VIN+ and ground.

VIN

Inverting Input. DC-biased to approximately V

/2. Should be ac-coupled with a 0.1

F capacitor.

WARNING!

ESD SENSITIVE DEVICE

Typical Performance CharacteristicsAD8321

REV. 0

GAIN CONTROL Decimal

GAIN ERROR dB

1.2

0.9

0.3

0.6

f = 65MHz

f = 10MHz

f = 42MHz

0.6

Figure 4. Gain Error vs. Gain Control

FREQUENCY MHz

100

OUTPUT NOISE nV/

= 1

MAX GAIN

(71D)

MIN GAIN

(00D)

Figure 7. Output Referred Noise vs.
Frequency

FUNDAMENTAL FREQUENCY MHz

DISTORTION dBc

59

56

53

50

47

= 14dBm

OUT

= 12dBm @

MAX GAIN)

= 13dBm

OUT

= 13dBm @

MAX GAIN)

= 15dBm

OUT

= 11dBm @

MAX GAIN)

= 17dBm

OUT

= 9dBm @

MAX GAIN)

Figure 10. Third Order Harmonic
Distortion vs. Frequency for Various
Input Levels

GAIN CONTROL Decimal

OUTPUT NOISE nV/

f = 10MHz

Figure 6. Output Referred Noise vs.
Gain Control

FUNDAMENTAL FREQUENCY MHz

DISTORTION dBc

59

56

53

50

47

= 14dBm

OUT

= 12dBm @

MAX GAIN)

= 13dBm

OUT

= 13dBm @

MAX GAIN)

= 15dBm

OUT

= 11dBm @

MAX GAIN)

= 17dBm

OUT

= 9dBm @

MAX GAIN)

Figure 9. Second Order Harmonic
Distortion vs. Frequency for Various
Input Levels

FREQUENCY MHz

3RD ORDER INTERCEPT dBm

= 11dBm

MAX GAIN

Figure 12. Third Order Intercept vs.
Frequency

FREQUENCY MHz

GAIN dB

40

0.1

30

20

10

100

1000

46D

23D

00D

71D

Figure 5. AC Response

GAIN CONTROL Decimal

DISTORTION dBc

= 65MHz

= 0.137V p-p

= 15dBm)

OUT

= 11dBm @

MAX GAIN)

80

70

60

50

40

30

HD3

HD2

Figure 8. Harmonic Distortion vs.
Gain Control

FREQUENCY MHz

OUT

 dBm

41.0

80

60

40

20

= 11dBm

MAX GAIN

41.4

41.8

42.2

42.6

43.0

Figure 11. Two-Tone Intermodula-
tion Distortion

AD8321

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FREQUENCY MHz

100

GAIN dB

MAX GAIN
P

= 11dBm

= 10pF

= 0pF

= 20pF

= 50pF

Figure 13. AC Response for Various
Capacitor Loads

150ns

= 0V p-p

MAX GAIN
tr(CLK) = 3ns

7.5mV

OUT

DATEN

CLK

Figure 16. Clock Feedthrough

1.5V

30ns

MAX GAIN

0.5V

OUT

Figure 19. Overload Recovery

75ns

MAX GAIN
V

= 0V p-p

15mV

OUT

Figure 15. Power Up/Power Down
Glitch

0.75V

30ns

MAX GAIN
V

= 0V p-p 0.137V p-p

200mV

OUT

Figure 18. Output Settling Time Due
to Input Change

TEMPERATURE C

 mA

50

100

= 0

100

25

Figure 21. Supply Current vs.
Temperature

75ns

MIN GAIN
V

= 0V p-p

5mV

OUT

Figure 14. Power Up/Power Down
Glitch

FREQUENCY MHz

FEEDTHROUGH dB

100

0.1

80

60

100

1000

40

20

= 0

MAX GAIN

MIN GAIN

Figure 17. Input Signal Feedthrough
vs. Frequency

FREQUENCY MHz

100

IMPEDANCE 

= 1

= 0

Figure 20. Output Impedance vs.
Frequency

AD8321

REV. 0

OPERATIONAL DESCRIPTION

The AD8321 is a digitally controlled variable gain power ampli-
fier that is optimized for driving a 75

cable. As a multifunc-

tional bipolar device on a single silicon die, it incorporates all
the analog features necessary to accommodate reverse path
(upstream) high speed (5 MHz to 65 MHz) cable data modem
requirements. The AD8321 has an overall gain range of ap-
proximately 53 dB and is capable of greater than 100 MHz
operation at output signal levels exceeding 12 dBm. Overall,
when considering the device's wide gain range, low distortion,
wide bandwidth and variable load drive, the device can be used
in many variable gain block applications.

AD8321

POWER-

DOWN/

SWITCH

INTER

ATTENUATOR CORE

INV

DATA SHIFT REGISTER

DATA LATCH

PWR

AMP

DATEN

CLK

VIN+

VIN

VOUT

REVERSE

AMP

GND

VCC

SDATA

Figure 22. Functional Block Diagram

The digitally programmable gain is controlled by the three-wire
"SPI" compatible inputs. These inputs are called SDATA
(serial data input port),

DATEN (data enable low input port)

and CLK (clock input port). See Pin Function Descriptions
and Functional Block diagram. The AD8321 is programmed by
an 8-bit "attenuator" word. When a standard 8-bit word is
used, the first data bit MSB will be shifted out of the 7-bit shift
register during the eighth rising CLK edge. The lower seven
bits will then be loaded into the AD8321's digital decode sec-
tion when the

DATEN input is taken high.

The gain of the AD8321 is linear in steps of 0.7526 dB. The
gain transfer function starts at 27.43 dB (at decimal code 0)
and increases 0.7526 dB/LSB. The gain increases up to decimal
code 71. At this point the gain is at its maximum level of 26 dB.
If a decimal word between 71 and 127 is entered, the gain is no
longer incremented and stays at 26 dB. Since the MSB of an 8-bit
word is a "don't care" bit, at decimal code 128, the AD8321's
gain returns to its minimum value. The gain vs. gain control
relationship repeats itself as shown in Figure 23 for the upper
127 codes.

The gain transfer function is as follows:

= 26 dB ((71 CODE)

0.7526 dB) for CODE

= 26 dB for 71

CODE

127

= 26 dB + ((199 CODE)

0.7526 dB) for 128

CODE

199

= 26 dB for 199

CODE

255

where CODE is the decimal equivalent of the 8-bit word loaded in
the AD8321's data latch (see Figure 23).

GAIN CODE Decimal

30

256

GAIN dB

10

20

224

192

160

128

Figure 23. Linear-In dB Gain vs. Gain Control

The AD8321 is composed of four analog functions in the
power-up or forward mode. The input amplifier (preamp) which
can be used single-endedly or differentially and provides a maxi-
mum of 12 dB of attenuation. If the input is used in the differ-
ential configuration, it is imperative that the input signals are
180 degrees out of phase and of equal amplitudes. This will
ensure the proper gain accuracy and harmonic performance.

The preamp stage drives a vernier stage that provides the fine
tune gain adjustment. The 0.7526 dB step resolution is imple-
mented in this stage. After the vernier stage, a DAC provides the
bulk of the AD8321's attenuation (six bits or 36 dB). The signals
in the preamp and vernier gain blocks are differential to im-
prove the PSRR and linearity. A single-ended current is fed
from the DAC into the output stage, which amplifies this cur-
rent to the appropriate level necessary to drive a 75

load. The

output stage utilizes negative feedback to implement a
75

output impedance. This eliminates the need for an exter-

nal 75

matching resistor needed in typical video (or video

filter) termination requirements.

AD8321

REV. 0

The attenuation setting in the AD8321 is determined by the
8-bit word in the data latch. The SDATA load sequence is
initiated by a falling edge on

DATEN. The gain control data

(SDATA) is serially loaded (MSB first) into the 7-bit shift register
at each rising edge of the clock. See Figure 24. While

DATEN

is low, the data latch holds the previous data word allowing the
attenuation level to remain unchanged. After eight clock cycles
the new data word is fully loaded and

DATEN is switched high.

This enables the data latch and the loaded register data is passed to
the attenuator with the updated gain value. Also at this

DATEN

transition, the internal clock is disabled, thus inhibiting new
serial input data.

The power amplifier has two basic modes of operation. A for-
ward mode (or power-up mode) and a reverse mode (or power-
down) mode. In the power-up mode (

PD = 1), the power

amplifier stage is enabled and the AD8321 has a maximum gain
of 20 V/V or 26 dB (into 75

). With a total attenuation of

53.43 dB in the DAC, vernier and preamp, the AD8321's total
gain range is 26 dB to 27.43 dB. In both the forward or reverse
mode the single-ended output signal maintains a dc level of
V

/2. This dc output level provides for optimum large signal

linearity.

In the power-down mode (

PD = 0), the power amplifier is

turned off and a "reverse" amplifier (the inner triangle in Figure
22) is enabled. During this 1-to-0 transition, the output power
is disabled. This assures that S11 and S22 remain approximately
equal to zero thus minimizing line reflections. In the time do-
main, as

PD switches states, a transitional glitch and pedestal

offset results (See Figures 14 and 15). These anomalies have
been minimized by temperature compensated internal circuitry
and laser trimming. The powered down supply current drops to
52 mA versus 90 mA in the power-up mode.

APPLICATIONS
General Application

The AD8321 is primarily intended for use as the return path
(also called upstream path) Power Amplifier (PA) or line driver
in cable modem applications. Upstream data is modulated in
either QPSK or QAM format. This is done either in DSP or by
a dedicated QPSK/QAM modulator such as the AD9853 or
other modem/modulator chip. The amplifier receives its input
signal either from the dedicated QPSK/QAM modulator or from
a DAC. In both cases, the signal must be low-pass filtered be-
fore being applied to the line driving amplifier. Because the
distance to the central office varies from cable modem sub-
scriber to subscriber, resulting in various line losses, signals from
various subscribers will require attenuation while others may
require gain. As a result, the AD8321 line driver is required to
vary its output applying attenuation or gain as needed so that all
signals arriving at the central office are of the same amplitude.

DOCSIS (Data Over Cable Service Interface Specifications)
requires a cable modem output signal ranging in power from a
minimum of 8 dBmV to a maximum of 58 dBmV. In cable
modem applications where DOCSIS compliance is desired, the
AD8321 amplifier must be used in conjunction with a 75

matching attenuator connected between the AD8321 output
and the low-pass input port of the diplexer. See the schematic in
Figure 28. The matching attenuator is used to achieve DOCSIS-
compliant noise levels at the lower end of the AD8321 output
power range. The insertion loss of a diplexer is typically less
than 1 dB. As a result of these combined losses, the PA line
driver must be capable of delivering sufficient power into a 75

load while maintaining reasonable distortion performance at the
output of the modem. (See sections containing "DOCSIS" for
further information. All references to DOCSIS pertain to
SP-RFI-I04-980724 entitled Radio Frequency Interface
Specification.)

VALID DATA WORD G1

MSB. . . .LSB

GAIN TRANSFER (G1)

8 CLOCK CYCLES

GAIN TRANSFER (G2)

OFF

ANALOG

OUTPUT

SIGNAL AMPLITUDE (p-p)

PEDESTAL

CLK

SDATA

DATEN

VALID DATA WORD G2

Figure 24. Serial Interface Timing

AD8321

REV. 0

Basic Connection

Figure 25 shows the basic schematic for operating the AD8321
in single-ended inverting mode. To operate in inverting mode,
connect the input signal through an ac coupling capacitor to
VIN; VIN+ should be decoupled to ground with a 0.1

capacitor. Because the amplifier operates from a single supply,
and the differential input pins are biased to approximately
V

/2, the differential inputs must be ac-coupled using 0.1

capacitors. For operation in the noninverting mode, the VIN
pin should be decoupled to ground via a 0.1

F capacitor, with

the input signal being fed to the AD8321 through the (ac-coupled)
VIN+ pin. Inverting mode should be chosen if the AD8321 is
being used as a drop-in replacement for the AD8320 (the
AD8321 predecessor). Balanced differential inputs to the
AD8321 may also be applied at an amplitude that is one-half
the specified single-ended input amplitude. See the Differential
Inputs section for more on this mode of operation.

Power Supply and Decoupling

The AD8321 should be powered with a good quality (i.e., low
noise) single supply of 9 V. Although the AD8321 circuit will
function at voltages lower than 9 V, optimum performance will
not be achieved at lower supply settings. Careful attention must
be paid to decoupling the power supply pins. A 10

F capacitor

located in near proximity to the AD8321 is required to provide
good decoupling for lower frequency signals. In addition, and
more importantly, five 0.1

F decoupling capacitors should be

located close to each of the five power supply pins (7, 8, 9, 17
and 20). A 0.1

F capacitor must also be connected to the pins

labeled BYP1 and BYP2 (Pins 5 and 14) to provide decoupling
to internal nodes of the device. All six ground pins should be
connected to a common low impedance ground plane.

Input Bias, Impedance and Termination

On the input side, the VIN+ and VIN have a dc bias level
equal to (V

/2)0.2 V. The input signal must therefore be ac-

coupled before being applied to either input pin. The input
impedance, when operated in single-ended mode is roughly
820

(900

in differential mode). An external shunt resis-

tance (R1) to ground of 82.5

is required to create a single-

ended input impedance of close to 75

. If single-ended 50

termination is required, a 53.6

shunt resistor may be used.

Differential input operation may be achieved by using a shunt
resistor of 41

to ground on each of the inputs, or 82.6

across the inputs resulting in a differential input impedance of
approximately 75

. Note: to avoid dc loading of either the

VIN+ or VIN pin, the ac-coupling capacitor must be placed
between the input pin(s) and the shunt resistor(s). Refer to the
Differential Inputs section for more details on this mode of
operation.

Output Bias, Impedance and Termination

On the output side, the VOUT pin is also dc-biased to V

/2 or

midway between the supply voltage and ground. The output
signal must therefore be ac-coupled before being applied to the
load. The dc-bias voltage is available on the BYP1 and BYP2
pins (Pins 5 and 14 respectively) and can be used in dc-biasing
schemes. These nodes must be decoupled to ground using a
0.1

F capacitor as shown in Figure 25. If the BYP1 and/or

BYP2 voltages are used externally, they should be buffered.
External back termination resistors are not required when using
the AD8321. The output impedance of the AD8321 is 75

and

is maintained dynamically. This on chip back termination is
maintained regardless of whether the amplifier is in forward
transmit mode or reverse powered down mode. If the output
signal is being evaluated on 50

test equipment such as a spec-

trum analyzer, a 75

to 50

adapter (commonly called a mini-

mum loss pad) should be used to maintain a properly matched
circuit.

ATTENUATOR

CORE

DATA SHIFT

REGISTER

DATA LATCH

AD8321

POWER-

DOWN/

SWITCH

INTER

DATEN

CLK

VIN+

VIN

VOUT

SDATA

VCC

0.1 F

VCC

0.1 F

VCC

C10

0.1 F

VCC

C11

0.1 F

BYP1

0.1 F

82.5

INPUT

DATEN

CLK

GND

SDATA

0.1 F

TO
DIPLEXER
R

= 75

BYP2

VCC

+9V

0.1 F

10 F

0.1 F

Figure 25. Basic Connection for Single-Ended Inverting Operation

AD8321

REV. 0

Varying the Gain and SPI Programming

The gain of the AD8321 can be varied over a range of 53 dB
from approximately 27 dB to +26 dB, in increments of ap-
proximately 0.7526 dB per LSB. Programming the gain of the
AD8321 is accomplished using conventional Serial Peripheral
Interface or SPI protocol. Three digital lines,

DATEN, CLK

and SDATA, are used to stream eight bits of data into the serial
shift register of the AD8321. Changing the state of the

DATEN

port from Logic 1-to-0 starts the load sequence by activating the
CLK line. No changes in output signal are realized during this
transition. Subsequently, any data applied to SDATA is clocked
into the serial shift register Most Significant Bit (MSB) first and
on the rising edge of each CLK pulse. The AD8321 may be
programmed to deliver maximum gain (+26 dB) at decimal
code 71. As a result, only the last seven bits of a typical 8-bit
SPI word effect the gain resulting in the gain response depicted
in Figure 22. Since the SPI codes from 0 through 71 appear
digitally identical to codes 128 through 199 for all bits except
the MSB, the AD8321 repeats the gain vs. decimal code re-
sponse twice in the 256 available codes (see Operational De-
scription for gain equations and Figure 23 for Gain Response).
The MSB of a typical SPI word (i.e., the first data bit presented
to the SDATA line after the

DATEN transition from logic 1 to

0 and prior to the rising edge of the first clock pulse) is disre-
garded or ignored. Data enters the serial shift register through
the SDATA port on the rising edge of the next seven CLK
pulses. Returning the

DATEN line to Logic 1 latches the con-

tent of the shift register into the attenuator core resulting in a
well controlled change in output signal level. The timing dia-
gram for AD8321's serial interface is shown in Figure 24.

Gain Dependence on Load Impedance

The AD8321 has a dynamic output impedance of 75

. This

dynamic output impedance is trimmed to provide a maximum
gain of +26 dB when loaded with 75

. Operating the AD8321

at load impedances other than 75

will only change the gain of

the AD8321 while the specified gain range of 53 dB is unchanged.
Varying the load impedance will result in 6 dB of additional gain
when R

LOAD

approaches infinity. The relationship between

LOAD

and gain is depicted in Figure 26 and is described by the

following equation:

Gain (dB) = [20 log ((2

LOAD

)/(R

LOAD

+75))]+(26(0.7526

(71-Code)))

LOAD

500

GAIN dB

400

300

200

100

Figure 26. Maximum Gain vs. R

LOAD

Between Burst On/Off Transients, Asynchronous Power-
Down and DOCSIS

A 42% reduction in consumed power may be achieved asyn-
chronously by applying Logic 0 to

PD Pin 6 activating the on-

chip "reverse amplifier." The supply current is then reduced to
approximately 52 mA and the modem can no longer transmit in
the upstream direction. The on-chip reverse amplifier is de-
signed to reduce "between burst noise" and maintain a 75

source impedance to the low pass port of the modem's diplexer
while minimizing power consumption. Changing the logic level
applied to the

PD pin will result in a Burst On/Off Transient at

the output of the AD8321. The transient results from switching
between the forward transmit amplifier and the powered down
(reverse) amplifier. Although the resulting transient meets the
DOCSIS transient amplitude requirements at maximum gain, it
is the lower gain range (i.e., 8 dBmV to 31 dBmV) where the
AD8321 may exceed the 7 mV maximum. The diplexer may
further reduce the glitch amplitude. An external RF switch, such
as Alpha Industries AS128-73 GaAs 2 Watt High Linearity
SPDT RF switch, may be used to further reduce the spurious
emissions, improve the isolation between the cable plant and the
upstream line driver and switch in a 75

back termination

required to maintain proper line termination to the LP port of
the diplexer (see Figure 28).

Noise and DOCSIS

One of the most difficult issues facing designers of DOCSIS
compliant modems is maintaining a quiet output from the PA
during times when no information is being transmitted up-
stream. In addition, maintaining proper signal-to-noise ratios
serves to ensure the quality of transmitted data. This is extremely
critical when the output signal of the modem is set to the mini-
mum DOCSIS specified output level or 8 dBmV. The AD8321
output noise spectral density at minimum gain (or 8 dBmV) is
20 nV/

Hz measured at 10 MHz. Considering the "Spurious

Emissions in 5 MHz to 42 MHz" of Table 48 in DOCSIS, the
calculated noise power in dBmV for 160 K sym/sec is:

160

41 5

log

dBmV

Comparing the computed noise power to the signal at 8 dBmV
yields 49.5 dBc or 3.5 dB higher than the required 53 dBc in
DOCSIS Table 48. An attenuator designed to match the
AD8321 75

source to the 75

load may be required. Refer-

ring to the schematic of Figure 28 and the evaluation board
silkscreen of Figure 31, the matching attenuator is comprised of
the three resistors referred to as Rc, Rd and Re. Select the at-
tenuation level from Table I such that noise floor is reduced to
levels specified in DOCSIS.

Table I.

Rc ( )

Rd ( )

Re ( )

Attenuation (dB)

1304

8.65

1304

654.3

17.42

654.3

432

26.1

432

331.5

35.75

331.5

AD8321

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Distortion and DOCSIS

Care must be taken when selecting attenuation levels specified
in Table I as the output signal from the AD8321 must compen-
sate for the losses resulting from any added attenuation as well
as the insertion losses associated with the diplexer. An increase
in input signal becomes apparent at the upper end of the gain
range and will be needed to achieve the 58 dBmV at the mo-
dem output. The insertion losses of the diplexer may vary,
depending on the quality of the diplexer and whether the fre-
quency of operation is in near proximity to the cut-off fre-
quency of the low-pass filter. Figures 9 and 10 show the
expected second and third harmonic distortion performance vs.
fundamental frequency at various input power levels. These
graphs indicate the worst harmonic levels exhibited over the
entire output range of the AD8321 (i.e., 27 dB to +26 dB).
Figures 9 and 10 are useful when it is necessary to determine
inband harmonic levels (5 MHz to 42 MHz or 5 MHz to
65 MHz). Harmonics that are higher in frequency, as compared
to the cutoff frequency of the low-pass filter of the diplexer, will
be further suppressed by the stop band attenuation level of the
LP filter in the diplexer. Designers must balance the need to
improve noise performance by adding attenuation with the
resulting need for increased signal amplitude while maintaining
DOCSIS specified distortion performance.

Evaluation Board Features and Operation

The AD8321 evaluation board (p/n AD8321-EVAL) and com-
panion software program written in Microsoft Visual Basic are
available through Analog Devices, Inc. and can be used to
control the AD8321 Variable Gain Upstream Power Amplifier
via the parallel port of a PC. This evaluation package provides a
convenient way to program the gain/attenuation of the AD8321
without the addition of any external glue logic. AD8321-EVAL
has been developed to facilitate the use of the AD8321 in an
application targeted at DOCSIS compliance. A low cost Alpha
Industries AS128-73 GaAs 2 Watt High Linearity SPDT RF
switch (referred to as SWb) is included on the evaluation board
(see Figure 28) along with accommodations for a user specified
75

matching attenuator (See Table I for a table of resistor

values of attenuators ranging from 1 dB to 4 dB). The
AD8321

DATEN, CLK and SDATA digital lines are pro-

grammed according to the gain setting and mode of operation
selected using the Windows

interface of the control software

(see Figure 30). The serial interface of the AD8321 is ad-
dressed through the parallel port of a PC using four or more
bits (plus ground). Two additional bits from the parallel port
are used to control the RF switch(s). This software programs
the AD8321 gain or attenuation, incorporates asynchronous
control of the power-down feature (

PD Pin 6) as well as asyn-

chronous control of the Alpha Industries RF switch(es) AS128-
73.* A standard printer cable is used to feed the necessary data
to the AD8321-EVAL board. These features allow the designer
to fully develop and evaluate the upstream signal path begin-
ning at the input to the PA.

Overshoot on PC Printer Ports

The data lines on some PC parallel printer ports have excessive
overshoot. Overshoot presented to the CLK pin (TP7 on the
evaluation board) may cause communications problems. The
evaluation board layout was designed to accommodate a series
resistor and shunt capacitor (R6 and C12) if required to filter or
condition the CLK data.

Between Burst Transient Reduction

In order to reduce the amplitude of the "Burst On/Off Tran-
sient" glitch at the output of the AD8321, when switching from
forward transmit mode to reverse powered down mode, position
the SWb switch in Figure 28 to position "a" before changing the
logic applied to

PD Pin 6 of the AD8321 from Logic 1-to-0

(and also 0-to-1). Use the "Enable Output Switch" feature in
the evaluation board control software (see Figure 31) to select
the appropriate position of the AS128-73 switch. A check in this
box enables the switch to pass upstream data to the output of
the evaluation board. The AS128-73 produces a glitch of ap-
proximately 5 mV p-p regardless of the AD8321 gain setting.
The AD8321-EVAL board comes with resistors and capacitors
installed on the logic lines controlling the RF switch (R8, R9,
C16, C17). These values were selected to reduce the glitch
amplitude to DOCSIS acceptable levels and may be modified if
required. The SPDT function of the AS128-73 RF switch ac-
commodates the need to maintain proper termination when the
diplexer is disconnected from the output of the AD8321. The
AD8321-EVAL board accommodates the needed back termina-
tion (refer to the Cb and Rb of the evaluation circuit).

Differential Inputs

When evaluating the AD8321 in differential input mode, termi-
nation resistor(s) should be selected and applied such that the
combined resistance of the termination resistor(s) and the input
impedance of the AD8321 results in a match between the signal
source impedance and the input impedance of the AD8321. The
evaluation board is designed to accommodate Mini-Circuits T1-
6T-KK81 1:1 transformer for the purposes of converting a
single-ended (i.e., ground referenced) input signal to differen-
tial inputs. The following paragraphs identify three options for
providing differential input signals to the AD8321 evaluation
board. Option 1 uses a transformer to produce a truly differen-
tial input signal. The termination resistor(s) specified in Option
1 and 2 may also be used without the transformer if a differen-
tial signal source is available. Option 2 uses a transformer and-
produces ground referenced input signals that are separated in
phase by 180

. Option 3 relies on differential signals provided

by the user and does not employ a transformer for single-to-
differential conversion.

Differential Input Option 1: Install the Mini-Circuits T1-6T-
KK81 1:1 transformer in the T1 location of the evaluation
board. Jumpers J1, J2 and J3 should be applied pointing in the
direction of the transformer. A differential input termination
resistor of 82.5

can be used in the R3 position. This value

should be used when the single-ended input signal has a source
impedance of 75

. In this configuration, the input signal must

be applied to the VIN+/DIFF IN port of the evaluation board.
An open circuit is required in R1, R2 and J4 positions resulting
in a 75

differential input termination to the AD8321. If a

single-ended input source is applied to the VIN+/DIFF IN

port, the R3 value should be 53.6

Windows is a registered trademark of Microsoft Corporation.
*Alpha Industries @ www.alphaind.com

AD8321

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Differential Input Option 2: Install the Mini-Circuits T1-6T-
KK81 1:1 transformer in the T1 location of the evaluation
board. Jumpers J1, J2 and J3 should be applied pointing in the
direction of the transformer. Apply an open circuit in the R3
position while J4 is applied connecting the center-tap of the
secondary to ground. A 41

resistor should be used between

each input and ground at R1 and R2. This option will also
result in a 75

differential input termination to the AD8321.

If a 50

single-ended input source is applied to the VIN+/

DIFF IN port, the R1 and R2 values should be 26.7

Differential Input Option 3: A differential input may be ap-
plied to both VIN and VIN+ inputs of the evaluation board. In
this example, no transformer is employed. Jumpers J1, J2 and J3
are installed in line with the input signals. Select the differential
input termination configuration of either Option 1 or Option 2.
Apply Option 1 resistor value to R3 for a true differential input
or apply Option 2 values to R1 and R2 to produce ground refer-
enced inputs that are separated in phase by 180

. If the differen-

tial input signal source impedance is anything other than 75

or 50

, calculate the appropriate value according to the equa-

tions below:

For Option 1 Configurations:

Desired Input Impedance = R3 900

For Option 2 and 3 (R1 = R2 = R):

Desired Input Impedance = 2

(R 450)

DIFF IN

AD8321

DIFF IN

AD8321

VIN+

AD8321

OPTION 1 DIFFERENTIAL INPUT TERMINATION

OPTION 2 DIFFERENTIAL INPUT TERMINATION

OPTION 3 DIFFERENTIAL INPUT TERMINATION

VIN

Figure 27. Differential Input Termination Options

Controlling the Evaluation Board from a PC

The AD8321-EVAL package comes with the circuit described
by Figure 28 and includes a 2 dB attenuator (reference Rc, Rd
and Re) and the control software allowing the user to program
the gain/attenuation of the AD8321 via a standard printer cable
connected to the parallel port of a PC.

Install Software

To install the "CABDRIVE" software that controls the AD8321-
EVAL evaluation circuit, close all Windows applications and
select the "SETUP" file located on Disk 1 of the AD8321-
EVAL software. Follow the on screen instructions (see Figure
29) and insert Disk 2 when prompted to do so. Enter the path
of the directory into which the control software will be installed.
Select the button in the upper left corner to begin the installa-
tion of "CABDRIVE" software into the specified directory.

Running the Software

To invoke the control software, select the "Ad8321" icon from
the directory containing the installed software. After invoking
the control software, choose the appropriate printer port from
the display portrayed in Figure 30.

Controlling the Gain/Attenuation of AD8321

The AD8321 control panel has four different functions. The
slide bar controls the gain/attenuation of the AD8321. Adjust
the slider to the gain/attenuation displayed in units of dB. The
additional displays show the selection in units of Volts (output)/
Volts (input), and the corresponding control codes in decimal,
binary and hexadecimal. (See Figure 31.)

"POWER UP" and "POWER DOWN"

The buttons marked "Power Up" and "Power Down" select
the mode of operation of the AD8321. The "Power Up" button
puts the AD8321 in forward transmit mode feeding the condi-
tioned signal to the VOUT port on the evaluation board. Con-
versely, the "Power Down" button selects the reverse mode
where the forward signal transmission is disabled and the low
noise reverse amplifier actively maintains a 75

back termina-

tion. These features may be selected asynchronously (at any
time). (See the section on Between Burst Transient Reduction
for more specific details.)

Enable Output Switch

An Alpha Industries AS128-73 GaAs 2W Hi Linearity switch is
installed on a standard AD8321-EVAL circuit and is controlled
by the check box on the control panel portrayed in Figure 31.
This feature is intended to remove the output of the AD8321
from the VOUT port prior to using the "Power Up" and
"Power Down" feature described above. This application circuit
may be used to reduce any transients created between bursts to
DOCSIS compliant levels. (See the section on Between Burst
Transient Reduction for more specific details.)

AD8321

REV. 0

EVALUATION BOARD BILL OF MATERIALS

AD8321 Evaluation Board Rev. B SINGLE- ENDED INVERTING INPUT March 17, 1999

Qty.

Description

Vendor

Ref Desc.

F 16 V. 1350 size tantalum chip capacitor

ADS# 4-7-6

C6 & C14

0.1

F 50 V. 1206 size ceramic chip capacitor

ADS# 4-5-18

C1C5, C7C11, Cbe

1,000 pF 50 V. 1206 size ceramic chip capacitor

ADS# 4-5-20

C12, C16 & C17

82.5