REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD826
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
High-Speed, Low-Power
Dual Operational Amplifier
CONNECTION DIAGRAM
8-Lead Plastic Mini-DIP and SO Package
1
2
3
4
8
7
6
5
AD826
V+
OUT2
IN2
+IN2
OUT1
IN1
+IN1
V
The AD826 features high output current drive capability of
50 mA min per amp, and is able to drive unlimited capacitive
loads. With a low power supply current of 15 mA max for both
amplifiers, the AD826 is a true general purpose operational
amplifier.
The AD826 is ideal for power sensitive applications such as video
cameras and portable instrumentation. The AD826 can operate
from a single +5 V supply, while still achieving 25 MHz of band-
width. Furthermore the AD826 is fully specified from a single
+5 V to
±15 V power supplies.
The AD826 excels as an ADC/DAC buffer or active filter in
data acquisition systems and achieves a settling time of 70 ns
to 0.01%, with a low input offset voltage of 2 mV max. The
AD826 is available in small 8-lead plastic mini-DIP and SO
packages.
10
90
100
0%
500ns
5V
5V
C
L
= 100pF
C
L
= 1000pF
FEATURES
High Speed:
50 MHz Unity Gain Bandwidth
350 V/ s Slew Rate
70 ns Settling Time to 0.01%
Low Power:
7.5 mA Max Power Supply Current Per Amp
Easy to Use:
Drives Unlimited Capacitive Loads
50 mA Min Output Current Per Amplifier
Specified for +5 V, 5 V and 15 V Operation
2.0 V p-p Output Swing into a 150 Load
(V
S
= +5 V)
Good Video Performance
Differential Gain & Phase Error of 0.07% & 0.11
Excellent DC Performance:
2.0 mV Max Input Offset Voltage
APPLICATIONS
Unity Gain ADC/DAC Buffer
Cable Drivers
8- and 10-Bit Data Acquisition Systems
Video Line Driver
Active Filters
PRODUCT DESCRIPTION
The AD826 is a dual, high speed voltage feedback op amp. It
is ideal for use in applications which require unity gain stability
and high output drive capability, such as buffering and cable
driving. The 50 MHz bandwidth and 350 V/
µs slew rate make
the AD826 useful in many high speed applications including:
video, CATV, copiers, LCDs, image scanners and fax machines.
TEKTRONIX
P6201 FET
PROBE
HP PULSE
GENERATOR
1/2
AD826
1k
50
1k
C
L
V
OUT
V
IN
TEKTRONIX
7A24 FET
PREAMP
V
S
0.01 F
3.3 F
0.01 F
V
S
3.3 F
1
3
2
Driving a Large Capacitive Load
REV. B
2
AD826SPECIFICATIONS
(@ T
A
= +25 C, unless otherwise noted)
Parameter
Conditions
V
S
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Unity Gain Bandwidth
±5 V
30
35
MHz
±15 V
45
50
MHz
0, +5 V
25
29
MHz
Bandwidth for 0.1 dB Flatness
Gain = +1
±5 V
10
20
MHz
±15 V
25
55
MHz
0, +5 V
10
20
MHz
Full Power Bandwidth
1
V
OUT
= 5 V p-p
R
LOAD
= 500
±5 V
15.9
MHz
V
OUT
= 20 V p-p
R
LOAD
= 1 k
±15 V
5.6
MHz
Slew Rate
R
LOAD
= 1 k
±5 V
200
250
V/
µs
Gain = 1
±15 V
300
350
V/
µs
0, +5 V
150
200
V/
µs
Settling Time to 0.1%
2.5 V to +2.5 V
±5 V
45
ns
0 V10 V Step, A
V
= 1
±15 V
45
ns
to 0.01%
2.5 V to +2.5 V
±5 V
70
ns
0 V10 V Step, A
V
= 1
±15 V
70
ns
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion
F
C
= 1 MHz
±15 V
78
dB
Input Voltage Noise
f = 10 kHz
±5 V, ±15 V
15
nV/
Hz
Input Current Noise
f = 10 kHz
±5 V, ±15 V
1.5
pA/
Hz
Differential Gain Error
NTSC
±15 V
0.07
0.1
%
(R1 = 150
)
Gain = +2
±5 V
0.12
0.15
%
0, +5 V
0.15
%
Differential Phase Error
NTSC
±15 V
0.11
0.15
Degrees
(R1 = 150
)
Gain = +2
±5 V
0.12
0.15
Degrees
0, +5 V
0.15
Degrees
DC PERFORMANCE
Input Offset Voltage
±5 V to ±15 V
0.5
2
mV
T
MIN
to T
MAX
3
mV
Offset Drift
10
µV/°C
Input Bias Current
±5 V, ±15 V
3.3
6.6
µA
T
MIN
10
µA
T
MAX
4.4
µA
Input Offset Current
±5 V, ±15 V
25
300
nA
T
MIN
to T
MAX
500
nA
Offset Current Drift
0.3
nA/
°C
Open-Loop Gain
V
OUT
=
±2.5 V
±5 V
R
LOAD
= 500
2
4
V/mV
T
MIN
to T
MAX
1.5
V/mV
R
LOAD
= 150
1.5
3
V/mV
V
OUT
=
±10 V
±15 V
R
LOAD
= 1 k
3.5
6
V/mV
T
MIN
to T
MAX
2
5
V/mV
V
OUT
=
±7.5 V
±15 V
R
LOAD
= 150
(50 mA Output)
2
4
V/mV
INPUT CHARACTERISTICS
Input Resistance
300
k
Input Capacitance
1.5
pF
Input Common-Mode Voltage Range
±5 V
+3.8
+4.3
V
2.7
3.4
V
±15 V
+13
+14.3
V
12
13.4
V
0, +5 V
+3.8
+4.3
V
+1.2
+0.9
V
Common-Mode Rejection Ratio
V
CM
=
±2.5 V, T
MIN
T
MAX
±5 V
80
100
dB
V
CM
=
±12 V
±15 V
86
120
dB
T
MIN
to T
MAX
±15 V
80
100
dB
REV. B
3
AD826
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±18 V
Internal Power Dissipation
2
Plastic (N) . . . . . . . . . . . . . . . . . . . . . See Derating Curves
Small Outline (R) . . . . . . . . . . . . . . . . See Derating Curves
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . .
±V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . .
±6 V
Output Short Circuit Duration . . . . . . . See Derating Curves
Storage Temperature Range (N, R) . . . . . . . 65
°C to +125°C
Operating Temperature Range . . . . . . . . . . 40
°C to +85°C
Lead Temperature Range (Soldering 10 seconds) . . . +300
°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability .
2
Specification is for device in free air: 8-lead plastic package,
JA
= 100
°C/watt;
8-lead SOIC package,
JA
= 155
°C/watt.
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Option
AD826AN
40
°C to +85°C 8-Lead Plastic DIP
N-8
AD826AR
40
°C to +85°C 8-Lead Plastic SOIC
SO-8
AD826AR-REEL7 40
°C to +85°C 7" Tape & Reel SOIC SO-8
AD826AR-REEL
40
°C to +85°C 13" Tape & Reel SOIC SO-8
Parameter
Conditions
V
S
Min
Typ
Max
Unit
OUTPUT CHARACTERISTICS
Output Voltage Swing
R
LOAD
= 500
±5 V
3.3
3.8
±V
R
LOAD
= 150
±5 V
3.2
3.6
±V
R
LOAD
= 1 k
±15 V
13.3
13.7
±V
R
LOAD
= 500
±15 V
12.8
13.4
±V
R
LOAD
= 500
0, +5 V
+1.5,
+3.5
V
Output Current
±15 V
50
mA
±5 V
50
mA
0, +5 V
30
mA
Short-Circuit Current
±15 V
90
mA
Output Resistance
Open Loop
8
MATCHING CHARACTERISTICS
Dynamic
Crosstalk
f = 5 MHz
±15 V
80
dB
Gain Flatness Match
G = +1, f = 40 MHz
±15 V
0.2
dB
Slew Rate Match
G = 1
±15 V
10
V/
µs
DC
Input Offset Voltage Match
T
MIN
T
MAX
±5 V to ±15 V
0.5
2
mV
Input Bias Current Match
T
MIN
T
MAX
±5 V to ±15 V
0.06
0.8
µA
Open-Loop Gain Match
V
O
=
±10 V, R
LOAD
= 1 k
,
T
MIN
T
MAX
±15 V
0.15
0.01
mV/V
Common-Mode Rejection Ratio Match
V
CM
=
±12 V, T
MIN
T
MAX
±15 V
80
100
dB
Power Supply Rejection Ratio Match
±5 V to ±15 V, T
MIN
T
MAX
80
100
dB
POWER SUPPLY
Operating Range
Dual Supply
±2.5
±18
V
Single Supply
+5
+36
V
Quiescent Current/Amplifier
±5 V
6.6
7.5
mA
T
MIN
to T
MAX
±5 V
7.5
mA
±15 V
7.5
mA
T
MIN
to T
MAX
±15 V
6.8
7.5
mA
Power Supply Rejection Ratio
V
S
=
±5 V to ±15 V, T
MIN
to T
MAX
75
86
dB
NOTES
1
Full power bandwidth = slew rate/2
V
PEAK
.
Specifications subject to change without notice.
ESD SUSCEPTIBILITY
ESD (electrostatic discharge) sensitive device. Electrostatic charges
as high as 4000 volts, which readily accumulate on the human
body and on test equipment, can discharge without detection.
Although the AD826 features proprietary ESD protection cir-
cuitry, permanent damage may still occur on these devices
if they are subjected to high energy electrostatic discharges.
Therefore, proper ESD precautions are recommended to avoid
any performance degradation or loss of functionality.
2.0
0
50
90
1.5
0.5
30
1.0
50
70
30
10
10
80
40
40
60
20
0
20
AMBIENT TEMPERATURE C
MAXIMUM POWER DISSIPATION
Watts
8-LEAD MINI-DIP PACKAGE
8-LEAD SOIC PACKAGE
T
J
= +150 C
Maximum Power Dissipation vs. Temperature for Different
Package Types
REV. B
AD826
4
20
0
0
20
15
5
5
10
10
15
INPUT COMMON-MODE RANGE
Volts
SUPPLY VOLTAGE Volts
V
CM
+V
CM
Figure 1. Common-Mode Voltage Range vs. Supply
20
0
0
20
15
5
5
10
10
15
SUPPLY VOLTAGE Volts
OUTPUT VOLTAGE SWING
Volts
R
L
= 150V
R
L
= 500V
Figure 2. Output Voltage Swing vs. Supply
30
0
10k
15
5
100
10
10
20
1k
25
LOAD RESISTANCE
OUTPUT VOLTAGE SWING
Volts p-p
V
S
= 15V
V
S
= 5V
Figure 3. Output Voltage Swing vs. Load Resistance
40 C
7.7
5.7
0
20
7.2
6.2
5
6.7
10
15
SUPPLY VOLTAGE Volts
QUIESCENT SUPPLY CURRENT PER AMP
mA
+25 C
+85 C
Figure 4. Quiescent Supply Current per Amp vs. Supply
Voltage for Various Temperatures
SLEW RATE
V/
s
20
5
0
15
10
SUPPLY VOLTAGE Volts
200
300
350
400
250
Figure 5. Slew Rate vs. Supply Voltage
100
1
0.01
1k
10k
100M
10M
1M
100k
0.1
10
FREQUENCY Hz
CLOSED-LOOP OUTPUT IMPEDANCE
Figure 6. Closed-Loop Output Impedance vs. Frequency
Typical Characteristics
REV. B
AD826
5
7
1
140
4
2
40
3
60
6
5
120
80
60
40
100
20
0
20
TEMPERATURE C
INPUT BIAS CURRENT
A
Figure 7. Input Bias Current vs. Temperature
130
30
140
90
50
40
70
60
110
120
100
80
60
40
20
0
20
TEMPERATURE C
SHORT CIRCUIT CURRENT
mA
SINK CURRENT
SOURCE CURRENT
Figure 8. Short Circuit Current vs. Temperature
100
20
60
140
80
40
40
60
100
120
80
60
40
20
0
20
TEMPERATURE C
PHASE MARGIN
Degrees
20
80
40
60
UNITY GAIN BANDWIDTH
MHz
PHASE MARGIN
GAIN BANDWIDTH
Figure 9. Unity Gain Bandwidth and Phase Margin
vs. Temperature
100
20
1G
40
0
10k
20
1k
80
60
100M
10M
1M
100k
FREQUENCY Hz
+100
+40
0
+20
+80
+60
PHASE MARGIN
Degrees
OPEN-LOOP GAIN
dB
GAIN 15V SUPPLIES
GAIN 5V SUPPLIES
PHASE 5V OR
15V SUPPLIES
RL = 1k
Figure 10. Open-Loop Gain and Phase Margin
vs. Frequency
4
1
100
1k
10k
2
3
5
6
LOAD RESISTANCE
OPEN-LOOP GAIN
V/mV
15V
5V
7
Figure 11. Open-Loop Gain vs. Load Resistance
100
10
100M
30
20
1k
100
40
50
60
70
80
90
10M
1M
100k
10k
FREQUENCY Hz
PSR
dB
POSITIVE
SUPPLY
NEGATIVE
SUPPLY
Figure 12. Power Supply Rejection vs. Frequency
REV. B
AD826
6
140
60
1k
10M
120
80
10k
100
100k
1M
FREQUENCY Hz
CMR
dB
Figure 13. Common-Mode Rejection vs. Frequency
30
10
0
100k
1M
100M
10M
20
FREQUENCY Hz
OUTPUT VOLTAGE
Volts p-p
R
L
= 150
R
L
= 1k
Figure 14. Large Signal Frequency Response
10
10
160
4
8
20
6
0
2
2
0
4
6
8
140
120
100
80
60
40
SETTLING TIME ns
OUTPUT SWING FROM 0 TO
V
0.01%
0.1%
1%
1%
0.01%
0.1%
Figure 15. Output Swing and Error vs. Settling Time
40
100
10M
70
90
1k
80
100
50
60
1M
100k
10k
FREQUENCY Hz
HARMONIC DISTORTION
dB
V
IN
= 1V p-p
GAIN = +2
2
ND
HARMONIC
3
RD
HARMONIC
Figure 16. Harmonic Distortion vs. Frequency
50
0
10M
30
10
10
20
3
40
1M
100k
10k
1k
100
FREQUENCY Hz
INPUT VOLTAGE NOISE
nV/ Hz
Figure 17. Input Voltage Noise Spectral Density
380
300
60
140
360
320
40
340
100
120
80
60
40
20
0
20
TEMPERATURE C
SLEW RATE
V/
s
Figure 18. Slew Rate vs. Temperature
REV. B
AD826
7
FREQUENCY Hz
GAIN
dB
5
0
5
100k
1M
100M
10M
1
2
3
4
1
2
3
4
V
S
15V
5V
5V
0.1dB
FLATNESS
55MHz
20MHz
20MHz
V
OUT
V
IN
781
150
V
S
= 15V
V
S
= 5V
V
S
= 5V
Figure 19. Closed-Loop Gain vs. Frequency
SUPPLY VOLTAGE Volts
0.13
0.07
0.10
DIFFERENTIAL PHASE
Degrees
DIFFERENTIAL GAIN
Percent
0.10
15
0.13
0.11
0.12
5
10
DIFF GAIN
DIFF PHASE
Figure 20. Differential Gain and Phase vs. Supply Voltage
30
70
110
100k
100M
10M
1M
10k
90
50
60
80
100
40
FREQUENCY Hz
CROSSTALK
dB
15V
R
L
= 1k
5V
R
L
= 150
Figure 21. Crosstalk vs. Frequency
FREQUENCY HZ
5
0
5
100k
1M
100M
10M
1
2
3
4
1
2
3
4
0.1dB
V
S
C
C
FLATNESS
15V
3pF
16MHz
5V
4pF
14MHz
5V
6pF
12MHz
1k
1k
V
IN
C
C
V
OUT
GAIN
dB
V
S
= 15V
V
S
=
5V
V
S
=
5V
Figure 22. Closed-Loop Gain vs. Frequency, Gain = 1
FREQUENCY Hz
GAIN
dB
1.0
0
1.0
100k
1M
100M
10M
0.2
0.4
0.6
0.8
0.2
0.4
0.6
0.8
V
S
= 15V
V
S
= 5V
V
S
= +5V
Figure 23. Gain Flatness Matching vs. Supply, G = +1
1/2
AD826
3
2
1
USE GROUND PLANE
PINOUT SHOWN IS FOR MINIDIP PACKAGE
V
IN
V
S
8
R
L
= 150 FOR V
S
= 5V, 1k FOR V
S
= 15V
R
L
1 F
0.1 F
1/2
AD826
5
6
7
4
R
L
V
S
1 F
0.1 F
V
OUT
Figure 24. Crosstalk Test Circuit
REV. B
AD826
8
TEKTRONIX
P6201 FET
PROBE
PULSE (LS)
OR
FUNCTION (SS)
GENERATOR
1/2
AD826
R
IN
100
50
1k
R
L
V
OUT
V
IN
TEKTRONIX
7A24
PREAMP
V
S
0.01 F
3.3 F
0.01 F
V
S
3.3 F
Figure 25. Noninverting Amplifier Configuration
10
90
100
0%
50ns
5V
5V
Figure 26. Noninverting Large Signal Pulse Response,
R
L
= 1 k
10
90
100
0%
50ns
5V
5V
Figure 27. Noninverting Large Signal Pulse Response,
R
L
= 150
10
90
100
0%
50ns
200mV
200mV
Figure 28. Noninverting Small Signal Pulse Response,
R
L
= 1 k
5V
10
90
100
0%
50ns
200mV
200mV
Figure 29. Noninverting Small Signal Pulse Response,
R
L
= 150
REV. B
AD826
9
V
S
TEKTRONIX
P6201 FET
PROBE
PULSE (LS)
OR FUNCTION (SS)
GENERATOR
1/2
AD826
1k
0.01 F
R
L
V
OUT
TEKTRONIX
7A24
PREAMP
R
IN
1k
50
V
IN
3.3 F
0.01 F
V
S
3.3 F
Figure 30. Inverting Amplifier Configuration
10
90
100
0%
5V
50ns
5V
Figure 31. Inverting Large Signal Pulse Response,
R
L
= 1 k
10
90
100
0%
5V
50ns
5V
Figure 32. Inverting Large Signal Pulse Response,
R
L
= 150
10
90
100
0%
200mV
50ns
200mV
Figure 33. Inverting Small Signal Pulse Response,
R
L
= 1 k
10
90
100
0%
200mV
50ns
200mV
Figure 34. Inverting Small Signal Pulse Response,
R
L
= 150
REV. B
AD826
10
THEORY OF OPERATION
The AD826 is a low cost, wide band, high performance dual
operational amplifier which can drive heavy capacitive and
resistive loads. It also achieves a constant slew rate, bandwidth
and settling time over its entire specified temperature range.
The AD826 (Figure 35) consists of a degenerated NPN differen-
tial pair driving matched PNPs in a folded-cascode gain stage.
The output buffer stage employs emitter followers in a class AB
amplifier which delivers the necessary current to the load while
maintaining low levels of distortion.
C
F
IN
+IN
NULL 1
NULL 8
OUTPUT
+V
S
V
S
Figure 35. Simplified Schematic
The capacitor, C
F
, in the output stage mitigates the effect of
capacitive loads. With low capacitive loads, the gain from the
compensation node to the output is very close to unity. In this
case, C
F
is bootstrapped and does not contribute to the overall
compensation capacitance of the device. As the capacitive load
is increased, a pole is formed with the output impedance of the
output stage. This reduces the gain, and therefore, C
F
is
incompletely bootstrapped. Effectively, some fraction of C
F
contributes to the overall compensation capacitance, reducing
the unity gain bandwidth. As the load capacitance is further
increased, the bandwidth continues to fall, maintaining the
stability of the amplifier.
INPUT CONSIDERATIONS
An input protection resistor (R
IN
in Figure 25) is required in
circuits where the input to the AD826 will be subjected to
transient or continuous overload voltages exceeding the
± 6 V
maximum differential limit. This resistor provides protection for
the input transistors by limiting their maximum base current.
For high performance circuits, it is recommended that a "bal-
ancing" resistor be used to reduce the offset errors caused by
bias current flowing through the input and feedback resistors.
The balancing resistor equals the parallel combination of R
IN
and R
F
and thus provides a matched impedance at each input
terminal. The offset voltage error will then be reduced by more
than an order of magnitude.
APPLYING THE AD826
The AD826 is a breakthrough dual amp that delivers precision
and speed at low cost with low power consumption. The AD826
offers excellent static and dynamic matching characteristics,
combined with the ability to drive heavy resistive and capacitive
loads.
As with all high frequency circuits, care should be taken to main-
tain overall device performance as well as their matching. The
following items are presented as general design considerations.
Circuit Board Layout
Input and output runs should be laid out so as to physically
isolate them from remaining runs. In addition, the feedback
resistor of each amplifier should be placed away from the
feedback resistor of the other amplifier, since this greatly
reduces inter-amp coupling.
Choosing Feedback and Gain Resistors
In order to prevent the stray capacitance present at each amplifier's
summing junction from limiting its performance, the feedback
resistors should be
1 k. Since the summing junction capaci-
tance may cause peaking, a small capacitor (1 pF5 pF) may
be paralleled with R
F
to neutralize this effect. Finally, sockets
should be avoided, because of their tendency to increase interlead
capacitance.
Power Supply Bypassing
Proper power supply decoupling is critical to preserve the
integrity of high frequency signals. In carefully laid out designs,
decoupling capacitors should be placed in close proximity to the
supply pins, while their lead lengths should be kept to a mini-
mum. These measures greatly reduce undesired inductive effects
on the amplifier's response.
Though two 0.1
µF capacitors will typically be effective in
decoupling the supplies, several capacitors of different values
can be paralleled to cover a wider frequency range.
REV. B
AD826
11
SINGLE SUPPLY OPERATION
An exciting feature of the AD826 is its ability to perform well in a
single supply configuration (see Figure 37). The AD826 is ideally
suited for applications that require low power dissipation and high
output current and those which need to drive large capacitive
loads, such as high speed buffering and instrumentation.
Referring to Figure 36, careful consideration should be given to
the proper selection of component values. The choices for this
particular circuit are: (R1 + R3) R2 combine with C1 to form a
low frequency corner of approximately 30 Hz.
V
S
1/2
AD826
R2
10k
3.3 F
0.01 F
C3
0.1 F
V
OUT
R1
9k
R3
1k
C2
0.1 F
V
IN
C1
1 F
C
L
200pF
R
L
150
C
OUT
Figure 36. Single Supply Amplifier Configuration
R3 and C2 reduce the effect of the power supply changes on the
output by low-pass filtering with a corner at
1
2
R
3
C
2
.
The values for R
L
and C
L
were chosen to demonstrate the
AD826's exceptional output drive capability. In this configura-
tion, the output is centered around 2.5 V. In order to eliminate
the static dc current associated with this level, C3 was inserted
in series with R
L
.
10
90
100
0%
500mV
100ns
500mV
Figure 37. Single Supply Pulse Response, G = +1,
R
L
= 150
, C
L
= 200 pF
PARALLEL AMPS PROVIDE 100 mA TO LOAD
By taking advantage of the superior matching characteristics of
the AD826, enhanced performance can easily be achieved by
employing the circuit in Figure 38. Here, two identical cells are
paralleled to obtain even higher load driving capability than that
of a single amplifier (100 mA min guaranteed). R1 and R2 are
included to limit current flow between amplifier outputs that
would arise in the presence of any residual mismatch.
V
S
V
IN
V
OUT
1k
R1
5
R2
5
V
S
1k
1k
1k
R
L
1/2
AD826
1/2
AD826
0.1 F
1 F
0.1 F
1 F
Figure 38. Parallel Amp Configuration
REV. B
AD826
12
SINGLE-ENDED TO DIFFERENTIAL LINE DRIVER
Outstanding CMRR (> 80 dB @ 5 MHz), high bandwidth, wide
supply voltage range, and the ability to drive heavy loads, make
the AD826 an ideal choice for many line driving applications.
In this application, the AD830 high speed video difference
amp serves as the differential line receiver on the end of a back
terminated, 50 ft., twisted-pair transmission line (see Figure 40).
The overall system is configured in a gain of +1 and has a 3 dB
bandwidth of 14 MHz. Figure 39 is the pulse response with a
2 V p-p, 1 MHz signal input.
10
90
100
0%
2V
200ns
2V
Figure 39. Pulse Response
15V
1/2
AD826
0.01 F
2.2 F
1/2
AD826
36
1.05k
5pF
BNC
I
N
15V
AD830
V
OUT
50 FEET TWISTED PAIR
Z = 72
36
0.1 F
1.05k
5pF
1.05k
1.05k
0.1 F
0.01 F
2.2 F
36
36
15V
0.01 F
0.1 F
15V
0.1 F
0.01 F
Figure 40. Differential Line Driver
LOW DISTORTION LINE DRIVER
The AD826 can quickly be turned into a powerful, low distor-
tion line driver (see Figure 41). In this arrangement the AD826
can comfortably drive a 75
back-terminated cable, with a
5 MHz, 2 V p-p input; all of this while achieving the harmonic
distortion performance outlined in the following table.
Configuration
2nd Harmonic
1. No Load
78.5 dBm
2. 150
R
L
Only
63.8 dBm
3. 150
R
L
7.5
R
C
70.4 dBm
In this application one half of the AD826 operates at a gain of
2.1 and supplies the current to the load, while the other pro-
vides the overall system gain of 2. This is important for two
reasons: the first is to keep the bandwidth of both amplifiers the
same, and the second is to preserve the AD826's ability to oper-
ate from low supply voltages. R
C
varies with the load and must
be chosen to satisfy the following equation:
R
C
= MR
L
where M is defined by [(M+ 1) G
S
= G
D
] and G
D
= Driver's Gain,
G
S
= System Gain.
1.1k
1k
1k
R
L
1/2
AD826
1/2
AD826
R
C
7.5
1k
75
75
75
V
S
1 F
0.1 F
0.1 F
1 F
Figure 41. Low Distortion Amplifier
REV. B
AD826
13
HIGH PERFORMANCE ADC BUFFER
Figure 42 is a schematic of a 12-bit high speed analog-to-digital
converter. The AD826 dual op amp takes a single ended input
and drives the AD872 A/D converter differentially, thus reduc-
ing 2nd harmonic distortion. Figure 43 is a FFT of a 1 MHz
input, sampled at 10 MHz with a THD of 78 dB. The AD826
can be used to amplify low level signals so that the entire range
of the converter is used. The ability of the AD826 to perform on
a
±5 volt supply or even with a single 5 volts combined with its
rapid settling time and ability to deliver high current to compli-
cated loads make it a very good flash A/D converter buffer as
well as a very useful general purpose building block.
V
S
1/2
AD826
52.5
0.1 F
1k
1k
1k
1k
AD872
12-BIT
10MSPS
ADC
V
INA
V
INB
50
COAX
CABLE
V
IN
500mV
p-p MAX
COMMON
100 F
25V
1/2
AD826
V
S
0.1 F
100 F
25V
V
S
V
S
5V
5V
Figure 42. A Differential Input Buffer for High
Bandwidth ADCs
Figure 43. FFT, Buffered A/D Converter
REV. B
AD826
14
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic Mini-DIP (N) Package
0.011
±0.003
(0.28
±0.08)
0.30 (7.62)
REF
15
°
0
°
PIN 1
4
5
8
1
0.25
(6.35)
0.31
(7.87)
0.10
(2.54)
BSC
SEATING
PLANE
0.035
±0.01
(0.89
±0.25)
0.18
±0.03
(4.57
±0.76)
0.033
(0.84)
NOM
0.018
±0.003
(0.46
±0.08)
0.125
(3.18)
MIN
0.165
±0.01
(4.19
±0.25)
0.39 (9.91) MAX
8-Lead SO (R) Package
8
5
4
1
0.1968 (5.00)
0.1890 (4.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0500 (1.27)
BSC
0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
0
0.0196 (0.50)
0.0099 (0.25)
45
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C1807a06/00 (rev. B) 00877
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