AD8190 2:1 HDMI/DVI Switch with Equalization Data Sheet (Rev. 0)

2:1 HDMI/DVI Switch with Equalization

AD8190

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

FEATURES

Two inputs, one output HDMI/DVI links
Enables HDMI 1.2a-compliant receiver

Four TMDS channels per link

Supports 250 Mbps to 1.65 Gbps data rates
Supports 25 MHz to 165 MHz pixel clocks
Equalized inputs for operation with long HDMI cables

(20 meters at 1080p)

Fully buffered unidirectional inputs/outputs
Globally switchable 50 on-chip terminations
Pre-emphasized outputs
Low added jitter
Single-supply operation (3.3 V)

Four auxiliary channels per link

Bidirectional unbuffered inputs/outputs
Flexible supply operation (3.3 V to 5 V)
HDCP standard compatible
Allows switching of DDC bus and two additional signals

Output disable feature

Reduced power dissipation
Output termination removal

Two AD8190s support HDMI/DVI dual-link
Standards compliant: HDMI receiver, HDCP, DVI
Serial (I

C slave) control interface

56-lead, 8 mm x 8 mm, LFCSP, Pb-free package

APPLICATIONS

Multiple input displays
Projectors
A/V receivers
Set-top boxes
Advanced television (HDTV) sets

FUNCTIONAL BLOCK DIAGRAM

LOW SPEED

UNBUFFERED

AVCC
DVCC
AMUXVCC
AVEE
DVEE

VTTO

OP[3:0]

AUX_COM[3:0]

I2C_SDA

I2C_SCL

I2C_ADDR

ON[3:0]

AD8190

RESET

CONTROL

LOGIC

CONFIG

INTERFACE

SERIAL INTERFACE

VTTI

IP_A[3:0]

IN_A[3:0]

VTTI

IP_B[3:0]

IN_B[3:0]

SWITCH

CORE

AUX_A[3:0]

AUX_B[3:0]

BIDIRECTIONAL

HIGH SPEED

BUFFERED

061

22-

SWITCH

CORE

Figure 1.

TYPICAL APPLICATION

01:18

DVD

DVD PLAYER

SET-TOP BOX

HDTV SET

HDMI

RECEIVER

AD8190

061

22-

002

Figure 2. Typical AD8190 Application for HDTV Sets

GENERAL DESCRIPTION

The AD8190 is an HDMI/DVI switch featuring equalized
TMDS inputs and pre-emphasized TMDS outputs, ideal for
systems with long cable runs. Outputs can be set to a high
impedance state to reduce the power dissipation and/or allow
the construction of larger arrays using the wire-OR technique.

The AD8190 is provided in a space saving, 56-lead, LFCSP,
surface-mount, Pb-free, plastic package and is specified to
operate over the -40°C to +85°C temperature range.

PRODUCT HIGHLIGHTS

Supports data rates up to 1.65 Gbps, enabling UXGA
(1600 × 1200) DVI resolutions and 1080p HDMI formats.

Input cable equalizer enables use of long cables at the
input (more than 20 meters of 24 AWG cable at 1080p).

Auxiliary switch allows routing of the DDC bus and two
additional single-ended signals for a single chip, fully
HDMI 1.2a receive-compliant solution.

AD8190

Rev. 0 | Page 2 of 24

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Typical Application........................................................................... 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

Maximum Power Dissipation ..................................................... 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 12

Introduction ................................................................................ 12

Input Channels............................................................................ 12

Output Channels ........................................................................ 12

Switching Mode .......................................................................... 13

Auxiliary Lines Switching.......................................................... 13

Serial Control Interface ................................................................. 14

Reset ............................................................................................. 14

Write Procedure.......................................................................... 14

Read Procedure........................................................................... 15

Switching/Update Delay ............................................................ 15

Configuration Registers................................................................. 16

High

Speed Device Modes Register ......................................... 16

Auxiliary Device Modes Register............................................. 16

Receiver Settings Register ......................................................... 17

Input Termination Pulse Register ............................................ 17

Receive Equalizer Register ........................................................ 17

Transmitter Settings Register.................................................... 17

Application Notes ........................................................................... 18

Pinout........................................................................................... 18

Cable Lengths and Equalization............................................... 19

The AD8190 as a Single-Channel Buffer ................................ 19

PCB Layout Guidelines.............................................................. 19

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 23

REVISION HISTORY

7/06--Revision 0: Initial Version

AD8190

Rev. 0 | Page 3 of 24

SPECIFICATIONS

= 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input swing =

1000 mV, TMDS outputs terminated with external 50 resistors to 3.3 V, unless otherwise noted.

Table 1.

Parameter Conditions/Comments

Min

Typ

Max

Unit

DYNAMIC PERFORMANCE

Maximum Data Rate (DR) per Channel

NRZ

1.65

Gbps

Bit Error Rate (BER)

PRBS 2

- 1

-9

Added Deterministic Jitter

1.65 Gbps, PRBS 2

- 1

(p-p)

Added Random Jitter

ps (rms)

Differential Intrapair Skew At

output

Differential Interpair Skew

At output

EQUALIZATION PERFORMANCE

Receiver (Highest Setting)

Boost frequency = 825 MHz

Transmitter (Highest Setting)

Boost frequency = 825 MHz

INPUT CHARACTERISTICS

Input Voltage Swing

Differential

150

1200

Input Common-Mode Voltage (V

ICM

)

AVCC - 800

AVCC

OUTPUT CHARACTERISTICS

High Voltage Level

Single-ended high speed channel

AVCC - 10

AVCC + 10

Low Voltage Level

Single-ended high speed channel

AVCC - 600

AVCC - 400

Rise/Fall Time (20% to 80%)

135

200

INPUT TERMINATION

Resistance Single-ended

AUXILIARY CHANNELS

On Resistance, R

AUX

100

On Capacitance, C

AUX

DC bias = 2.5 V, ac voltage = 3.5 V, f = 100 kHz

Input/Output Voltage Range

DVEE

AMUXVCC

POWER SUPPLY

AVCC Operating

range 3

3.3

3.6

QUIESCENT CURRENT

AVCC Outputs

disabled

Outputs enabled, no pre-emphasis

Outputs enabled, maximum pre-emphasis

108

120

VTTI

Input termination on

5 40

VTTO

Output termination on, no pre-emphasis

Output termination on, maximum
pre-emphasis

73 80

88 mA

DVCC

AMUXVCC

0.01

0.1

POWER DISSIPATION

Outputs

disabled

115

271

364

Outputs enabled, no pre-emphasis

411

574

664

Outputs enabled, maximum pre-emphasis

754

936

1057

TIMING CHARACTERISTICS

Switching/Update Delay

High speed switching register: HS_CH

200

All other configuration registers

1.5

RESET Pulse Width

AD8190

Rev. 0 | Page 5 of 24

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

AVCC to AVEE

3.7 V

DVCC to DVEE

3.7 V

DVEE to AVEE

±0.3 V

VTTI

AVCC + 0.6 V

VTTO

AVCC + 0.6 V

AMUXVCC 5.5

Internal Power Dissipation

4.62 W

High Speed Input Voltage

AVCC - 1.4 V < V

< AVCC + 0.6 V

High Speed Differential
Input Voltage

2.0 V

Low Speed Input Voltage

DVEE - 0.3 V < V

< AMUXVCC + 0.6 V

C Logic Input Voltage

DVEE - 0.3 V < V

< DVCC + 0.6 V

Storage Temperature
Range

-65°C to +125°C

Operating Temperature
Range

-40°C to +85°C

Junction Temperature

150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

is specified for the worst-case conditions: a device soldered

in a 4-layer JEDEC circuit board for surface-mount packages.

is specified for the exposed pad soldered to the circuit board

with no airflow.

Table 3. Thermal Resistance

Package Type

Unit

56-Lead LFCSP

2.1

°C/W

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the
AD8190 is limited by the associated rise in junction tempera-
ture. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition
temperature of the plastic, approximately 150°C. Temporarily
exceeding this limit may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of 175°C for an extended
period can result in device failure. To ensure proper operation,
it is necessary to observe the maximum power derating as
determined by the coefficients in Table 3.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

AD8190

Rev. 0 | Page 6 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1
INDICATOR

AVCC

IN_A0

IP_A0

AVEE

IN_A1

IP_A1

VTTI

IN_A2

IP_A2

AVCC

IN_A3

IP_A3

AVEE

I2C_ADDR

IP_B1

VTTI

IN_B2

IP_B2

AVEE

IN_B3

IP_B3

AVCC

IN_B1

AVCC

IP_B0

IN_B0

AVEE

I2C_SDA

1
5

1
6

1
7

1
9

2
1

2
0

2
2

2
3

2
4

2
5

2
6

2
7

2
8

I
2
C

1
8

4
5

4
6

4
7

4
8

4
9

5
0

5
1

5
2

5
3

5
4

4
4

4
3

TOP VIEW

(Not to Scale)

AD8190

5
5

5
6

NOTES

1. THE AD8190 LFCSP HAS AN EXPOSED PADDLE (ePAD) ON THE UNDERSIDE

OF THE PACKAGE WHICH AIDS IN HEAT DISSIPATION. THE ePAD MUST BE

ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE IN ORDER TO

MEET THERMAL SPECIFICATIONS.

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Type

Description

1, 10, 33, 42

AVCC

Power

Positive Analog Supply. 3.3 V nominal.

IN_A0

HS I

High Speed Input Complement.

IP_A0

HS I

High Speed Input.

4, 13, 30, 39, ePAD

AVEE

Power

Negative Analog Supply. 0 V nominal.

IN_A1

HS I

High Speed Input Complement.

IP_A1

HS I

High Speed Input.

7, 36

VTTI

Power

Input Termination Supply. Nominally connected to AVCC.

IN_A2

HS I

High Speed Input Complement.

IP_A2

HS I

High Speed Input.

IN_A3

HS I

High Speed Input Complement.

IP_A3

HS I

High Speed Input.

14 I2C_ADDR

Control

C Address LSB.

15, 21

DVCC

Power

Positive Digital Power Supply. 3.3 V nominal.

ON0

HS O

High Speed Output Complement.

OP0

HS O

High Speed Output.

18, 24

VTTO

Power

Output Termination Supply. Nominally connected to AVCC.

ON1

HS O

High Speed Output Complement.

OP1

HS O

High Speed Output.

ON2

HS O

High Speed Output Complement.

OP2

HS O

High Speed Output.

ON3

HS O

High Speed Output Complement.

OP3

HS O

High Speed Output.

RESET

Control

Configuration Registers Reset. This pin is normally pulled up to DVCC.

28 I2C_SCL

Control

C Clock.

29 I2C_SDA

Control

C Data.

IN_B0

HS I

High Speed Input Complement.

IP_B0

HS I

High Speed Input.

AD8190

Rev. 0 | Page 10 of 24

= 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input swing =

1000 mV, TMDS outputs terminated with external 50 resistors to 3.3 V, pattern = PRBS 2

- 1, data rate = 1.65 Gbps, unless otherwise noted.

0.5

0.6

HDMI CABLE LENGTH (m)

I
NI

I
C J

I
T

R (

I
)

0.4

0.3

0.2

0.1

2m CABLE = 30AWG

5m TO 10m CABLES = 28AWG

15m TO 30m CABLES = 24AWG

720p,

EQ = 12dB

1080p,

EQ = 12dB

480p,

EQ = 12dB

1.65Gbps,

EQ = 12dB

Figure 14. Jitter vs. Input Cable Length (See Figure 4 for Test Setup)

612

DATA RATE (Gbps)

(

s
)

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

DJ (p-p)

RJ (rms)

1.65Gbps

1080p

1080i/720p

480p

480i

Figure 15. Jitter vs. Data Rate

3.0

3.6

612

SUPPLY VOLTAGE (V)

(

s
)

3.1

3.2

3.3

3.4

3.5

DJ (p-p)

RJ (rms)

Figure 16. Jitter vs. Supply Voltage

0.6

612

HDMI CABLE LENGTH (m)

TIC

I
TT

(

0.5

0.4

0.3

0.2

0.1

2m CABLE = 30AWG

5m TO 10m CABLES = 28AWG

15m TO 20m CABLES = 24AWG

720p, PE OFF

1080p, MAX PE

720p, MAX PE

480p, PE OFF

480p, MAX PE

1080p, PE OFF

Figure 17. Jitter vs. Output Cable Length (See Figure 9 for Test Setup)

1200

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

612

DATA RATE (Gbps)

E H

I
G

(mV)

1000

800

600

400

200

1.8

Figure 18. Eye Height vs. Data Rate

800

2.5

3.6

612

SUPPLY VOLTAGE (V)

EYE

(
m

)

700

600

500

400

300

200

100

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

Figure 19. Eye Height vs. Supply Voltage

AD8190

Rev. 0 | Page 11 of 24

612

DIFFERENTIAL INPUT SWING (V)

(

s
)

= 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input swing =

1000 mV, TMDS outputs terminated with external 50 resistors to 3.3 V, pattern = PRBS 2

- 1, data rate = 1.65 Gbps, unless otherwise noted.

2.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

RJ (rms)

DJ (p-p)

Figure 20. Jitter vs. Differential Input Swing

60

100

612

TEMPERATURE (°C)

(

s
)

40

20

RJ (rms)

DJ (p-p)

Figure 21. Jitter vs. Temperature

160

40

100

612

TEMPERATURE (°C)

/
F

I
M

20% T

% (

140

120

100

20

RISE TIME

FALL TIME

Figure 22. Rise and Fall Time vs. Temperature

2.5

2.7

2.9

3.1

3.3

3.5

3.7

INPUT COMMON-MODE VOLTAGE (V)

T
E

(
p

DJ (p-p)

RJ (rms)

Figure 23. Jitter vs. Input Common-Mode Voltage

120

40

100

612

TEMPERATURE (°C)

I
FF

I
NAT

I
O

N RE

I
S

NCE

(

)

115

110

105

100

20

Figure 24. Differential Input Termination Resistance vs. Temperature

AD8190

Rev. 0 | Page 12 of 24

THEORY OF OPERATION

INTRODUCTION

The primary function of the AD8190 is to switch one of two
(DVI or HDMI) single-link sources to one output. Each
HDMI/DVI link consists of four differential, high speed
channels and four auxiliary single-ended, low speed control
signals. The high speed channels include a data-word clock and
three transition minimized differential signaling (TMDS) data
channels running at 10× the data-word clock frequency for data
rates up to 1.65 Gbps. The four low speed control signals are
5 V tolerant bidirectional lines that can carry configuration
signals, HDCP encryption, and other information, depending
upon the specific application.

All four high speed TMDS channels are identical; that is, the
pixel clock can be run on any of the four TMDS channels.

Transmit and receive channel compensation is provided for the
high speed channels where the user can (manually) select
among a number of fixed settings.

The AD8190 has I

C serial programming with two user pro-

grammable I

C slave addresses. The I

C slave address of the

AD8190 is 0b100100X. The least significant bit, represented by
X in the address, is set by tying the I2C_ADDR pin to either
3.3 V (for the value, X = 1) or to 0 V (for X = 0).

INPUT CHANNELS

Each high speed input differential pair terminates to the
3.3 V VTTI power supply through a pair of single-ended 50
on-chip resistors, as shown in Figure 25. The input terminations
can be optionally disconnected for approximately 100 ms following
a source switch. The user can program which of the eight high
speed input channels employs this feature by selectively setting the
associated RX_PT bits in the input termination pulse register.
Additionally, all the input terminations can be disconnected by
programming the RX_TO bit in the receiver settings register.

The input equalizer can be manually configured to provide two
different levels of high frequency boost: 6 dB or 12 dB. The user
can individually program the equalization level of the eight high
speed input channels by selectively setting the associated RX_EQ
bits in the receive equalizer register. No specific cable length is
suggested for a particular equalization setting because cable
performance varies widely between manufacturers; however, in
general, the equalization of the AD8190 can be set to 12 dB
without degrading the signal integrity, even for short input
cables. At the 12 dB setting, the AD8190 can equalize up to
20 meters of 24 AWG cable at 1080p, over reference cables that
exhibit an insertion loss of -15 dB.

CABLE

IP_xx

IN_xx

AVEE

VTTI

Figure 25. High Speed Input Simplified Schematic

OUTPUT CHANNELS

Each high speed output differential pair is terminated to the
3.3 V VTTO power supply through two single-ended 50
on-chip resistors (see Figure 26). This output termination is
user-selectable; all the output terminations can be turned on
or off by programming the TX_PTO bit of the transmitter
settings register.

VTTO

OPx

ONx

AVEE

DISABLE

OUT

-
00

Figure 26. High Speed Output Simplified Schematic

The AD8190 output has a disable feature that places the outputs
in a tristate mode. This mode is enabled by setting the HS_EN
bit of the high speed device modes register. Larger wire-OR'ed
arrays can be constructed using the AD8190 in this mode.

The AD8190 requires output termination resistors when the
high speed outputs are enabled. Termination can be internal
and/or external. The internal terminations of the AD8190 are
enabled by setting the TX_PTO bit of the transmitter settings
register (the default upon reset). External terminations can be
provided either by on-board resistors or by the input termination
resistors of an HDMI/DVI receiver. If both internal and external
terminations are provided, set the output current level to 20 mA
by programming the TX_OCL bit of the transmitter settings
register (the default upon reset). If only external terminations
are provided, set the output current level to 10 mA. The high
speed outputs must be disabled if there are no output termination
resistors present in the system.

The output pre-emphasis can be manually configured to provide
one of four different levels of high frequency boost. The specific
boost level is selected by programming the TX_PE bits of the
transmitter settings register. No specific cable length is suggested
for a particular pre-emphasis setting because cable performance
varies widely between manufacturers.

AD8190

Rev. 0 | Page 13 of 24

SWITCHING MODE

The AD8190 behaves like a 2:1 HDMI/DVI switch by imple-
menting a quad switching mode. In this mode, the user selects
the high speed source (A or B) that is routed to the output by
programming the HS_CH bit of the high speeds modes register
as shown in Table 7. The low speed auxiliary source (AUX_A or
AUX_B) that is routed to the common output is separately set
by programming the AUX_CH bit of the auxiliary device
register as shown in Table 9.

AUXILIARY LINES SWITCHING

The auxiliary (low speed) lines have no amplification. They are
routed using a passive switch that is bandwidth compatible with
standard speed I

C. The schematic equivalent for this passive

connection is shown in Figure 27.

AUX_COM0

AUX_A0

½C

AUX

½C

AUX

122

-
006

Figure 27. Auxiliary Channel Simplified Schematic

Showing AUX_A0 to AUX_COM0 Routing

When turning off the AD8190, care needs to be taken with
the AMUXVCC supply to ensure that the auxiliary multiplexer
pins are in a high impedance state. A scenario that illustrates
this requirement is one where the auxiliary multiplexer is used
to switch the display data channel (DDC) bus. In some applica-
tions, additional devices can be connected to the DDC bus
(such as an EEPROM with EDID information) upstream of the
AD8190. Extended display identification data (EDID) is a VESA
standard-defined data format for conveying display configuration

information to sources to optimize display use. EDID devices
may need to be available via the DDC bus, regardless of the
state of the AD8190 and any downstream circuit. For this
configuration, the auxiliary inputs of the powered down
AD8190 need to be in a high impedance state to avoid pulling
down on the DDC lines and preventing these other devices
from using the bus.

When the AD8190 is powered from a simple resistor network,
as shown in Figure 28, it uses the 5 V supply that is required
from any HDMI/DVI source to guarantee high impedance of
the auxiliary multiplexer pins. The AMUXVCC supply does not
draw any static current; therefore, it is recommended that the
resistor network tap the 5 V supplies as close to the connectors
as possible to avoid any additional voltage drop.

This precaution does not need to be taken if the DDC
peripheral circuitry is connected to the bus downstream of
the AD8190.

PERIPHERAL

CIRCUITRY

PERIPHERAL

CIRCUITRY

10k

10M

AD8190

AMUXVCC

+5V INTERNAL

(IF ANY)

10k

I < 50mA

PIN 18 HDMI CONNECTOR

PIN 14 DVI CONNECTOR

PIN 18 HDMI CONNECTOR

PIN 14 DVI CONNECTOR

+5V

SOURCE A

SOURCE B

Figure 28. Suggested AMUXVCC Power Scheme

AD8190

Rev. 0 | Page 14 of 24

SERIAL CONTROL INTERFACE

RESET

On initial power-up, or at any point in operation, the AD8190
register set can be restored to the default values by pulling the
RESET pin to low according to the specification in Table 1.
During normal operation, however, the RESET pin must be
pulled up to 3.3 V. Pulling the RESET pin to low sets the
HS_CH register to 0 (Input A) and incurs the associated
switching delay before the input can be switched to Input B,
regardless of the previous state of the AD8190.

WRITE PROCEDURE

To write data to the AD8190 register set, an I

C master (such as

a microcontroller) needs to send the appropriate control signals
to the AD8190 slave device. The signals are controlled by the
I

C master unless otherwise specified. For a diagram of the

procedure, see Figure 29. The steps for a write procedure are as
follows:

Send a start condition (while holding the I2C_SCL line
high, pull the I2C_SDA line low).

Send the AD8190 part address (seven bits). The upper six
bits of the AD8190 part address are the static value
[100100] and the LSB is set by Input Pin I2C_ADDR. This
transfer should be MSB first.

Send the write indicator bit (0).

Wait for the AD8190 to acknowledge the request.

Send the register address (eight bits) to which data is to be
written. This transfer should be MSB first.

Wait for the AD8190 to acknowledge the request.

Send the data (eight bits) to be written to the register
whose address was set in Step 5. This transfer should be
MSB first.

Wait for the AD8190 to acknowledge the request.

Do one of the following:

Send a stop condition (while holding the I2C_SCL
line high, pull the I2C_SDA line high) and release
control of the bus to end the transaction (shown in
Figure 29).

Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 2 in this procedure to perform
another write.

Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 2 of the read procedure (in the
Read Procedure section) to perform a read from
another address.

Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 8 of the read procedure (in the
Read Procedure section) to perform a read from the
same address set in Step 5.

R/W

ACK

ADDR

START

FIXED ADDR PART

REGISTER ADDR

DATA

STOP

ACK

I2C_SCL

GENERAL CASE

I2C_SDA

EXAMPLE

I2C_SDA

*THE SWITCHING/UPDATE DELAY BEGINS AT THE FALLING EDGE OF THE

LAST DATA BIT; FOR EXAMPLE, THE FALLING EDGE JUST BEFORE STEP 8.

Figure 29. I

C Write Procedure

AD8190

Rev. 0 | Page 15 of 24

START

FIXED PART ADDR

REGISTER ADDR

FIXED PART ADDR

DATA

STOP

ACK

ADDR ACK

R/W

ADDR ACK

ACK

R/W

9 10 11

I2C_SCL

GENERAL CASE

I2C_SDA

EXAMPLE

I2C_SDA

0
09

Figure 30. I

C Read Procedure

READ PROCEDURE

To read data from the AD8190 register set, an I

C master (such

as a microcontroller) needs to send the appropriate control
signals to the AD8190 slave device. The signals are controlled
by the I

C master unless otherwise specified. For a diagram of

the procedure, see Figure 30. The steps for a read procedure are
as follows:

Send a start condition (while holding the I2C_SCL line
high, pull the I2C_SDA line low).

Send the AD8190 part address (seven bits). The upper six
bits of the AD8190 part address are the static value
[100100] and the LSB is set by Input Pin I2C_ADDR. This
transfer should be MSB first.

Send the write indicator bit (0).

Wait for the AD8190 to acknowledge the request.

Send the register address (eight bits) from which data is to
be read. This transfer should be MSB first.

Wait for the AD8190 to acknowledge the request.

Send a repeated start condition (Sr) by holding the
I2C_SCL line high and pulling the I2C_SDA line low.

Resend the AD8190 part address (seven bits) from Step 2.
The upper six bits of the AD8190 part address compose the
static value [100100]. The LSB is set by Input Pin I2C_ADDR.
This transfer should be MSB first.

Send the read indicator bit (1).

10.

Wait for the AD8190 to acknowledge the request.

11.

The AD8190 serially transfers the data (eight bits) held in
the register indicated by the address set in Step 5. This data
is sent MSB first.

12.

Acknowledge the data from the AD8190.

13.

Do one of the following:

Send a stop condition (while holding the I2C_SCL
line high, pull the SDA line high) and release control
of the bus to end the transaction (shown in Figure 30).

Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 2 of the write procedure (see the
previous Write Procedure section) to perform a write.

Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 2 of this procedure to perform a
read from another address.

Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 8 of this procedure to perform a
read from the same address.

SWITCHING/UPDATE DELAY

There is a delay between when a user writes to the configura-
tion registers of the AD8190 and when that state change takes
physical effect. This update delay begins at the falling edge of
I2C_SCL for the last data bit transferred, as shown in Figure 29.
This update delay is register specific and the times are specified
in Table 1.

During a delay window, new values can be written to the
configuration registers but the AD8190 does not physically
update until the end of that register's delay window. Writing
new values during the delay window does not reset the window;
new values supersede the previously written values. At the end
of the delay window, the AD8190 physically assumes the state
indicated by the last set of values written to the configuration
registers. If the configuration registers are written after the delay
window ends, the AD8190 immediately updates and a new
delay window begins.

AD8190

Rev. 0 | Page 16 of 24

CONFIGURATION REGISTERS

The serial interface configuration registers can be read and written using the I

C serial interface, Pin I2C_SDA, and Pin I2C_SCL.

The LSB of the AD8190 I

C part address is set by tying Pin I2C_ADDR to 3.3 V (I2C_ADDR = 1) or 0 V (I2C_ADDR = 0).

Table 5. Register Map

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Addr.

Default

High speed
switch enable

High speed
source select

High Speed
Device
Modes

HS_EN

HS_CH

0x00 0x40

Auxiliary
switch enable

Auxiliary
switch
source select

Auxiliary
Device
Modes

AUX_EN

AUX_CH

0x01 0x40

High speed
input
termination
select

Receiver
Settings

RX_TO

0x10 0x01

Input termination pulse-on-source-switch select (disconnect termination for a short period of time)

Input
Termination
Pulse

RX_PT[7] RX_PT[6]

RX_PT[5] RX_PT[4] RX_PT[3] RX_PT[2] RX_PT[1]

RX_PT

[0]

0x11 0x00

Input equalization level select

Receive
Equalizer

RX_EQ[7] RX_EQ[6]

RX_EQ[5] RX_EQ[4] RX_EQ[3] RX_EQ[2] RX_EQ[1]

RX_EQ[0]

0x13 0x00

High speed output
pre-emphasis level
select

High speed
output
termination
select

High speed
output
current level
select

Transmitter
Settings

TX_PE[1] TX_PE[0] TX_PTO

TX_OCL

0x20 0x03

HIGH SPEED DEVICE MODES REGISTER

HS_EN: High Speed (TMDS) Switch Enable Bit

Table 6. HS_EN Description

HS_EN Description

High speed channels off, low power/standby mode

High speed channels on

HS_CH: High Speed (TMDS) Source Select Bit

Table 7. HS_CH Mapping

HS_CH O[3:0] Description

A[3:0]

High speed Source A switched to output

B[3:0]

High speed Source B switched to output

AUXILIARY DEVICE MODES REGISTER

AUX_EN: Auxiliary (Low Speed) Switch Enable Bit

Table 8. AUX_EN Description

AUX_EN Description

Auxiliary switch off, no low speed input/output to
low speed common input/output connection

1 Auxiliary

switch

AUX_CH: Auxiliary (Low Speed) Switch Source Select Bit

Table 9. AUX_CH Mapping

AUX_CH AUX_COM[3:0] Description

0 AUX_A[3:0]

Auxiliary Source A switched to
output

1 AUX_B[3:0]

Auxiliary Source B switched to
output

AD8190

Rev. 0 | Page 17 of 24

RECEIVER SETTINGS REGISTER

RX_TO: High Speed (TMDS) Input Termination On/Off
Select Bit

Table 10. RX_TO Description

RX_TO Description

Input termination off

Input termination on (can be pulsed on and off
when source is switched, according to settings in
the input termination pulse register)

INPUT TERMINATION PULSE REGISTER

RX_PT[X]: High Speed (TMDS) Input Termination X
Pulse-On-Source Switch Select Bit

Table 11. RX_PT[X] Description

RX_PT[X] Description

Input termination for TMDS Channel X always
connected when source is switched

Input termination for TMDS Channel X
disconnected for approximately 100 ms when
source is switched

Table 12. RX_PT[X] Mapping

RX_PT[X]

Corresponding Input TMDS Channel

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

RECEIVE EQUALIZER REGISTER

RX_EQ[X]: High Speed (TMDS) Input X Equalization Level
Select Bit

Table 13. RX_EQ[X] Description

RX_EQ[X] Description

Low equalization (6 dB)

High equalization (12 dB)

Table 14. RX_EQ[X] Mapping

RX_EQ[X]

Corresponding Input TMDS Channel

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

TRANSMITTER SETTINGS REGISTER

TX_PE[1:0]: High Speed (TMDS) Output Pre-Emphasis
Level Select Bus (All TMDS Channels)

Table 15. TX_PE[1:0] Description

TX_PE[1:0] Description

No pre-emphasis (0 dB)

Low pre-emphasis (2 dB)

Medium pre-emphasis (4 dB)

High pre-emphasis (6 dB)

X_PTO: High Speed (TMDS) Output Termination On/Off
Select Bit (All Channels)

Table 16. TX_PTO Description

TX_PTO Description

Output termination off

Output termination on

TX_OCL: High Speed (TMDS) Output Current Level Select
Bit (All Channels)

Table 17. TX_OCL Description

TX_OCL Description

Output current set to 10 mA

Output current set to 20 mA

AD8190

Rev. 0 | Page 18 of 24

APPLICATION NOTES

612

Figure 31. Evaluation Board Layout of the TMDS Traces

The AD8190 is an HDMI/DVI switch featuring equalized
TMDS inputs and pre-emphasized TMDS outputs. It is in-
tended for use as a 2:1 switch in systems with long cable runs
on both the input and/or the output, and is fully HDMI 1.2a
receive compliant.

PINOUT

The AD8190 was designed to have an HDMI/DVI receiver
pinout at its input and a transmitter pinout at its output. This
makes the AD8190 ideal for use in AVR-type applications
where a designer routes both the inputs and the outputs directly
to HDMI/DVI connectors as shown in Figure 31. When the
AD8190 is used in receiver-type applications, it is necessary to
change the ordering of the output pins on the PCB to match up
with the on-board receiver, as shown in Figure 32.

One advantage of the AD8190 in an AVR-type application is
that all of the high speed signals can be routed on one side (the
topside) of the board, as shown in Figure 31. In addition to
12 dB of input equalization, the AD8190 provides up to 6 dB of
output pre-emphasis that boosts the output TMDS signals and
allows the AD8190 to precompensate when driving long PCB
traces or output cables. The net effect of the input equalization
and output pre-emphasis of the AD8190 is that the AD8190 can
compensate for the signal degradation of both input and output
cables; it acts to reopen a closed input data eye and transmit a
full-swing HDMI signal to an end receiver. More information
on the specific performance metrics of the AD8190 can be
found in the Typical Performance Characteristics section.

The AD8190 also provides a distinct advantage in receive-type
applications because it is a fully buffered HDMI/DVI switch.

Although inverting the output pin order of the AD8190 on the
PCB requires a designer to place vias in the high speed signal
path, the AD8190 fully buffers and electrically decouples the
outputs from the inputs. Therefore, the effects of the vias placed
on the output signal lines are not seen at the input of the AD8190.
The programmable output terminations also improve signal
quality at the output of the AD8190. The PCB designer, there-
fore, has significantly improved flexibility in the placement and
routing of the output signal path with the AD8190 over other
solutions.

An example of high speed routing from an HDMI Standard
Revision 1.2a receive-compliant reference design is shown in
Figure 32. The light gray TMDS lines are routed on the top layer
of the PCB, the dark gray TMDS lines are routed on the bottom
layer, and the black dots are vias.

AD9880 (Rx)

AD8190

HDMI IN

0
6

122

-
03

Figure 32. Layout of the TMDS Traces for the AD8190 in an HDMI Standard

Revision 1.2a Receive-Compliant Reference Design

AD8190

Rev. 0 | Page 19 of 24

CABLE LENGTHS AND EQUALIZATION

The AD8190 offers two levels of programmable equalization
for the high speed inputs: 6 dB and 12 dB. The equalizer of
the AD8190 is optimized for video data rates of 1.65 Gbps,
and as shown in Figure 14, it can equalize up to 20 meters of
24 AWG HDMI cable at data rates corresponding to the video
format, 1080p.

The length of cable that can be used in a typical HDMI/DVI
application depends on a large number of factors including:

Cable quality: the quality of the cable in terms of conductor
wire gauge and shielding. Thicker conductors have lower
signal degradation per unit length.

Data rate: the data rate being sent over the cable. The signal
degradation of HDMI cables increases with data rate.

Edge rates: the edge rates of the source input. Slower input
edges result in more significant data eye closure at the end
of a cable.

Receiver sensitivity: the sensitivity of the terminating
receiver.

As such, specific cable types and lengths are not recom-
mended for use with a particular equalizer setting. In
nearly all applications, the AD8190 equalization level can
be set to high, or 12 dB, for all input cable configurations
at all data rates, without degrading the signal integrity.

THE AD8190 AS A SINGLE-CHANNEL BUFFER

The AD8190 can be used as a single-channel TMDS buffer
without the need for any external I

C control. In its default

configuration, the AD8190 connects both the high speed and
low speed channels of Input A to their respective outputs, sets
the input equalization level to 6 dB, the output pre-emphasis
level to 0 dB, enables both the output and input terminations,
and provides a fully functioning HDMI link with TMDS
buffering.

The AD8190 enters this default state whenever the RESET pin
is pulled to low in accordance with the specification in Table 1.

PCB LAYOUT GUIDELINES

The AD8190 is used to switch two distinctly different types of
signals, both of which are required for HDMI and DVI video.
These signal groups require different treatment when laying out
a PC board.

The first group of signals carries the audiovisual (AV) data.
HDMI/DVI video signals are differential, unidirectional, and
high speed (up to 1.65 Gbps). The channels that carry the video
data must be controlled impedance, terminated at the receiver,
and capable of operating up to at least 1.65 Gbps. It is especially
important to note that the differential traces that carry the
TMDS signals should be designed with a controlled differential
impedance of 100 . The AD8190 provides single-ended 50

terminations on-chip for both its inputs and outputs, and both
the input and output terminations can be enabled or disabled
through the serial interface. Transmitter termination is not fully
specified by the HDMI standard but its inclusion improves the
overall system signal integrity.

The audiovisual (AV) data carried on these high speed channels
is encoded by a technique called transition minimized differ-
ential signaling (TMDS) and in the case of HDMI, is also encrypted
according to the high bandwidth digital copy protection (HDCP)
standard.

The second group of signals consists of low speed auxiliary
control signals used for communication between a source and a
sink. Depending upon the application, these signals can include
the DDC bus (this is an I

C bus used to send EDID information

and HDCP encryption keys between the source and the sink),
the consumer electronics control (CEC) line, and the hot plug
detect (HPD) line. These auxiliary signals are bidirectional, low
speed, and transferred over a single-ended transmission line
that does not need to have controlled impedance. The primary
concern with laying out the auxiliary lines is ensuring that they
conform to the I

C bus standard and do not have excessive

capacitive loading.

TMDS Signals

In the HDMI/DVI standard, four differential pairs carry the
TMDS signals. In DVI, three of these pairs are dedicated to
carrying RGB video and sync data. For HDMI, audio data is
also interleaved with the video data; the DVI standard does
not incorporate audio information. The fourth high speed
differential pair is used for the AV data-word clock, and runs
at one-tenth the speed of the TMDS data channels.

The four high speed channels of the AD8190 are identical.
No concession was made to lower the bandwidth of the fourth
channel for the pixel clock, so any channel can be used for any
TMDS signal. The user chooses which signal is routed over
which channel. Additionally, the TMDS channels are symmetrical;
therefore, the p and n of a given differential pair are inter-
changeable, provided the inversion is consistent across all inputs
and outputs of the AD8190. However, the routing between
inputs and outputs through the AD8190 is fixed. For example,
Output Channel 0 always switches between Input A0 and
Input B0, and so forth.

The AD8190 buffers the TMDS signals and the input traces can
be considered electrically independent of the output traces. In
most applications, the quality of the signal on the input TMDS
traces are more sensitive to the PCB layout. Regardless of the
data being carried on a specific TMDS channel, or whether the
TMDS line is at the input or the output of the AD8190, all four
high speed signals should be routed on a PCB in accordance
with the same RF layout guidelines.

AD8190

Rev. 0 | Page 20 of 24

Layout for the TMDS Signals

The TMDS differential pairs can either be microstrip traces,
routed on the outer layer of a board, or stripline traces, routed
on an internal layer of the board. If microstrip traces are used,
there should be a continuous reference plane on the PCB layer
directly below the traces. If stripline traces are used, they must
be sandwiched between two continuous reference planes in the
PCB stack-up. Additionally, the p and n of each differential pair
must have a controlled differential impedance of 100 . The
characteristic impedance of a differential pair is a function of
several variables including the trace width, the distance separating
the two traces, the spacing between the traces and the reference
plane, and the dielectric constant of the PC board binder material.
Interlayer vias introduce impedance discontinuities that can
cause reflections and jitter on the signal path, therefore, it is
preferable to route the TMDS lines exclusively on one layer of the
board, particularly for the input traces. Additionally, to prevent
unwanted signal coupling and interference, route the TMDS
signals away from other signals and noise sources on the PCB.

Both traces of a given differential pair must be equal in length
to minimize intrapair skew. Maintaining the physical symmetry
of a differential pair is integral to ensuring its signal integrity;
excessive intrapair skew can introduce jitter through duty cycle
distortion (DCD). The p and n of a given differential pair should
always be routed together in order to establish the required 100
differential impedance. Enough space should be left between
the differential pairs of a given group so that the n of one pair
does not couple to the p of another pair. For example, one tech-
nique is to make the interpair distance 4 to 10 times wider than
the intrapair spacing.

Any group of four TMDS channels (Input A, Input B, or the
output) should have closely matched trace lengths in order to
minimize interpair skew. Severe interpair skew can cause the
data on the four different channels of a group to arrive out of
alignment with one another. A good practice is to match the
trace lengths for a given group of four channels to within
0.05 inches on FR4 material.

The length of the TMDS traces should be minimized to re-
duce overall signal degradation. Commonly used PC board
material such as FR4 is lossy at high frequencies, so long traces
on the circuit board increase signal attenuation, resulting in
decreased signal swing and increased jitter through intersymbol
interference (ISI).

Controlling the Characteristic Impedance of a TMDS
Differential Pair

The characteristic impedance of a differential pair depends on a
number of variables including the trace width, the distance
between the two traces, the height of the dielectric material
between the trace and the reference plane below it, and the
dielectric constant of the PCB binder material. To a lesser
extent, the characteristic impedance also depends upon the
trace thickness and the presence of solder mask.

There are many combinations that can produce the correct
characteristic impedance. It is generally required to work with
the PC board fabricator to obtain a set of parameters to produce
the desired results.

One consideration is how to guarantee a differential pair with a
differential impedance of 100 over the entire length of the
trace. One technique to accomplish this is to change the width
of the traces in a differential pair based on how closely one trace
is coupled to the other. When the two traces of a differential
pair are close and strongly coupled, they should have a width
that produces a 100 differential impedance. When the traces
split apart to go into a connector, for example, and are no longer
so strongly coupled, the width of the traces should be increased
to yield a differential impedance of 100 in the new configuration.

TMDS Terminations

The AD8190 provides internal 50 single-ended terminations
for all of its high speed inputs and outputs. It is not necessary to
include external termination resistors for the TMDS differential
pairs on the PCB.

The output termination resistors of the AD8190 back-terminate
the output TMDS transmission lines. These back-terminations
act to absorb reflections from impedance discontinuities on the
output traces, improving the signal integrity of the output traces
and adding flexibility to how the output traces can be routed.
For example, interlayer vias can be used to route the AD8190
TMDS outputs on multiple layers of the PCB without severely
degrading the quality of the output signal.

Auxiliary Control Signals

There are four single-ended control signals associated with each
source or sink in an HDMI/DVI application. These are hot plug
detect (HPD), consumer electronics control (CEC), and two
display data channel (DDC) lines. The two signals on the DDC
bus are SDA and SCL (serial data and serial clock, respectively).
These four signals can be switched through the auxiliary bus of
the AD8190 and do not need to be routed with the same strict
considerations as the high speed TMDS signals.

In general, it is sufficient to route each auxiliary signal as a
single-ended trace. These signals are not sensitive to impedance
discontinuities, do not require a reference plane, and can be
routed on multiple layers of the PCB. However, it is best to
follow strict layout practices whenever possible to prevent the
PCB design from affecting the overall application. The specific
routing of the HPD, CEC, and DDC lines depends upon the
application in which the AD8190 is being used.

For example, the maximum speed of signals present on the
auxiliary lines are 100 kHz I

C data on the DDC lines, therefore,

any layout that enables 100 kHz I

C to be passed over the DDC

bus should suffice. The HDMI 1.2a specification, however,
places a strict 50 pF limit on the amount of capacitance that can
be measured on either SDA or SCL at the HDMI input connector.

AD8190

Rev. 0 | Page 21 of 24

This 50 pF limit includes the HDMI connector, the PCB, and
whatever capacitance is seen at the input of the AD8190, or an
equivalent receiver. There is a similar limit of 100 pF of input
capacitance for the CEC line.

The parasitic capacitance of traces on a PCB increases with
trace length. To help ensure that a design satisfies the HDMI
specification, the length of the CEC and DDC lines on the PCB
should be made as short as possible. Additionally, if there is a
reference plane in the layer adjacent to the auxiliary traces in
the PCB stackup, relieving or clearing out this reference plane
immediately under the auxiliary traces significantly decreases
the amount of parasitic trace capacitance. An example of the
board stackup is shown in Figure 33.

PCB DIELECTRIC

LAYER 1: MICROSTRIP

SILKSCREEN

PCB DIELECTRIC

LAYER 2: REFERENCE PLANE

LAYER 3: REFERENCE PLANE

LAYER 4: MICROSTRIP

REFERENCE LAYER

RELIEVED UNDERNEATH

MICROSTRIP

Figure 33. Example Board Stackup

HPD is a dc signal presented by a sink to a source to indicate
that the source EDID is available for reading. The placement of
this signal is not critical, but it should be routed as directly as
possible.

When the AD8190 is powered up, one set of the auxiliary inputs
is passively routed to the outputs. In this state, the AD8190
looks like a 100 resistor between the selected auxiliary inputs
and the corresponding outputs as illustrated in Figure 27. The
AD8190 does not buffer the auxiliary signals, therefore, the
input traces, output traces, and the connection through the
AD8190 all must be considered when designing a PCB to meet
HDMI/DVI specifications. The unselected auxiliary inputs of the
AD8190 are placed into a high impedance mode when the device
is powered up. To ensure that all of the auxiliary inputs of the
AD8190 are in a high impedance mode when the device is
powered off, it is necessary to power the AMUXVCC supply as
illustrated in Figure 28.

In contrast to the auxiliary signals, the AD8190 buffers the
TMDS signals, allowing a PCB designer to layout the TMDS
inputs independently of the outputs.

Power Supplies

The AD8190 has five separate power supplies referenced to
two separate grounds. The supply/ground pairs are:
AVCC/AVEE, VTTI/AVEE, VTTO/AVEE, DVCC/DVEE,
and AMUXVCC/DVEE.

The AVCC/AVEE (3.3 V) and DVCC/DVEE (3.3 V) supplies
power the core of the AD8190. The VTTI/AVEE supply (3.3 V)
powers the input termination (see Figure 25). Similarly, the
VTTO/AVEE supply (3.3 V) powers the output termination
(see Figure 26). The AMUXVCC/DVEE supply (3.3 V to 5 V)
powers the auxiliary multiplexer core and determines the
maximum allowed voltage on the auxiliary lines. For example,
if the DDC bus is using 5 V I

C, then AMUXVCC should be

connected to +5 V relative to DVEE.

In a typical application, all pins labeled AVEE or DVEE should
be connected directly to ground. All pins labeled AVCC,
DVCC, VTTI, or VTTO should be connected to 3.3 V, and
Pin AMUXVCC tied to 5 V. The supplies can also be powered
individually, but care must be taken to ensure that each stage of
the AD8190 is powered correctly.

AD8190

Rev. 0 | Page 22 of 24

Power Supply Bypassing

The AD8190 requires minimal supply bypassing. When
powering the supplies individually, place a 0.01 F capacitor
between each 3.3 V supply pin (AVCC, DVCC, VTTI, and
VTTO) and ground to filter out supply noise. Generally, bypass
capacitors should be placed near the power pins and should
connect directly to the relevant supplies (without long inter-
vening traces). For example, to improve the parasitic inductance
of the power supply decoupling capacitors, minimize the trace
length between capacitor landing pads and the vias as shown in
Figure 34.

EXTRA ADDED INDUCTANCE

06122-

033

RECOMMENDED

NOT RECOMMENDED

Figure 34. Recommended Pad Outline for Bypass Capacitors

In applications where the AD8190 is powered by a single 3.3 V
supply, it is recommended to use two reference supply planes
and bypass the 3.3 V reference plane to the ground reference
plane with one 220 pF, one 1000 pF, two 0.01 F, and one 4.7 F
capacitors. The capacitors should via down directly to the

supply planes and be placed within a few centimeters of the
AD8190. The AMUXVCC supply does not require additional
bypassing. This scheme is illustrated in Figure 35.

DECOUPLING

CAPACITORS

AUXILIARY LINES

TMDS TRACES

AD8190

Figure 35. Example Placement of Power Supply Decoupling Capacitors

Around the AD8190

AD8190

Rev. 0 | Page 23 of 24

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2

-
A

PIN 1

INDICATOR

TOP

VIEW

7.75

BSC SQ

8.00

BSC SQ

4.95
4.80 SQ
4.65

0.50
0.40
0.30

0.30
0.23
0.18

0.50 BSC

0.20 REF

12° MAX

0.80 MAX
0.65 TYP

1.00
0.85
0.80

6.50
REF

SEATING

PLANE

0.60 MAX

PIN 1

INDICATOR

COPLANARITY

0.08

0.05 MAX
0.02 NOM

0.30 MIN

EXPOSED

PAD

(BOTTOM VIEW)

NOTE:
THE AD8190 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF
THE DEVICE OVER THE FULL DVI/HDMI TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO AVEE. IT IS RECOMMENDED THAT NO PCB SIGNAL
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A AVEE PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE
DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.

Figure 36. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

8 mm × 8 mm Body, Very Thin Quad

(CP-56-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature
Range Package

Description

Package
Option

Ordering
Quantity

AD8190ACPZ

-40°C to +85°C

56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

CP-56-3

AD8190ACPZ-R7

-40°C to +85°C

56-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Reel

CP-56-3

750

AD8190-EVAL

Evaluation

Kit

Z = Pb-free part.

Part Number AD8190

Document Outline