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FUNCTIONAL BLOCK DIAGRAM

VCO

DATA

INPUT

AD800/AD802

RETIMED
DATA
OUTPUT

FRAC
OUTPUT

LOOP

FILTER

DET

COMPENSATING

ZERO

RECOVERED
CLOCK
OUTPUT

RETIMING

DEVICE

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

Clock Recovery and Data Retiming

Phase-Locked Loop

AD800/AD802*

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700

Fax: 617/326-8703

PRODUCT DESCRIPTION

The AD800 and AD802 employ a second order phase-locked
loop architecture to perform clock recovery and data retiming
on Non-Return to Zero, NRZ, data. This architecture is
capable of supporting data rates between 20 Mbps and 160
Mbps. The products described here have been defined to work
with standard telecommunications bit rates. 45 Mbps DS-3 and
52 Mbps STS-1 are supported by the AD800-45 and
AD800-52 respectively. 155 Mbps STS-3 or STM-1 are
supported by the AD802-155.

Unlike other PLL-based clock recovery circuits, these devices
do not require a preamble or an external VCXO to lock onto
input data. The circuit acquires frequency and phase lock using
two control loops. The frequency acquisition control loop
initially acquires the clock frequency of the input data. The
phase-lock loop then acquires the phase of the input data, and
ensures that the phase of the output signals track changes in the
phase of the input data. The loop damping of the circuit is
dependent on the value of a user selected capacitor; this defines
jitter peaking performance and impacts acquisition time. The
devices exhibit 0.08 dB jitter peaking, and acquire lock on
random or scrambled data within 4

bit periods when

using a damping factor of 5.

FEATURES
Standard Products

44.736 Mbps--DS-3
51.84 Mbps--STS-1
155.52 Mbps--STS-3 or STM-1

Accepts NRZ Data, No Preamble Required
Recovered Clock and Retimed Data Outputs
Phase-Locked Loop Type Clock Recovery--No Crystal

Required

Random Jitter: 20 Peak-to-Peak
Pattern Jitter: Virtually Eliminated
10KH ECL Compatible
Single Supply Operation: 5.2 V or +5 V
Wide Operating Temperature Range: 40 C to +85 C

During the process of acquisition the frequency detector
provides a Frequency Acquisition (FRAC) signal which
indicates that the device has not yet locked onto the input data.
This signal is a series of pulses which occur at the points of cycle
slip between the input data and the synthesized clock signal.
Once the circuit has acquired frequency lock no pulses occur at
the FRAC output.

The inclusion of a precisely trimmed VCO in the device
eliminates the need for external components for setting center
frequency, and the need for trimming of those components. The
VCO provides a clock output within

20% of the device center

frequency in the absence of input data.

The AD800 and AD802 exhibit virtually no pattern jitter, due
to the performance of the patented phase detector. Total loop
jitter is 20

peak-to-peak. Jitter bandwidth is dictated by mask

programmable fractional loop bandwidth. The AD800, used for
data rates < 90 Mbps, has been designed with a nominal loop
bandwidth of 0.1% of the center frequency. The AD802, used
for data rates in excess of 90 Mbps, has a loop bandwidth of
0.08% of center frequency.

All of the devices operate with a single +5 V or 5.2 V supply.

*Protected by U.S. Patent No. 5,027,085.

REV. B

AD800/AD802SPECIFICATIONS

= V

MIN

to V

MAX

, V

= GND, T

= T

MIN

to T

MAX

, Loop Damping

Factor = 5, unless otherwise noted)

AD800-45BQ

AD800-52BR

AD802-155KR/BR

Parameter

Condition

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Units

NOMINAL CENTER FREQUENCY

44.736

51.84

155.52

MHz

OPERATING TEMPERATURE

K Grade

RANGE (T

MIN

to T

MAX

)

B Grade

TRACKING RANGE

45.5

155

156

Mbps

CAPTURE RANGE

45.5

155

156

Mbps

STATIC PHASE ERROR

= 1, T

= +25

= 5.2 V

Degrees

= 1

11.5

Degrees

RECOVERED CLOCK SKEW

RCS

(Figure 1)

0.2

0.6

0.2

0.6

0.2

0.8

SETUP TIME

(Figure 1)

2.06

2.37

TRANSITIONLESS DATA RUN

240

Bit Periods

OUTPUT JITTER

= 1

3.5

Degrees rms

1 PRN Sequence

2.5

4.7

2.5

4.7

5.4

9.7

Degrees rms

1 PRN Sequence

2.5

4.7

2.5

4.7

5.4

9.7

Degrees rms

JITTER TOLERANCE

f = 10 Hz

2,500

3,000

Unit Intervals

f = 2.3 kHz

6.5

Unit Intervals

f = 30 kHz

0.47

Unit Intervals

f = 1 MHz

0.47

Unit Intervals

f = 30 Hz

830

Unit Intervals

f = 300 Hz

Unit Intervals

f = 2 kHz

7.4

Unit Intervals

f = 20 kHz

0.47

Unit Intervals

f = 6.5 kHz

2.0

7.6

Unit Intervals

f = 65 kHz

0.26

0.9

Unit Intervals

JITTER TRANSFER

Damping Factor

Capacitor, C

= 1, Nominal

8.2

6.8

2.2

= 5, Nominal

0.22

0.15

0.047

= 10, Nominal

0.82

0.68

0.22

Peaking

= 1, Nominal

= +25

C, V

= 5.2 V

= 5, Nominal

= +25

C, V

= 5.2 V

0.08

= 10, Nominal

= +25

C, V

= 5.2 V

0.02

Bandwidth

130

kHz

ACQUISITION TIME

= 1/2

= 1

1.5

Bit Periods

= +25

= 5

Bit Periods

= 5.2 V

= 10

1.4

Bit Periods

POWER SUPPLY

Voltage (V

MIN

to V

MAX

)

= +25

4.5

5.2

5.5

4.5

5.2

5.5

4.5

5.2

5.5

Volts

Current

= +25

C, V

= 5.2 V

125

170

125

170

140

180

205

INPUT VOLTAGE LEVELS

= +25

Input Logic High, V

1.084

0.72

1.084

0.72

1.084

0.72

Volts

Input Logic Low, V

1.95

1.594

1.95

1.594

1.95

1.594

Volts

OUTPUT VOLTAGE LEVELS

= +25

Output Logic High, V

1.084

0.72

1.084

0.72

1.084

0.72

Volts

Output Logic Low, V

1.95

1.60

1.95

1.60

1.95

1.60

Volts

INPUT CURRENT LEVELS

= +25

Input Logic High, I

125

Input Logic Low, I

OUTPUT SLEW TIMES

= +25

Rise Time (t

)

20%80%

0.75

1.5

0.75

1.5

0.75

1.5

Fall Time (t

)

80%20%

0.75

1.5

0.75

1.5

0.75

1.5

SYMMETRY

= 1/2, T

= +25

Recovered Clock Output

= 5.2 V

NOTES

Refer to Glossary for parameter definition.

Specifications subject to change without notice.

AD800/AD802

REV. B

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Input Voltage (Pin 16 or Pin 17 to V

) . . . . V

to +300 mV

Maximum Junction Temperature

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150

Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . +175

Storage Temperature Range . . . . . . . . . . . . 65

C to +150

Lead Temperature Range (Soldering 60 sec) . . . . . . . +300

ESD Rating

AD800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V
AD802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 V

*Stresses above those listed under "Absolute Maximum Ratings" may cause

permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to an absolute
maximum rating condition for an extended period may adversely affect device
reliability.

RECOVERED CLOCK

SKEW,

RCS

DATAOUT 50%

(PIN 2)

CLKOUT 50%

(PIN 5)

SETUP TIME

Figure 1. Recovered Clock Skew and Setup
(See Previous Page)

PIN DESCRIPTIONS

Number

Mnemonic

Description

DATAOUT

Differential Retimed Data Output

DATAOUT

Differential Retimed Data Output

CC2

Digital Ground

CLKOUT

Differential Recovered Clock Output

CLKOUT

Differential Recovered Clock Output

Digital V

CC1

Digital Ground

Analog V

ASUBST

Analog Substrate

Loop Damping Capacitor Input

Analog Ground

CC1

Digital Ground

Digital V

DATAIN

Differential Data Input

DATAIN

Differential Data Input

SUBST

Digital Substrate

FRAC

Differential Frequency Acquisition
Indicator Output

FRAC

Differential Frequency Acquisition
Indicator Output

THERMAL CHARACTERISTICS

SOIC Package

C/W

Cerdip Package

C/W

Use of a heatsink may be required depending on operating
environment.

GLOSSARY
Maximum and Minimum Specifications

Maximum and minimum specifications result from statistical
analyses of measurements on multiple devices and multiple test
systems. Typical specifications indicate mean measurements.
Maximum and minimum specifications are calculated by adding
or subtracting an appropriate guardband from the typical
specification. Device-to-device performance variation and test
system-to-test system variation contribute to each guardband.

Nominal Center Frequency

This is the frequency that the VCO will operate at with no input
signal present and the loop damping capacitor, C

, shorted.

Tracking Range

This is the range of input data rates over which the PLL will
remain in lock.

Capture Range

This is the range of input data rates over which the PLL can
acquire lock.

Static Phase Error

This is the steady-state phase difference, in degrees, between the
recovered clock sampling edge and the optimum sampling
instant, which is assumed to be halfway between the rising and
falling edges of a data bit. Gate delays between the signals that
define static phase error, and IC input and output signals
prohibit direct measurement of static phase error.

Data Transition Density,

This is a measure of the number of data transitions, from "0" to
"1" and from "1" to "0," over many clock periods.

is the ratio

1) of data transitions to clock periods.

Jitter

This is the dynamic displacement of digital signal edges from
their long term average positions, measured in degrees rms, or
Unit Intervals (UI). Jitter on the input data can cause dynamic
phase errors on the recovered clock sampling edge. Jitter on the
recovered clock causes jitter on the retimed data.

Output Jitter

This is the jitter on the retimed data, in degrees rms, due to a
specific pattern or some psuedo-random input data sequence
(PRN Sequence).

Jitter Tolerance

Jitter tolerance is a measure of the PLL's ability to track a jittery
input data signal. Jitter on the input data is best thought of as
phase modulation, and is usually specified in unit intervals.

ORDERING GUIDE

Fractional Loop

Device

Center Frequency

Bandwidth

Description

Operating Temperature

Package Option

AD800-45BQ

44.736 MHz

0.1%

20-Pin Cerdip

C to +85

Q-20

AD800-52BR

51.84 MHz

0.1%

20-Pin Plastic SOIC

C to +85

R-20

AD802-155BR

155.52 MHz

0.08%

20-Pin Plastic SOIC

C to +85

R-20

AD802-155KR

155.52 MHz

0.08%

20-Pin Plastic SOIC

C to +70

R-20

AD800/AD802

REV. B

The PLL must provide a clock signal which tracks this phase
modulation in order to accurately retime jittered data. In order
for the VCO output to have a phase modulation which tracks
the input jitter, some modulation signal must be generated at
the output of the phase detector (see Figure 21). The
modulation output from the phase detector can only be
produced by a phase error between the data input and the clock
input. Hence, the PLL can never perfectly track jittered data.
However, the magnitude of the phase error depends on the gain
around the loop. At low frequencies the integrator provides very
high gain, and thus very large jitter can be tracked with small
phase errors between input data and recovered clock. At
frequencies closer to the loop bandwidth, the gain of the
integrator is much smaller, and thus less input jitter can be
tolerated. The PLL data output will have a bit error rate less
than 1 10

when in lock and retiming input data that has the

specified jitter applied to it.

Jitter Transfer

The PLL exhibits a low-pass filter response to jitter applied to
its input data.

Bandwidth

This describes the frequency at which the PLL attenuates
sinusoidal input jitter by 3 dB.

Peaking

This describes the maximum jitter gain of the PLL in dB.

Damping Factor,

describes how the PLL will track an input signal with a phase

step. A greater value of

corresponds to less overshoot in the

PLL response to a phase step.

is a standard constant in second

order feedback systems.

Acquisition Time

This is the transient time, measured in bit periods, required for
the PLL to lock on input data from its free-running state.

Symmetry

Symmetry is calculated as (100 on time)/period, where on
time equals the time that the clock signal is greater than the
midpoint between its "0" level and its "1" level.

Bit Error Rate vs. Signal-to-Noise Ratio

The AD800 and AD802 were designed to operate with standard
ECL signal levels at the data input. Although not recom-
mended, smaller input signals are tolerable. Figure 8, 14, and
20 show the bit error rate performance versus input signal-to-
noise ratio for input signal amplitudes of full 900 mV ECL, and
decreased amplitudes of 80 mV and 20 mV. Wideband ampli-
tude noise is summed with the data signals as shown in Figure
2. The full ECL and 80 mV signals give virtually indistinguish-
able results. The 20 mV signals also provide adequate perfor-
mance when in lock, but signal acquisition may be impaired.

POWER
COMBINER

0.47

POWER
COMBINER

1.0

180

POWER

SPLITTER

FILTER

NOISE

SOURCE

100MHz AD802-155
33MHz AD800-52

GND

5.2V

D.U.T.
AD800/AD802

DATA IN

DIFFERENTIAL
SIGNAL
SOURCE

Figure 2. Bit Error Rate vs. Signal-to-Noise Ratio Test:
Block Diagram

USING THE AD800 AND THE AD802 SERIES
Ground Planes

Use of one ground plane for connections to both analog and
digital grounds is recommended. Output signal sensitivity to
power supply noise (PECL configuration, Figure 22) is less
using one ground plane than when using separate analog and
digital ground planes.

Power Supply Connections

Use of a 10

F tantalum capacitor between V

and ground is

recommended.

Use of 0.1

F ceramic capacitors between IC power supply or

substrate pins and ground is recommended. Power supply
decoupling should take place as close to the IC as possible.
Refer to schematics, Figure 22 and Figure 26, for advised
connections.

Sensitivity of IC output signals (PECL configuration,
Figure 22) to high frequency power supply noise (at 2 the
nominal data rate) can be reduced through the connection of
signals AV

and V

CC1

, and the addition of a bypass network.

The type of bypass network to consider depends on the noise
tolerance required. The more complex bypass network schemes
tolerate greater power supply noise levels. Refer to Figures 23
and 24 for bypassing schemes and power supply sensitivity
curves.

Transmission Lines

Use of 50

transmission lines are recommended for DATAIN,

CLKOUT, DATAOUT, and FRAC signals.

Terminations

Termination resistors should be used for DATAIN, CLKOUT,
DATAOUT, and FRAC signals. Metal, thick film, 1% tolerance
resistors are recommended. Termination resistors for the
DATAIN signals should be placed as close as possible to the
DATAIN pins.

Connections from V

to lead resistors for DATAIN, DATA-

OUT, FRAC, and CLKOUT signals should be individual, not
daisy chained. This will avoid crosstalk on these signals.

Loop Damping Capacitor, C

A ceramic capacitor may be used for the loop damping
capacitor.

Input Buffer

Use of an input buffer, such as a 10H116 Line Receiver IC, is
suggested for an application where the DATAIN signals do not
come directly from an ECL gate, or where noise immunity on
the DATAIN signals is an issue.

AD800/AD802

REV. B

100

20

40

TEMPERATURE 

CENTER FREQUENCY MHz

Figure 3. AD800-45 Center Frequency vs. Temperature

100

20

40

TEMPERATURE 

DATA RATE Mbps

Figure 5. AD800-45 Capture and Tracking Range vs.
Temperature

0.30

0.05

0.25

0.20

0.15

0.10

INPUT JITTER UI p-p

DATA RATE Mbps

= 0.68

Figure 7. AD800-45 Acquisition Range vs. Input Jitter

100

20

40

TEMPERATURE 

JITTER Degrees rms

Figure 4. AD800-45 Jitter vs. Temperature

100

0.1

JITTER FREQUENCY Hz

UNIT INTERVALS p-p

AD800-45

DS-3 MASK

Figure 6. AD800-45 Jitter Tolerance

1E-5

1E-11

1E-2

1E-3

1E-4

1E-9

1E-7

1E-1

5E-2

3E-2

2E-2

S/N dB

1
2

erfc

S
N

2 2

ECL

BIT ERROR RATE

Figure 8. AD800-45 Bit Error Rate vs. Input Jitter

Typical Characteristics

AD800/AD802

REV. B

100

20

40

TEMPERATURE 

CENTER FREQUENCY MHz

Figure 9. AD800-52 Center Frequency vs. Temperature

100

20

40

TEMPERATURE 

DATA RATE Mbps

Figure 11. AD800-52 Capture and Tracking Range vs.
Temperature

0.30

0.05

0.25

0.20

0.15

0.10

INPUT JITTER UI p-p

DATA RATE Mbps

= 0.68

Figure 13. AD800-52 Acquisition Range vs. Input Jitter

100

20

40

TEMPERATURE 

JITTER Degrees rms

Figure 10. AD800-52 Jitter vs. Temperature

100

0.1

JITTER FREQUENCY Hz

UNIT INTERVALS p-p

AD800-52

OC-1 MASK

Figure 12. AD800-52 Jitter Tolerance

1E-5

1E-10

1E-2

1E-3

1E-4

1E-8

1E-6

1E-1

5E-2

3E-2

2E-2

S/N dB

1
2

erfc

S
N

2 2

ECL

BIT ERROR RATE

Figure 14. AD800-52 Bit Error Rate vs. Input Jitter

AD800/AD802

REV. B

180

100

120

110

40

140

130

150

160

170

100

20

TEMPERATURE 

CENTER FREQUENCY MHz

Figure 15. AD802-155 Center Frequency vs. Temperature

TEMPERATURE 

200

130

100

160

140

20

150

40

190

170

180

DATA RATE Mbps

Figure 17. AD802-155 Capture Range, Tracking Range vs.
Temperature

INPUT JITTER UI

100

1000

0.1

100

AD802 155

CCITT G.958 STM1 TYPE A MASK

JITTER FREQUENCY Hz

Figure 19. AD802-155 Minimum Acquisition Range vs.
Jitter Frequency, T

MIN

to T

MAX

MIN

to V

MAX

100

20

40

JITTER Degrees rms

TEMPERATURE 

Figure 16. AD802-155 Output Jitter vs. Temperature

100

0.1

UI Pk-Pk

JITTER FREQUENCY Hz

AD802-155

CCITT G.958 STM1 TYPE A MASK

Figure 18. AD802-155 Jitter Tolerance

1E-5

1E-10

1E-2

1E-3

1E-4

1E-8

1E-6

1E-1

5E-2

3E-2

2E-2

BIT ERROR RATE

S/N dB

1
2

erfc

S
N

2 2

80mV

20mV

ECL

20mV

80mV

ECL

1E-12

Figure 20. AD802-155 Bit Error Rate vs. Input Jitter

AD800/AD802

REV. B

THEORY OF OPERATION

The AD800 and AD802 are phase-locked loop circuits for re-
covery of clock from NRZ data. The architecture uses a fre-
quency detector to aid initial frequency acquisition, refer to
Figure 21 for a block diagram. Note the frequency detector is al-
ways in the circuit. When the PLL is locked, the frequency error
is zero and the frequency detector has no further effect. Since
the frequency detector is always in circuit, no control functions
are needed to initiate acquisition or change mode after acquisi-
tion. The frequency detector also supplies a frequency acquisi-
tion (FRAC) output to indicate when the loop is acquiring lock.
During the frequency acquisition process the FRAC output is a
series of pulses of width equal to the period of the VCO. These
pulses occur on the cycle slips between the data frequency and
the VCO frequency. With a maximum density (1010 . . .) data
pattern, every cycle slip will produce a pulse at FRAC. How-
ever, with random data, not every cycle slip produces a pulse.
The density of pulses at FRAC increases with the density of
data transitions. The probability that a cycle slip will produce a
pulse increases as the frequency error approaches zero. After the
frequency error has been reduced to zero, the FRAC output will
have no further pulses. At this point the PLL begins the process
of phase acquisition, with a settling time of roughly 2000 bit pe-
riods. Valid retimed data can be guaranteed by waiting 2000 bit
periods after the last FRAC pulse has occurred.

Jitter caused by variations of density of data transitions (pattern
jitter) is virtually eliminated by use of a new phase detector
(patented). Briefly, the measurement of zero phase error does
not cause the VCO phase to increase to above the average run
rate set by the data frequency. The jitter created by a 2

pseudo-random code is 1/2 degree, and this is small compared
to random jitter.

The jitter bandwidth for the AD802-155 is 0.08% of the center
frequency. This figure is chosen so that sinusoidal input jitter at
130 kHz will be attenuated by 3 dB. The jitter bandwidths of
the AD800-45 and AD800-52 are 0.1% of the respective center
frequencies. The jitter bandwidth of the AD800 or the AD802 is
mask programmable from 0.01% to 1% of the center frequency.
A device with a very low loop bandwidth (0.01% of the center
frequency) could effectively filter (clean up) a jittery timing
reference. Consult the factory if your application requires a
special loop bandwidth.

The damping ratio of the phase-locked loop is user program-
mable with a single external capacitor. At 155 MHz a damping
ratio of 10 is obtained with a 0.22

F capacitor. More generally,

the damping ratio scales as

1.7

DATA

. At 155 MHz a

damping ratio of 1 is obtained with a 2.2 nF capacitor. A lower
damping ratio allows a faster frequency acquisition; generally
the acquisition time scales directly with the capacitor value.
However, at damping ratios approaching one, the acquisition
time no longer scales directly with the capacitor value. The
acquisition time has two components: frequency acquisition and
phase acquisition. The frequency acquisition always scales with
capacitance, but the phase acquisition is set by the loop
bandwidth of the PLL and is independent of the damping ratio.
Thus, the 0.08% fractional loop bandwidth sets a minimum
acquisition time of 15,000 bit periods. Note the acquisition time
for a damping factor of 1 is specified as 15,000 bit periods. This
comprises 13,000 bit periods for frequency acquisition and
2,000 periods for phase acquisition. Compare this to the
400,000 bit periods acquisition time specified for a damping
ratio of 5; this consists entirely of frequency acquisition, and the
2,000 bit periods of phase acquisition is negligible.

While lower damping ratio affords faster acquisition, it also
allows more peaking in the jitter transfer response (jitter
peaking). For example, with a damping ratio of 10 the jitter
peaking is 0.02 dB, but with a damping factor of 1, the peaking
is 2 dB.

DET

TS + 1

RETIMING

DEVICE

VCO

DET

DATA

INPUT

RECOVERED
CLOCK OUTPUT

RETIMED
DATA OUTPUT

FRAC OUTPUT

Figure 21. AD800 and AD802 Block Diagram

AD800/AD802

REV. B

DATAOUT

CC2

CLKOUT

ASUBST

FRAC

SUBST

DATAIN

DATAOUT

CLKOUT

AD800/802

R5 100

R10

R6 100

5.0V

R12

R11

R7 100

R8 100

C10

0.1

100

154

100

R22
80.6

R21

80.6

R19
130

R20
130

FRAC

5.0V

10H116

R24
130

R23

130

R26

80.6

R25

80.6

DATAIN

5.0V

0.1

C7 0.1

C6 0.1

0.1

C16

5.0V

R16 100

5.0V

C13 0.1

100

154

0.1

C20

C21 0.1

5.0V

C9
0.1

R13

R14

R15 100

R17

R18

C17 0.1

C14 0.1

C15 0.1

0.1

C12

C11

C19

0.1

5.0V

BYPASS

NETWORK

OUT

CC1

Figure 22. Evaluation Board Schematic, Positive Supply

Table I. Evaluation Board, Positive Supply: Components List

Reference
Designator

Description

Quantity

R18, R1518

Resistor, 100

, 1%

R914

Resistor, 154

, 1%

R19, 20, 23, 24

Resistor, 130

, 1%

R21, 22, 25, 26

Resistor, 80.6

, 1%

Capacitor, Loop Damping (See Specifications Page)

Capacitor, 10

F, Tantalum

C3C21

Capacitor, 0.1

F, Ceramic Chip

AD800/AD802

10H116, ECL Line Receiver

0.1

C2
10

BYPASS

NETWORK

(A, B, C,

OR D)

TO DEVICE

5.0V

BEADS WITH ONE LOOP

0.1

TO
DEVICE

(A)

0.1

TO
DEVICE

BEAD WITH

ONE LOOP

(B)

(C)

BEAD WITH

TWO LOOPS

0.1

TO
DEVICE

BEAD WITH

TWO LOOPS

(D)

BEAD WITH

TWO LOOPS

BYPASS NETWORK
COMPONENTS:
CAPACITOR ..........CERAMIC CHIP
FERRITE BEAD......1/4 IN. STACKPOLE CARBO 57-1392

3.0

1.0

1.5

0.5

0.1

1.0

2.5

2.0

0.9

0.7

0.6

0.5

0.8

0.4

0.3

0.2

JITTER ns p-p

NOISE V p-p @ 311MHz

(A)

(B)

(C)

(D)

Figure 23. Bypass Network Schemes

Figure 24. AD802-155 Output Jitter vs. Supply Noise

(PECL Configuration)

AD800/AD802

REV. B

BYPASS

NETWORK

(A, B, C,

OR D)

MICRO

METALS

T50-10

TO
DEVICE

PINS

6, 7, 9

10, 15,

PINS
8, 13,
14

AD802-155

PIN
3

0.47

10 TURNS

NOISE IN

SENSE

Figure 25. Power Supply Noise Sensitivity Test Circuit, PECL Configuration

5.2V

DATAOUT

CLKOUT

ASUBST

FRAC

SUBST

DATAIN

CC1

DATAOUT

CLKOUT

FRAC

DATAIN

DATAOUT

CLKOUT

DATAOUT

CLKOUT

10H116

AD800/802

R5 100

R10

R6 100

5.2V

R12

R11

R7 100

R8 100

5.2V

100

154

0.1

154

100

0.1

C6
0.1

C10

0.1

5.2V

R14
80.6

R13

80.6

0.1

5.2V

0.1

R21
274

R22
274

C8 0.1

C9 0.1

R15

130

R16

130

FRAC

5.2V

C11

0.1

R20
130

R19

130

R18
80.6

R17
80.6

DATAIN

5.2V

--5.2V

C12

CC2

CC1

FRAC

Figure 26. Evaluation Board Schematic, Negative Supply

Table II. Evaluation Board, Negative Supply: Components List

Reference
Designator

Description

Quantity

R18

Resistor, 100

, 1%

R912

Resistor, 154

, 1%

R13, 14, 17, 18

Resistor, 80.6

, 1%

R15, 16, 19, 20

Resistor, 130

, 1%

R21, 22

Resistor, 274

, 1%

Capacitor, Loop Damping (See Specifications Page)

Capacitor, 10

F, Tantalum

C3C12

Capacitor, 0.1

F, Ceramic Chip

AD800/AD802

10H116, ECL Line Receiver

Part Number AD800