REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

MOS

Quad 14-Bit DAC

AD7834/AD7835

Š Analog Devices, Inc., 1995

One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700

Fax: 617/326-8703

FEATURES
Four 14-Bit DACs in One Package

AD7834--Serial Loading
AD7835--Parallel 8-/14-Bit Loading

Voltage Outputs
Power-On Reset Function
Max/Min Output Voltage Range of +/8.192 V
Maximum Output Voltage Span of 14 V
Common Voltage Reference Inputs
User Assigned Device Addressing
Clear Function to User-Defined Voltage
Surface Mount Packages

AD7834--28-Pin SO, DIP and Cerdip
AD7835--44-Pin PQFP and PLCC

APPLICATIONS
Process Control
Automatic Test Equipment
General Purpose Instrumentation

GENERAL DESCRIPTION

The AD7834 and AD7835 contain four 14-bit DACs on one
monolithic chip. The AD7834 and AD7835 have output volt-
ages in the range of

8.192 V with a maximum span of 14 V.

The AD7834 is a serial input device. Data is loaded in 16-bit
format from the external serial bus, MSB first after two leading
0s, into one of the input latches via DIN, SCLK and FSYNC.
The AD7834 has five dedicated package address pins, PA0
PA4, that can be wired to AGND or V

to permit up to 32

AD7834s to be individually addressed in a multipackage
application.

The AD7835 can accept either 14-bit parallel loading or
double-byte loading, where right-justified data is loaded in one
8-bit and one 6-bit byte. Data is loaded from the external bus
into one of the input latches under the control of the WR, CS,
BYSHF

and DAC channel address pins, A0A2.

With either device, the LDAC signal can be used to update
either all four DAC outputs simultaneously or individually,
on reception of new data. In addition, for either device, the
asynchronous CLR input can be used to set all signal outputs,
V

OUT

4, to the user-defined voltage level on the Device

Sense Ground pin, DSG. On power-on, before the power sup-
plies have stabilized, internal circuitry holds the DAC output
voltage levels to within

2 V of the DSG potential. As the sup-

plies stabilize, the DAC output levels move to the exact DSG
potential (assuming CLR is exercised).

The AD7834 is available in 28-pin 0.3" SO and 0.6" DIP pack-
ages, and the AD7835 is available in a 44-pin PQFP package
and a 44-pin PLCC package.

AD7835 FUNCTIONAL BLOCK DIAGRAM

DAC 1

LATCH

INPUT

REGISTER

REF

()A V

REF

(+)A

OUT

BYSHF

DB13

DB0

DAC 2

LATCH

DAC 2

INPUT

REGISTER

DAC 3

LATCH

INPUT

REGISTER

DAC 4

LATCH

INPUT

REGISTER

DAC 1

AD7835

OUT

AGND

DGND

LDAC

DSG B

CLR

DSG A

DAC 4

DAC 3

REF

()B V

REF

(+)B

ADDRESS

DECODE

INPUT

BUFFER

AD7834 FUNCTIONAL BLOCK DIAGRAM

DAC 1

LATCH

INPUT

REGISTER

REF

() V

REF

(+)

OUT

PAEN

PA0

PA1

PA2

PA3

PA4

CONTROL

LOGIC

ADDRESS

DECODE

SERIAL-TO-

PARALLEL

CONVERTER

FSYNC

DIN

SCLK

DAC 2

LATCH

DAC 2

INPUT

REGISTER

DAC 3

LATCH

DAC 3

INPUT

REGISTER

DAC 4

LATCH

DAC 4

INPUT

REGISTER

DAC 1

AD7834

OUT

AGND

DGND

LDAC

DSG

CLR

arameter

Units

Test Conditions/Comments

ACCURACY

Resolution

Bits

Relative Accuracy

LSB max

Differential Nonlinearity

0.9

LSB max

Guaranteed Monotonic Over Temperature

Full-Scale Error

REF

(+) = +7 V, V

REF

() = 7 V

MIN

to T

MAX

mV max

Zero-Scale Error

mV max

REF

(+) = +7 V, V

REF

() = 7 V

Gain Error

0.5

mV typ

REF

(+) = +7 V, V

REF

() = 7 V

Gain Temperature Coefficient

ppm FSR/

C typ

ppm FSR/

C max

DC Crosstalk

V max

See Terminology. R

= 10 k

REFERENCE INPUTS

DC Input Resistance

typ

Input Current

A max

Per Input

REF

(+) Range

0/+8.192

+7/+8.192

0/+8.192 V min/max

REF

() Range

8.192/0

8.192/0 V min/max

REF

(+)V

REF

()]

5/14

7/14

5/14

V min/max

For Specified Performance. Can Go as Low as
0 V, but Performance Not Guaranteed

DEVICE SENSE GROUND INPUTS

Input Current

A max

Per Input. V

DSG

= 2 V to +2 V

DIGITAL INPUTS

INH

, Input High Voltage

2.4

V min

INL

, Input Low Voltage

0.8

V max

INH

, Input Current

A max

, Input Capacitance

pF max

POWER REQUIREMENTS

5.0

V nom

5% for Specified Performance

15.0

V nom

5% for Specified Performance

15.0

V nom

5% for Specified Performance

Power Supply Sensitivity

Full Scale/

110

dB typ

Full Scale/

100

dB typ

0.2

0.5

mA max

INH

= V

, V

INL

= DGND

mA max

AD7834. V

INH

= 2.4 V min, V

INL

= 0.8 V max

mA max

AD7835. V

INH

= 2.4 V min, V

INL

= 0.8 V max

mA max

AD7834. Outputs Unloaded

mA max

AD7835. Outputs Unloaded

mA max

Outputs Unloaded

REV. A

AD7834/AD7835SPECIFICATIONS

= +5 V

5%; V

= +15 V

5%; V

= 15 V

5%; AGND =

DGND = 0 V; T

= T

MIN

to T

MAX

, unless otherwise noted)

(These characteristics are included for Design Guidance and are not
subject to production testing. )

AC PERFORMANCE CHARACTERISTICS

arameter

Units

Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time

s typ

Full-Scale Change to

1/2 LSB. DAC Latch Contents

Alternately Loaded with All 0s and All 1s

Digital-to-Analog Glitch Impulse

120

nV-s typ

Measured with V

REF

(+) = V

REF

() = 0 V. DAC Latch

Alternately Loaded with All 0s and All 1s

DC Output Impedance

0.5

typ

See Terminology

Channel-to-Channel Isolation

100

dB typ

See Terminology; Applies to the AD7835 Only

DAC to DAC Crosstalk

nV-s typ

See Terminology

Digital Crosstalk

nV-s typ

Feedthrough to DAC Output Under Test Due to
Change in Digital Input Code to Another Converter

Digital Feedthrough AD7834

0.2

nV-s typ

Effect of Input Bus Activity on DAC Output Under Test

Digital Feedthrough

AD7834

0.1

nV-s typ

Output Noise Spectral Density

@ 1 kHz

nV/

typ

All 1s Loaded to DAC. V

REF

(+) = V

REF

() = 0 V

NOTES

Temperature range is as follows: A Version: 40

C to +85

C; B Version: 40

C to +85

C; S Version: 55

C to +125

Guaranteed by design.

Specifications subject to change without notice

AD7834/AD7835

REV. A

TIMING SPECIFICATIONS

Parameter

Limit at T

MIN,

MAX

Units

Description

AD7834 Specific

100

ns min

SCLK Cycle Time

ns min

SCLK Low Time @ +25

ns min

SCLK Low Time 40

C to +85

ns min

SCLK Low Time 55

C to +125

ns min

SCLK High Time

ns min

FSYNC

, PAEN Setup Time

ns min

FSYNC

, PAEN Hold Time

ns min

Data Setup Time

ns min

Data Hold Time

ns min

LDAC

to FSYNC Setup Time

ns min

LDAC

to FSYNC Hold Time

ns min

Delay Between Write Operations

AD7835 Specific

ns min

A0, A1, A2, BYSHF to CS Setup Time

ns min

A0, A1, A2, BYSHF to CS Hold Time

ns min

to WR Setup Time

ns min

to WR Hold Time

ns min

Pulse Width

ns min

Data Setup Time

ns min

Data Hold Time

ns min

LDAC

to CS Setup Time

ns min

to LDAC Setup Time

ns min

LDAC

to CS Hold Time

General

ns min

LDAC

, CLR Pulse Width

NOTES

All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

Rise and fall times should be no longer than 50 ns.

Specifications subject to change without notice.

= +5 V

5%; V

= +15 V

5%; V

= 15 V

5%; AGND = DGND = 0 V)

A0. A1 A2

BYSHF

DATA

LDAC

(SIMULTANEOUS

UPDATE)

LDAC

(PRE-CHANNEL

UPDATE)

Figure 2. AD7835 Timing Diagram

LDAC

(SIMULTANEOUS

UPDATE)

LDAC

(PRE-CHANNEL

UPDATE)

1ST

CLK

2ND
CLK

24TH

CLK

D22

D23

SCLK

DIN

FSYNC

Figure 1. AD7834 Timing Diagram

REV. A

AD7834/AD7835

ABSOLUTE MAXIMUM RATINGS

= +25

C unless otherwise noted)

to DGND . . . . . . . . . . . . . . . 0.3 V, +7 V or V

+ 0.3 V

(Whichever Is Lower)

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, +17 V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, 17 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, +0.3 V
Digital Inputs to DGND . . . . . . . . . . . . . . 0.3 V, V

+ 0.3 V

REF

(+) to V

REF

() . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, +18 V

REF

(+) to AGND . . . . . . . . . . . . . . . V

0.3 V, V

+ 0.3 V

REF

() to AGND . . . . . . . . . . . . . . . V

0.3 V, V

+ 0.3 V

DSG to AGND . . . . . . . . . . . . . . . . . V

0.3 V, V

+ 0.3 V

OUT

(14) to AGND . . . . . . . . . . . . V

0.3 V, V

+ 0.3 V

Operating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . . . 40

C to +85

Extended (S Version). . . . . . . . . . . . . . . . . 55

C to +125

Storage Temperature Range . . . . . . . . . . . . . 65

C to +150

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150

Plastic Package

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . +75

C/W

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260

Cerdip Package

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . +52

C/W

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +300

WARNING!

ESD SENSITIVE DEVICE

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7834/AD7835 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Linearity

Temperature

Error

DNL

Package

Model

Range

(LSBs)

Option

AD7834AR

C to +85

0.9

R-28

AD7834BR

C to +85

0.9

R-28

AD7834AN

C to +85

0.9

N-28

AD7834BN

C to +85

0.9

N-28

AD7834SQ

C to +125

0.9

Q-28

AD7835AS

C to +85

0.9

S-44

AD7835BS

C to +85

0.9

S-44

AD7835AP

C to +85

0.9

P-44A

NOTES

R = Small Outline IC (SOIC); N = Plastic DIP; Q = Cerdip; S = Plastic Quad Flatpack (PQFP);

P = Plastic Leaded Chip Carrier (PLCC).

Contact Sales Office for availability.

SOIC Package

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . +75

C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220

PQFP Package

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 95

C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220

PLCC Package

Thermal Impedance. . . . . . . . . . . . . . . . . . . . . . +55

C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220

Power Dissipation (Any Package) . . . . . . . . . . . . . . . . 480 mW

NOTES

Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

Transient currents of up to 100 mA will not cause SCR latch up.

AD7834/AD7835

REV. A

AD7834 PIN DESCRIPTION

Pin Mnemonic

Description

Logic Power Supply; +5 V

5%.

Negative Analog Power Supply; 15 V

5%.

Positive Analog Power Supply; +15 V

5%.

DGND

Digital Ground.

AGND

Analog Ground.

REF

(+)

Positive Reference Input. The positive reference voltage is referred to AGND.

REF

()

Negative Reference Input. The negative reference voltage is referred to AGND.

OUT

1 . . . V

OUT

DAC Outputs.

DSG

Device Sense Ground Input. Used in conjunction with the CLR input for power-on protection of the DACs.
When CLR is low, the DAC outputs are forced to the potential on the DSG pin.

DIN

Serial Data Input.

SCLK

Clock input for writing data to the device.

FSYNC

Frame Sync Input. Active low logic input used, in conjunction with DIN and SCLK, to write data to the device
with serial data expected after the falling edge of this signal. The contents of the 24-bit serial-to-parallel input
register are transferred on the rising edge of this signal.

PA0 . . . PA4

Package Address Inputs. These inputs are hardwired high (V

) or low (DGND) to assign dedicated package

addresses in a multipackage environment.

PAEN

Package Address Enable Input. When low, this input allows normal operation of the device. When it is high, the
device ignores the package address (but not the channel address) in the serial data stream and loads the serial
data into the input registers. This feature is useful in a multipackage application where it can be used to load the
same data into the same channel in each package.

LDAC

Load DAC Input (level sensitive). This input signal in conjunction with the FSYNC input signal, determines
how the analog outputs are updated. If LDAC is maintained high while new data is being loaded into the
device's input registers, no change occurs on the analog outputs. Subsequently, when LDAC is brought low, the
contents of all four input registers are transferred into their respective DAC latches, updating the analog outputs.

Alternatively, if LDAC is kept low while new data is shifted into the device, then the addressed DAC latch (and
corresponding analog output) is updated immediately on the rising edge of FSYNC.

CLR

Asynchronous Clear Input (level sensitive, active low). When this input is brought low, all analog outputs are
switched to the externally set potential on the DSG pin. When CLR is brought high, the signal outputs remain at
the DSG potential until LDAC is brought low. When LDAC is brought low, the analog outputs are switched
back to reflect their individual DAC output levels. As long as CLR remains low, the LDAC signals are ignored
and the signal outputs remain switched to the potential on the DSG pin.

PIN CONFIGURATION

DIP AND SOIC

TOP VIEW

(Not to Scale)

NC = NO CONNECT

AGND

DSG

REF

()

REF

(+)

OUT

DGND

SCLK

LDAC

CLR

OUT

DIN

PA0

PA1

PA2

FSYNC

PA3

PA4

PAEN

AD7834

REV. A

AD7834/AD7835

AD7835 PIN DESCRIPTION

Pin Mnemonic

Description

Logic Power Supply; +5 V

5%.

Negative Analog Power Supply; 15 V

5%.

Positive Analog Power Supply; +15 V

5%.

DGND

Digital Ground.

AGND

Analog Ground.

REF

(+)A, V

REF

()A

Reference Inputs for DACs 1 and 2. These reference voltages are referred to AGND.

REF

(+)B, V

REF

()B

Reference Inputs for DACs 3 and 4. These reference voltages are referred to AGND.

OUT

1 . . . V

OUT

DAC Outputs.

Level-Triggered Chip Select Input (active low). The device is selected when this input is low.

DB0 . . . DB13

Parallel Data Inputs. The AD7835 can accept a straight 14-bit parallel word on DB0 to DB13, where
DB13 is the MSB and the BYSHF input is hardwired to a logic high. Alternatively for byte loading, the
bottom 8 data inputs, DB0DB7, are used for data loading while the top 6 data inputs, DB8 to DB13,
should be hardwired to a logic low. The BYSHF control input selects whether 8 LSBs or 6 MSBs of data
are being loaded into the device.

BYSHF

Byte Shift Input. When low, it shifts the data on DB0DB7 into the DB8DB13 half of the input register.

A0, A1, A2

Address inputs. A0 and A1 are decoded to select one of the four input latches for a data transfer. A2 is
used to select all four DACs simultaneously.

LDAC

Load DAC Input (level sensitive). This input signal in conjunction with the WR and CS input signals, de-
termines how the analog outputs are updated. If LDAC is maintained high while new data is being loaded
into the device's input registers, no change occurs on the analog outputs. Subsequently, when LDAC is
brought low, the contents of all four input registers are transferred into their respective DAC latches, up-
dating the analog outputs simultaneously.

Alternatively, if LDAC is brought low while new data is being entered, then the addressed DAC latch
(and corresponding analog output) is updated immediately on the rising edge of WR.

CLR

Asynchronous Clear Input (level sensitive, active low). When this input is brought low, all analog outputs
are switched to the externally set potentials on the DSG pins (V

OUT

1 and V

OUT

2 follow DSGA while

OUT

3 and V

OUT

4 follow DSGB). When CLR is brought high, the signal outputs remain at the DSG po-

tentials until LDAC is brought low. When LDAC is brought low, the analog outputs are switched back to
reflect their individual DAC output levels. As long as CLR remains low, the LDAC signals are ignored
and the signal outputs remain switched to the potential on the DSG pins.

Level-Triggered Write Input (active low). When active it is used in conjunction with CS to write data over
the input data bus.

DSGA

Device Sense Ground A Input. Used in conjunction with the CLR input for power-on protection of the
DACs. When CLR is low, DAC outputs V

OUT

1 and V

OUT

2 are forced to the potential on the DSGA pin.

DSGB

Device Sense Ground B Input. Used in conjunction with the CLR input for power-on protection of the
DACs. When CLR is low, DAC outputs V

OUT

3 and V

OUT

4 are forced to the potential on the DSGB pin.

AD7834/AD7835

REV. A

PIN CONFIGURATIONS

PQFP PLCC

41 40

18 19

21 22 23 24 25 26 27 28

PIN 1
IDENTIFIER

TOP VIEW

(Not to Scale)

DB4

DB5

DB6

DB1

DGND

DB0

DB2

DB3

DSGB

OUT

DB13

DB12

DB11

AD7835

DSGA

OUT

NC = NO CONNECT

CLR

LDAC

BYSHF

DB10

DB9

DB8

DB7

REF

(+)A

AGND

REF

(+)B

REF

()A

REF

()B

12 13 14 15 16 17

18 19

21 22

40 39 38

36 35 34

PIN 1
IDENTIFIER

TOP VIEW

(Not to Scale)

DSGB

OUT

DB13

DB12

DB11

AD7835

DB1

DGND

DB0

DB2

DB3

DB4

DB5

DB6

DSGA

OUT

NC = NO CONNECT

CLR

LDAC

BYSHF

DB10

DB9

DB8

DB7

REF

()A

REF

(+)A

AGND

(+)B

REF

()B

TERMINOLOGY
Relative Accuracy

Relative Accuracy or endpoint linearity is a measure of the max-
imum deviation from a straight line passing through the endpoints
of the DAC transfer function. It is measured after adjusting for
zero error and full-scale error and is normally expressed in Least
Significant Bits or as a percentage of full-scale reading.

Differential Nonlinearity

Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.

DC Crosstalk

Although the common input reference voltage signals are inter-
nally buffered, small IR drops in the individual DAC reference
inputs across the die can mean that an update to one channel
can produce a dc output change in one or other of the channel
outputs.

The four DAC outputs are buffered by op amps that share com-
mon V

and V

power supplies. If the dc load current changes

in one channel (due to an update), this can result in a further dc
change in one or other channel outputs. This effect is most ob-
vious at high load currents and reduces as the load currents are
reduced. With high impedance loads the effect is virtually
unmeasurable.

Output Voltage Settling Time

This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.

Digital-to-Analog Glitch Impulse

This is the amount of charge injected into the analog output when
the inputs change state. It is specified as the area of the glitch in
nV-secs. It is measured with the reference inputs connected to 0 V
and the digital inputs toggled between all 1s and all 0s.

Channel-to-Channel Isolation

Channel-to-channel isolation refers to the proportion of input

signal from one DACs reference input which appears at the out-
put of the other DAC. It is expressed in dBs.

The AD7834 has no specification for Channel-to-channel isola-
tion because it has one reference for all DACs. Channel-to-
channel isolation is specified for the AD7835.

DAC-to-DAC Crosstalk

DAC-to-DAC Crosstalk is defined as the glitch impulse that ap-
pears at the output of one converter due to both the digital
change and subsequent analog O/P change at another converter.
It is specified in nV-s.

Digital Crosstalk

The glitch impulse transferred to the output of one converter
due to a change in digital input code to the other converter is
defined as the Digital Crosstalk and is specified in nV-s.

Digital Feedthrough

When the device is not selected, high frequency logic activity on
the device's digital inputs can be capacitively coupled both
across and through the device to show up as noise on the V

OUT

pins. This noise is digital feedthrough.

DC Output Impedance

This is the effective output source resistance. It is dominated by
package lead resistance.

Full-Scale Error

This is the error in DAC output voltage when all 1s are loaded
into the DAC latch. Ideally the output voltage, with all 1s
loaded into the DAC latch, should be V

REF

(+) 1 LSB. Full-

Scale Error does not include Zero-Scale Error.

Zero-Scale Error

Zero-Scale Error is the error in the DAC output voltage when
all 0s are loaded into the DAC latch. Ideally the output voltage,
with all 0s in the DAC latch should be equal to V

REF

(). Zero-

Scale Error is mainly due to offsets in the output amplifier.

Gain Error

Gain Error is defined as (Full-Scale Error) (Zero-Scale Error).

REV. A

AD7834/AD7835Typical Performance Characteristics

CODE/1000

INL LSBs

1.0

0.8

1.0

0.4

0.2

0.0

0.2

0.6

0.4

0.6

0.8

Figure 3. Typical INL Plot

REF

(+) Volts

INL LSBs

0.5

0.45

0.35

0.3

0.25

0.2

0.4

0.15

0.1

0.05

2.5

DAC 1

DAC 3

DAC 4

DAC 2

TEMP = +25

ALL DACs FROM 1 DEVICE

Figure 6. Typical INL vs. V

REF

(+)

REF

(+) V

REF

() = 5 V)

0.7

0.6

0.2

0.4

0.3

0.2

0.1

0.5

0.1

VERT = 100mV/DIV
HORIZ = 1ľs/DIV

Figure 9. Typical Digital/Analog
Glitch Impulse

REF

(+) Volts

INL LSBs

0.9

0.8

0.6

0.5

0.2

0.1

0.7

0.4

0.3

Figure 5. Typical INL vs. V

REF

(+)

REF

() = 6 V)

CODE/1000

INL LSBs

1.0

0.8

1.0

0.4

0.2

0.0

0.2

0.6

0.4

0.6

0.8

Figure 8. Typical DAC-to-DAC
Matching

VOLTS

2.985

3.005

3.045

3.065

3.085

3.025

VERT = 2V/DIV
HORIZ = 1ľs/DIV

VERT = 10mV/DIV

HORIZ = 1ľs/DIV

REF

(+) = +7V

REF

() = 3V

VOLTS

3.105

Figure 11. Settling Time ()

CODE/1000

INL LSBs

0.5

0.4

0.5

0.2

0.1

0.0

0.1

0.3

0.2

0.3

0.4

Figure 4. Typical DNL Plot

DAC 4

TEMPERATURE 

INL LSBs

0.8

0.7

40

+85

+25

0.5

0.4

0.3

0.2

0.6

0.1

DAC 1

DAC 2

DAC 3

ALL DACs FROM ONE DEVICE

Figure 7. Typical INL vs.
Temperature

VOLTS

7.25

7.225

7.175

7.15

7.125

7.2

VERT = 2V/DIV
HORIZ = 1.2ľs/DIV

VERT = 25mV/DIV

HORIZ = 2.5ľs/DIV

REF

(+) = +7V

REF

() = 3V

VOLTS

7.1

Figure 10. Settling Time (+)

AD7834/AD7835

REV. A

Table I. D23 Control

D23

Control Function

Ignore following 23 bits of information.

Use following 23 bits of address and
data as normal.

D22 and D21:

Decoded to select one of the four DAC channels

within a device. The truth table for D22 and D21 is as shown
below in Table II.

Table II. D22, D21 Control

D22

D21

Control Function

Select Channel 1

Select Channel 2

Select Channel 3

Select Channel 4

D20D16

: Determines the package address. The five address

bits allow up to 32 separate packages to be individually de-
coded. Successful decoding is accomplished when these five bits
match up with the five hardwired pins on the physical package.

D15D0

: DAC Data to be loaded into identified DAC Input

Register. This data must have two leading 0s followed by 14 bits
of data, MSB first. The MSB is in location D13 of the 24-bit
data stream.

Data Loading--AD7835, Parallel Loading Device

Data can be loaded into the AD7835 in either straight 14-bit
wide words or in two 8-bit bytes.

In systems which can transfer 14-bit wide data, the BYSHF
input should be hardwired to V

. This sets up the AD7835

as a straight 14-bit parallel-loading DAC.

In 8-bit bus systems where it is required to transfer data in two
bytes, it is necessary to have the BYSHF input under logic con-
trol. In such a system the top 6 pins of the device data bus,
DB8DB13, must be hardwired to DGND. New low byte data
is loaded into the lower 8 places of the selected input register by
carrying out a write operation while holding BYSHF high. A
second write operation is subsequently executed with BYSHF
low and the 6 MSBs on the DB0DB5 inputs (DB5 = MSB).

D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9

NOTE: D23 IS THE FIRST BIT TRANSMITTED IN THE SERIAL WORD.

CONTROL BIT TO USE/IGNORE

FOLLOWING 23 BITS OF INFORMATION

CHANNEL ADDRESS MSB, D1

CHANNEL ADDRESS LSB, D2

PACKAGE ADDRESS MSB, PA4

PACKAGE ADDRESS, PA3

PACKAGE ADDRESS, PA2

PACKAGE ADDRESS, PA1

PACKAGE ADDRESS LSB, PA0

LSB, DB0

SECOND LSB, DB1

THIRD LSB, DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

DB10

THIRD MSB, DB11

SECOND MSB, DB12

MSB, DB13

SECOND LEADING ZERO

FIRST LEADING ZERO

Figure 12. Bit Assignments for 24-Bit Data Stream of AD7834

GENERAL DESCRIPTION
DAC Architecture--General

Each channel consists of a segmented 14-bit R-2R voltage-mode
DAC. The full- scale output voltage range is equal to the entire
reference span of V

REF

(+) V

REF

(). The DAC coding is

straight binary; all 0s produces an output of V

REF

(); all 1s pro-

duces an output of V

REF

(+) 1 LSB.

The analog output voltage of each DAC channel reflects the
contents of its own DAC latch. Data is transferred from the ex-
ternal bus to the input register of each DAC latch on a per
channel basis. The AD7835 has a feature whereby using the A2
pin, data can be transferred from the input data bus to all four
input registers simultaneously.

Bringing the CLR line low switches all the signal outputs,
V

OUT

1 to V

OUT

4, to the voltage level on the DSG pin. The sig-

nal outputs are held at this level after the removal of the CLR
signal and will not switch back to the DAC outputs until the
LDAC

signal is exercised.

Data Loading--AD7834, Serial Input Device

A write operation transfers 24 bits of data to the AD7834. The
first 8 bits are control data and the remaining 16 bits are DAC
data (see Figure 12). The control data identifies the DAC chan-
nel to be updated with new data and which of 32 possible pack-
ages the DAC resides in. In any communication with the device
the first 8 bits must always be control data.

Note that the DAC output voltages, V

OUT

1 to V

OUT

4, can be

updated to reflect new data in the DAC input registers in one of
two ways. The first method normally keeps LDAC high and
only pulses LDAC low momentarily to update all DAC latches
simultaneously with the contents of their respective input regis-
ters. The second method ties LDAC low, and channel updating
occurs on a per channel basis after new data has been clocked
into the AD7834. With LDAC low, the rising edge of FSYNC
transfers the new data directly into the DAC latch, updating the
analog output voltage.

Data being shifted into the AD7834 enters a 24-bit long shift
register. If more than 24 bits are clocked in before FSYNC goes
high, the last 24 bits transmitted are used as the control data
and DAC data.

Individual bit functions are discussed below.

D23

: Determines whether the following 23-bits of address and

data should be used or should be ignored. This is effectively a
software Chip Select bit. D23 is the first bit to be transmitted in
the 24-bit long word.

REV. A

AD7834/AD7835

Table IV. Code Table for Unipolar Operation

Binary Number in DAC Latch

Analog Output

MSB

LSB

OUT

)

1111

REF

(16383/16384) V

0000

REF

(8192/16384) V

1111

REF

(8191/16384) V

0000

0001

REF

(1/16384) V

0000

0 V

NOTE
V

REF

= V

REF

(+); V

REF

() = 0 V for unipolar operation.

For V

REF

(+) = +5 V, 1 LSB = +5 V/2

= +5 V/16384 = 305

Bipolar Configuration

Figure 14 shows the AD7834/AD7835 set up for

5 V opera-

tion. The AD588 provides precision

5 V tracking outputs

which are fed to the V

REF

(+) and V

REF

() inputs of the AD7834/

AD7835. The code table for bipolar operation of the AD7834/
AD7835 is shown in Table V.

+15V

+5V

OUT

(5 TO +5V)

1ľF

AGND

DGND

OUT

REF

(+)

REF

()

15V

ADDITIONAL PINS OMITTED FOR CLARITY

100k

AD7834/
AD7835

SIGNAL

GND

100k

R1
39k

AD588

Figure 14. Bipolar

5 V Operation

Table V. Code Table for Bipolar Operation

Binary Number in DAC Latch Analog Output
MSB

LSB

OUT

)

1111

REF

() + V

REF

(16383/16384) V

0000

0001

REF

() + V

REF

(8193/16384) V

0000

REF

() + V

REF

(8192/16384) V

1111

REF

() + V

REF

(8191/16384) V

0000

0001

REF

() + V

REF

(1/16384) V

0000

REF

() V

NOTE
V

REF

= (V

REF

(+) V

REF

()).

For V

REF

(+) = +5 V, and V

REF

() = 5 V, 1 LSB = 10 V/2

= 10 V/16384 =

610

In Figure 14, full-scale and bipolar zero adjustments are pro-
vided by varying the gain and balance on the AD588. R2 varies
the gain on the AD588 while R3 adjusts the offset of both the
+5 V and 5 V outputs together with respect to ground.

For bipolar-zero adjustment, the DAC is loaded with
1000 . . . 0000 and R3 is adjusted until V

OUT

= 0 V. Full scale

is adjusted by loading the DAC with all 1s and adjusting R2 un-
til V

OUT

= 5(8191/8192) V = 4.99939 V.

When bipolar-zero and full-scale adjustment are not needed, R2
and R3 can be omitted. Pin 12 on the AD588 should be con-
nected to Pin 11 and Pin 5 should be left floating.

When 14-bit transfers are being used, the DAC output voltages,
V

OUT

4, can be updated to reflect new data in the DAC

input registers in one of two ways. The first method normally
keeps LDAC high and only pulses LDAC low momentarily to
update all DAC latches simultaneously with the contents of
their respective input registers. The second method ties LDAC
low and channel updating occurs on a per channel basis after
new data is loaded to an input register.

In order to avoid the DAC output going to an intermediate
value during a 2-byte transfer, LDAC should not be tied low
permanently, but should be held high until the 2 bytes are writ-
ten to the input register. When the selected input register has
been loaded with the 2 bytes, LDAC should then be pulsed low
to update the DAC latch and, hence, perform the digital-to-
analog conversion.

In many applications, it may be acceptable to allow the DAC
output to go to an intermediate value during a 2-byte transfer.
In such applications, LDAC can be tied low, thus using one less
control line.

The actual DAC input register that is being written to is deter-
mined by the logic levels present on the devices address lines, as
shown in Table III.

Table III. AD7835--Address Line Truth Table

DAC Selected

DAC 1

DAC 2

DAC 3

DAC 4

All DACs Selected

Unipolar Configuration

Figure 13 shows the AD7834/AD7835 in the unipolar binary
circuit configuration. The V

REF

(+) input of the DAC is driven

by the AD586, a +5 V reference. V

REF

() is tied to ground.

Table IV gives the code table for unipolar operation of the
AD7834/AD7835.

+15V

+5V

OUT

(0 TO +5V)

SIGNAL

GND

1nF

AGND

DGND

OUT

REF

(+)

REF

()

15V

ADDITIONAL PINS OMITTED FOR CLARITY

R1
10k

AD7834/
AD7835

AD586

SIGNAL

GND

Figure 13. Unipolar +5 V Operation

Offset and gain may be adjusted in Figure 13 as follows: To ad-
just offset, disconnect the V

REF

() input from 0 V, load the DAC

with all 0s and adjust the V

REF

() voltage until V

OUT

= 0 V. For

gain adjustment, the AD7834/AD7835 should be loaded with
all 1s and R1 adjusted until V

OUT

= 5 V(16383/16384) =

4.999695.

Many circuits will not require these offset and gain adjustments. In
these circuits R1 can be omitted. Pin 5 of the AD586 may be left
open circuit and Pin 2 (V

REF

()) of the AD7834/AD7835 tied to

0 V.

AD7834/AD7835

REV. A

OUT

has been disconnected from the DSG pin by the opening

of G

but will track the voltage present at DSG via the unity

gain buffer.

Power-On with LDAC Low, CLR High

In many applications of the AD7834/AD7835 LDAC will be
kept continuously low, thus updating the DAC after each valid
data transfer. If LDAC is low when power is applied, then G

closed and G

is open, thus connecting the output of the DAC

to the input of the output amplifier. G

and G

will be closed

and G

open, connecting the amplifier as a unity gain

buffer, as before. V

OUT

is connected to DSG via G

and R (a

thin film resistance between DSG and V

OUT

) until V

and V

reach approximately

10 V. Then, the internal power-on cir-

cuitry opens G

and G

and closes G

and G

. This is the situa-

tion shown in Figure 18. V

OUT

is now at the same voltage as the

DAC output.

DAC

OUT

DSG

Figure 18. Output Stage with LDAC Low

Loading the DAC and Using the CLR Input

When LDAC goes low, it closes G

and opens G

as in Fig-

ure 18. The voltage at V

OUT

now follows the voltage present at

the output of the DAC. The output stage remains connected in
this manner until a CLR signal is applied. Then the situation
reverts to that shown in Figure 17. Once again V

OUT

remains at

the same voltage as DSG until LDAC goes low. This recon-
nects the DAC output to the unity gain buffer.

DSG Voltage Range

During power-on, the V

OUT

pins of the AD7834/AD7835 are

connected to the relevant DSG pins via G

and the thin film re-

sistor, R. The DSG potential must obey the max ratings at all
times. Thus, the voltage at DSG must always be within the
range V

0.3 V, V

+ 0.3 V. However, in order that the volt-

ages at the V

OUT

pins of the AD7834/AD7835 stay within

2 V of the relevant DSG potential during power-on, the

voltage applied to DSG should also be kept within the range
AGND 2 V, AGND + 2 V.

Once the AD7834/AD7835 has powered on and the on-chip
amplifiers have settled, the situation is as shown as in Figure 17.
Any voltage that is now applied to the DSG pin is buffered by
the same amplifier that buffers the DAC output voltage in nor-
mal operation. Thus, for specified operation, the maximum
voltage that can be applied to the DSG pin increases to the
maximum allowable V

REF

(+) voltage, and the minimum voltage

that can be applied to DSG is the minimum V

REF

() voltage. After

the AD7834/AD7835 has fully powered on, the outputs can
track any DSG voltage within this minimum/maximum range.

POWER-ON OF THE AD7834/AD7835

Power should normally be applied to the AD7834/AD7835 in
the following sequence: first V

and V

, then V

, then

REF

(+) and V

REF

().

CONTROLLED POWER-ON OF THE OUTPUT STAGE

A block diagram of the output stage of the AD7834/AD7835 is
shown in Figure 15. It is capable of driving a load of 10 k

parallel with 200 pF. G

to G

are transmission gates that are

used to control the power on voltage present at V

OUT

. G

and

are also used in conjunction with the CLR input to set V

OUT

to the user defined voltage present at the DSG pin.

DAC

OUT

DSG

Figure 15. Block Diagram of AD7834/AD7835 Output Stage

Power-On with CLR

Low, LDAC High

The output stage of the AD7834/AD7835 has been designed to
allow output stability during power-on. If CLR is kept low dur-
ing power-on, then just after power is applied to the part, the
situation is as depicted in Figure 16. G

, G

and G

are open

while G

, G

and G

are closed.

DAC

OUT

DSG

Figure 16. Output Stage with V

< 10 V

OUT

is kept within a few hundred millivolts of DSG via G

and

R. R is a thin-film resistor between DSG and V

OUT

. The out-

put amplifier is connected as a unity gain buffer via G

and the

DSG voltage is applied to the buffer input via G

. The amplifi-

ers output is thus at the same voltage as the DSG pin. The out-
put stage remains configured as in Figure 16 until the voltage at
V

and V

reaches approximately

10 V. By now the output

amplifier has enough headroom to handle signals at its input
and has also had time to settle. The internal power-on circuitry
opens G

and G

and closes G

and G

. This situation is shown

in Figure 17. Now the output amplifier is connected in unity
gain mode via G

and G

. The DSG voltage is still applied to

the noninverting input via G

. This voltage appears at V

OUT

DAC

OUT

DSG

Figure 17. Output Stage with V

> 10 V and CLR Low

REV. A

AD7834/AD7835

The V

REF

pins should never be allowed to float when power is

applied to the part. (V

REF

(+) should never be allowed to go

below V

REF

()0.3 V. V

REF

() should never be allowed to go

below V

0.3 V. V

should never be allowed to go below

0.3 V.

In some systems it may be necessary to introduce one or more
Schottky diodes between pins to prevent the above situations
arising at power-on. These diodes are shown in Figure 19. How-
ever in most systems, with careful consideration given to power
supply sequencing, the above rules will be adhered to and pro-
tection diodes won't be necessary.

REF

(+)

REF

()

AD7834

ADDITIONAL PINS OMITTED FOR CLARITY

SD103C
1N5711
1N5712

Figure 19. Power-ON Protection

MICROPROCESSOR INTERFACING
AD7834 to 80C51 Interface

A serial interface between the AD7834 and the 80C51 micro-
controller is shown in Figure 20. TXD of the 80C51 drives
SCLK of the AD7834 while RXD drives the serial data line of
the part.

The 80C51 provides the LSB of its SBUF register as the first bit
in the serial data stream. The AD7834 expects the MSB of the
24-bit write first. Therefore, the user will have to ensure that
the data in the SBUF register is arranged correctly so that this is
taken into account. When data is to be transmitted to the part,
P3.3 is taken low. Data on RXD is valid on the falling edge of
TXD. The 80C51 transmits its data in 8-bit bytes with only 8
falling clock edges occurring in the transmit cycle. To load data
to the AD7834, P3.3 is left low after the first eight bits are
transferred. A second byte is then transferred, with P3.3 still
kept low. After the third byte has been transferred, the P3.3
line is taken high.

CLR

LDAC

FSYNC

SCLK

DIN

P3.5

P3.4

P3.3

TXD

RXD

ADDITIONAL PINS OMITTED FOR CLARITY

AD7834

80C51

Figure 20. AD7834 to 80C51 Interface

LDAC

and CLR on the AD7834 are also controlled by 80C51

port outputs. The user can bring LDAC low after every three
bytes have been transmitted to update the DAC which has been
programmed. Alternatively, it is possible to wait until all the in-
put registers have been loaded (twelve byte transmits) and then
update the DAC outputs.

AD7834 to 68HC11 Interface

Figure 21 shows a serial interface between the AD7834 and the
68HC11 microcontroller. SCK of the 68HC11 drives SCLK of

the AD7834 while the MOSI output drives the serial data line,
DIN, of the AD7834. The FSYNC signal is derived from port
line PC7 in this example.

For correct operation of this interface, the 68HC11 should be
configured such that its CPOL bit is a 0 and its CPHA bit is a 1.
When data is to be transferred to the part, PC7 is taken low.
When the 68HC11 is configured like this, data on MOSI is valid
on the falling edge of SCK. The 68HC11 transmits its serial
data in 8-bit bytes, MSB first. The AD7834 expects the MSB
of the 24-bit write first also. Eight falling clock edges occur in
the transmit cycle. To load data to the AD7834, PC7 is left low
after the first eight bits are transferred. A second byte of data is
then transmitted serially to the AD7834. Then a third byte is
transmitted, and when this transfer is complete, the PC7 line is
taken high.

CLR

LDAC

FSYNC

SCLK

DIN

PC5

PC6

PC7

SCK

MOSI

ADDITIONAL PINS OMITTED FOR CLARITY

AD7834

68HC11

Figure 21. AD7834 to 68HC11 Interface

In Figure 21, LDAC and CLR are controlled by the PC6 and
PC5 port outputs. As with the 80C51, each DAC of the
AD7834 can be updated after each three-byte transfer, or else
all DACs can be simultaneously updated after twelve bytes have
been transferred.

AD7834 to ADSP-2101 Interface

An interface between the AD7834 and the ADSP-2101 is shown
in Figure 22. In the interface shown, SPORT0 is used to trans-
fer data to the part. SPORT1 is configured for alternate func-
tions. FO, the flag output on SPORT1, is connected to LDAC
and is used to load the DAC latches. In this way data can be
transferred from the ADSP-2101 to all the input registers in the
DAC and the DAC latches can be updated simultaneously. In
the application shown, the CLR pin on the AD7834 is con-
trolled by circuitry that monitors the power in the system.

CLR

LDAC

FSYNC

SCLK

DIN

TFS

SCK

ADDITIONAL PINS OMITTED FOR CLARITY

AD7834

ADSP-2101

POWER

MONITOR

Figure 22. AD7834 to ADSP-2101 Interface

The AD7834 requires 24 bits of serial data framed by a single
FSYNC

pulse. It is necessary that this FSYNC pulse stays low

until all the data has been transferred. This can be provided by
the ADSP-2101 in one of two ways. Both require setting the se-

AD7834/AD7835

REV. A

rial word length of the SPORT to 12 bits, with the following
conditions: Internal SCLK; Alternate framing mode; Active low
framing signal. Data can be transferred using the Autobuffering
feature of the ADSP-2101, sending two 12-bit words directly af-
ter each other. This ensures a continuous TFS pulse. Alterna-
tively, the first data word can be loaded to the serial port, the
subsequent interrupt that is generated can be trapped and then
the second data word can be sent immediately after the first.
Again this produces a continuous TFS pulse that frames the 24
data bits.

AD7834 to DSP56000/DSP56001 Interface

Figure 23 shows a serial interface between the AD7834 and the
DSP56000/DSP56001. The serial port is configured for a word
length of 24 bits, gated clock and with FSL0 and FSL1 control
bits each set to "0." Normal Mode Synchronous operation is
selected which allows the use of SC0 and SC1 as outputs con-
trolling CLR and LDAC. The framing signal on SC2 has to be
inverted before being applied to FSYNC. SCK is internally
generated on the DSP56000/DSP56001 and is applied to SCLK
on the AD7834. Data from the DSP56000/DSP56001 is valid
on the falling edge of SCK.

CLR

LDAC

FSYNC

SCLK

DIN

SC1

SC2

SCK

STD

SC0

ADDITIONAL PINS OMITTED FOR CLARITY

AD7834

DSP56000/
DSP56001

Figure 23. AD7834 to DSP5600/DSP56001 Interface

AD7834 to TMS32020/TMS320C25

A serial interface between the AD7834 and the TMS32020/
TMS320C25 DSP processor is shown in Figure 24. The CLKX
and FSX signals for the TMS32020/TMS32025 should be gen-
erated using an external clock/timer circuit. The CLKX and
FSX pin should be configured as inputs. The TMS32020/
TMS320C25 should be set up for an 8-bit serial data length.
Data can then be written to the AD7834 by writing three bytes
to the serial port of the TMS32020/TMS320C25. In the con-
figuration shown in Figure 24 the CLR input on the AD7834 is
controlled by the XF output on the TMS32020/TMS320C25.
The clock/timer circuit controls the LDAC input on the
AD7834. Alternatively, LDAC could also be tied to ground to
allow automatic update of the DAC latches after each transfer.

CLR

LDAC

FSYNC

SCLK

DIN

FSX

CLKX

ADDITIONAL PINS OMITTED FOR CLARITY

AD7834

TMS32020/

TMS320C25

CLOCK/

TIMER

Figure 24. AD7834 to TMS32020/TMS320C25 Interface

Interfacing the AD7835--16-Bit Interface

The AD7835 can be interfaced to a variety of microcontrollers
or DSP processors, both 8-bit and 16-bit. Figure 25 shows the
AD7835 interfaced to a generic 16-bit microcontroller/DSP
processor. BYSHF is tied to V

in this interface. The lower ad-

dress lines from the processor are connected to A0, A1 and A2
on the AD7835 as shown. The upper address lines are decoded
to provide a chip select signal for the AD7835. They are also
decoded (in conjunction with the lower address lines if need be)
to provide a LDAC signal. Alternatively, LDAC could be
driven by an external timing circuit or just tied low. The data
lines of the processor are connected to the data lines of the
AD7835. The selection of the DACs is as given in Table III.

ADDITIONAL PINS OMITTED FOR CLARITY

ADDRESS

DECODE

AD7835

D13

LDAC

BYSHF

D13

DATA

BUS

UPPER BITS OF

ADDRESS BUS

ľCONTROLLER/

DSP

PROCESSOR

Figure 25. AD7835 16-Bit Interface

8-Bit Interface

Figure 26 shows an 8-bit interface between the AD7835 and a
generic 8-bit microcontroller/DSP processor. Pins D13 to D8
of the AD7835 are tied to DGND. Pins D7 to D0 of the pro-
cessor are connected to pins D7 to D0 of the AD7835. BYSHF
is driven by the A0 line of the processor. This maps the DAC
upper bits and lower bits into adjacent bytes in the processors
address space. Table VI shows the truth table for addressing
the DACs in the AD7835. If, for example, the base address for
the DACs in the processor address space is decoded by the up-
per address bits to location HC000, then the first DAC's upper
and lower bits are at locations HC000 and HC001 respectively.

ADDITIONAL PINS OMITTED FOR CLARITY

ADDRESS

DECODE

AD7835

LDAC

BYSHF

DATA

BUS

UPPER BITS OF

ADDRESS BUS

ľCONTROLLER/

DSP

PROCESSOR

D13

DGND

Figure 26. AD7835 8-Bit Interface

REV. A

AD7834/AD7835

When writing to the DACs, the lower 8 bits must be written
first, followed by the upper 6 bits. The upper 6 bits should be
output on data lines D0 to D5. Once again, the upper address
lines of the processor are decoded to provide a CS signal. They
are also decoded in conjunction with lines A3 to A0 to provide a
LDAC

signal. Alternatively, LDAC can be driven by an exter-

nal timing circuit or, if it's acceptable to allow the DAC output
to go to an intermediate value between 8-bit writes, LDAC can
be tied low.

Table VI. DAC Selection, 8-Bit Interface

Processor Address Lines

DAC Selected

Upper 6 Bits of All DACs

Lower 8 Bits of All DACs

Upper 6 Bits, DAC 1

Lower 8 Bits, DAC 1

Upper 6 Bits, DAC 2

Lower 8 Bits, DAC 2

Upper 6 Bits, DAC 3

Lower 8 Bits, DAC 3

Upper 6 Bits, DAC 4

Lower 8-Bits, DAC 4

APPLICATIONS
Serial Interface to Multiple AD7834s

Figure 27 shows how the Package Address pins of the AD7834
are used to address multiple AD7834s. The figure shows only
10 devices, but up to 32 AD7834s can each be assigned a

ADDITIONAL PINS

OMITTED FOR CLARITY

AD7834

DEVICE 0

PAEN

LDAC

FSYNC

SCLK

DIN

PA0

PA1

PA2

PA3

PA4

AD7834

DEVICE 9

PAEN

LDAC

FSYNC

SCLK

DIN

PA0

PA1

PA2

PA3

PA4

ľCONTROLLER

CONTROL OUT

SYNC OUT

SERIAL CLOCK OUT

SERIAL DATA OUT

AD7834

DEVICE 1

PAEN

LDAC

FSYNC

SCLK

DIN

PA0

PA1

PA2

PA3

PA4

Figure 27. Serial Interface to Multiple AD7834s

unique address by hardwiring each of the Package Address pins
to V

or DGND. Normal operation of the device occurs when

PAEN

is low. When serial data is being written to the AD7834s,

only the device with the same package address as the package
address contained in the serial data will accept data into the
input registers. If, on the other hand, PAEN is high, the package
address is ignored and the data is loaded into the same channel
on each package.

The main limitation with multiple packages is the output update
rate. For example, if an output update rate of 10 kHz is re-
quired, then there are 100

s to load all DACs. Assuming a se-

rial clock frequency of 10 MHz, it takes 2.5

s to load data to

one DAC. Thus forty DACs or ten packages can be updated in
this time. As the update rate requirement decreases, the num-
ber of possible packages increases.

Opto-Isolated Interface

In many process control applications it is necessary to provide
an isolation barrier between the controller and the unit being
controlled. Opto-isolators can provide voltage isolation in ex-
cess of 3 kV. The serial loading structure of the AD7834 makes
it ideal for opto-isolated interfaces as the number of interface
lines is kept to a minimum. Figure 28 shows a 5-channel iso-
lated interface to the AD7834. Multiple devices are connected
to the outputs of the opto-coupler and controlled as explained
above. To reduce the number of opto-isolators, the PAEN line
doesn't need to be controlled if it is not used. If the PAEN line
is not controlled by the microcontroller then it should be tied
low at each device. If simultaneous updating of the DACs is not
required, then LDAC pin on each part can be tied permanently
low and a further opto-isolator is not needed.

ľCONTROLLER

CONTROL OUT

SYNC OUT

SERIAL CLOCK OUT

SERIAL DATA OUT

OPTO-COUPLER

PAEN

LDAC

FSYNC

TO SCLKs

TO DINs

Figure 28. Opto-Isolated Interface

Automated Test Equipment

The AD7834/AD7835 is particularly suited for use in an auto-
mated test environment. Figure 29 shows the AD7835 provid-
ing the necessary voltages for the pin driver and the window
comparator in a typical ATE pin electronics configuration. Two
AD588s are used to provide reference voltages for the AD7835.
In the configuration shown, the AD588s are configured so that
the voltage at Pin 1 is 5 V greater than the voltage at Pin 9 and
the voltage at Pin 15 is 5 V less than the voltage at Pin 9.

One of the AD588s is used as a reference for DACs 1 and 2.
These DACs are used to provide high and low levels for the pin
driver. The pin driver may have an associated offset. This can
be nulled by applying an offset voltage to Pin 9 of the AD588.
First, the code 1000 . . . 0000 is loaded into the DAC1 latch
and the pin driver output is set to the DAC1 output. The

AD7834/AD7835

REV. A

OFFSET

voltage is adjusted until 0 V appears between the pin

driver output and DUT GND. This causes both V

REF

(+)A and

REF

()A to be offset with respect to AGND by an amount

equal to V

OFFSET

. However the output of the pin driver will vary

from 5 V to +5 V with respect to DUT GND as the DAC in-
put code varies from 000 . . . 000 to 111 . . . 111. The V

OFFSET

voltage is also applied to the DSG A pin. When a clear is per-
formed on the AD7835, the output of the pin driver will be 0 V
with respect to DUT GND.

ADDITIONAL PINS OMITTED FOR CLARITY

4
6

10 11 12

1ľF

+15V 15V

0.1ľF

AD588

4
6

11
12

1ľF

+15V 15V

AD588

DUT
GND

TO TESTER

WINDOW

COMPARATOR

15V

+15V

REF

(+)A

REF

()A

DSG A

REF

(+)B

REF

()B

AD7835

OUT

DSG B

AGND

DUT
GND

DUT

OFFSET

PIN

DRIVER

Figure 29. ATE Application

The other AD588 is used to provide a reference voltage for
DACs 3 and 4. These provide the reference voltages for the
window comparator shown in the diagram. Note that Pin 9 of
this AD588 is connected to DUT GND. This causes V

REF

(+)B

and V

REF

()B to be referenced to DUT GND. As DAC 3 and

DAC 4 input codes vary from 000 . . . 000 to 111 . . . 111,
V

OUT

3 and V

OUT

4 vary from 5 V to +5 V with respect to DUT

GND. DUT GND is also connected to DSG B. When the
AD7835 is cleared, V

OUT

3 and V

OUT

4 are cleared to 0 V with

respect to DUT GND.

Care must be taken to ensure that the maximum and minimum
voltage specs for the AD7835 reference voltages are not broken
in the above configuration.

Power Supply Bypassing and Grounding

In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the

AD7834/AD7835 is mounted should be designed such that the
analog and digital sections are separated and confined to certain
areas of the board. This facilitates the use of ground planes that
can be separated easily. A minimum etch technique is generally
best for ground planes as it gives the best shielding. Digital and
analog ground planes should only be joined at one place. If the
AD7834/AD7835 is the only device requiring an AGND to
DGND connection, then the ground planes should be con-
nected at the AGND and DGND pins of the AD7834/AD7835.
If the AD7834/AD7835 is in a system where multiple devices
require an AGND to DGND connection, the connection should
still be made at one point only, a star ground point which
should be established as close as possible to the AD7834/
AD7835.

Digital lines running under the device should be avoided as
these will couple noise onto the die. The analog ground plane
should be allowed to run under the AD7834/AD7835 to avoid
noise coupling. The power supply lines of the AD7834/
AD7835 should use as large a trace as possible to provide low
impedance paths and reduce the effects of glitches on the power
supply line. Fast switching signals like clocks should be shielded
with digital ground to avoid radiating noise to other parts of the
board and should never be run near the analog inputs. Avoid
crossover of digital and analog signals. Traces on opposite sides
of the board should run at right angles to each other. This re-
duces the effects of feedthrough through the board. A
microstrip technique is by far the best but not always possible
with a double sided board. In this technique, the component
side of the board is dedicated to ground plane while signal traces
are placed on the solder side.

The AD7834/AD7835 should have ample supply bypassing lo-
cated as close to the package as possible, ideally right up against
the device. Figure 30 shows the recommended capacitor values
of 10

F in parallel with 0.1

F on each of the supplies. The

F capacitors are the tantalum bead type. The 0.1

F ca-

pacitor should have low Effective Series Resistance (ESR) and
Effective Series Inductance (ESI), such as the common ceramic
types, which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.

10ľF

0.1ľF

ADDITIONAL PINS OMITTED FOR CLARITY

10ľF

0.1ľF

10ľF

0.1ľF

AD7834/
AD7835

AGND

DGND

Figure 30. Power Supply Decoupling

REV. A

AD7834/AD7835

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

C2027a69/95

PRINTED IN U.S.A.

28-Leaded Plastic DIP (N-28)

1.565 (39.70)

1.380 (35.10)

0.580 (14.73)
0.485 (12.32)

PIN 1

0.022 (0.558)

0.014 (0.356)

0.060 (1.52)

0.015 (0.38)

0.200 (5.05)

0.125 (3.18)

0.150
(3.81)
MIN

SEATING
PLANE

0.250

(6.35)

MAX

0.100
(2.54)

BSC

0.070
(1.77)

MAX

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)
0.125 (3.18)

0.625 (15.87)

0.600 (15.24)

28-Leaded SOIC (R-28)

0.7125 (18.10)

0.6969 (17.70)

0.4193 (10.65)

0.3937 (10.00)

0.2992 (7.60)

0.2914 (7.40)

PIN 1

SEATING

PLANE

0.0118 (0.30)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

0.1043 (2.65)

0.0926 (2.35)

0.0500

(1.27)

BSC

0.0125 (0.32)

0.0091 (0.23)

0.0500 (1.27)

0.0157 (0.40)

0.0291 (0.74)

0.0098 (0.25)

x 45

28-Leaded Cerdip (Q-28)

0.610 (15.49)

0.500 (12.70)

PIN 1

0.005 (0.13) MIN

0.100 (2.54) MAX

SEATING
PLANE

0.026 (0.66)

0.014 (0.36)

0.110 (2.79)

0.090 (2.29)

0.225

(5.72)

MAX

1.490 (37.85) MAX

0.150
(3.81)
MIN

0.070 (1.78)

0.030 (0.76)

0.200 (5.08)

0.125 (3.18)

0.015
(0.38)
MIN

0.620 (15.75)

0.590 (14.99)

0.018 (0.46)

0.008 (0.20)

44-Pin PQFP (S-44)

0.548 (13.925)

0.546 (13.875)

TOP VIEW

(PINS DOWN)

0.033 (0.84)

0.029 (0.74)

0.398 (10.11)

0.390 (9.91)

0.016 (0.41)

0.012 (0.30)

0.083 (2.11)

0.077 (1.96)

0.040 (1.02)

0.032 (0.81)

0.040 (1.02)

0.032 (0.81)

SEATING

PLANE

0.096 (2.44)

MAX

0.037 (0.94)

0.025 (0.64)

0.8

44-Pin PLCC (P-44A)

PIN 1

IDENTIFIER

TOP VIEW

(PINS DOWN)

0.695 (17.65)

0.685 (17.40)

0.656 (16.66)

0.650 (16.51)

0.048 (1.21)

0.042 (1.07)

0.048 (1.21)

0.042 (1.07)

0.020

(0.50)

0.021 (0.53)

0.013 (0.33)

0.050
(1.27)
BSC

0.63 (16.00)

0.59 (14.99)

0.032 (0.81)

0.026 (0.66)

0.180 (4.57)

0.165 (4.19)

0.040 (1.01)

0.025 (0.64)

0.025 (0.63)

0.015 (0.38)

0.110 (2.79)

0.085 (2.16)

0.056 (1.42)

0.042 (1.07)

Part Number AD7835