REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD7822/AD7825/AD7829
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
3 V/5 V, 2 MSPS, 8-Bit, 1-, 4-, 8-Channel
Sampling ADCs
FUNCTIONAL BLOCK DIAGRAM
CONVST
DB0
DB7
8-BIT
HALF
FLASH
ADC
PARALLEL
PORT
VREF
IN
/REF
OUT
EOC
RD
CS
AGND
V
MID
A0* A1* A2*
V
IN1
COMP
PD
*
2.5V
REF
V
DD
CONTROL
LOGIC
DGND
INPUT
MUX
V
IN2*
V
IN3*
V
IN4*
V
IN5*
V
IN6*
V
IN7*
V
IN8*
T/H
*A0, A1
*A2
*
PD
*V
IN2
TO V
IN4
*V
IN4
TO V
IN8
AD7825/AD7829
AD7829
AD7822/AD7825
AD7825/AD7829
AD7829
BUF
FEATURES
8-Bit Half-Flash ADC with 420 ns Conversion Time
1, 4 and 8 Single-Ended Analog Input Channels
Available with Input Offset Adjust
On-Chip Track-and-Hold
SNR Performance Given for Input Frequencies Up to
10 MHz
On-Chip Reference (2.5 V)
Automatic Power-Down at the End of Conversion
Wide Operating Supply Range
3 V 10% and 5 V 10%
Input Ranges
0 V to 2 V p-p, V
DD
= 3 V 10%
0 V to 2.5 V p-p, V
DD
= 5 V 10%
Flexible Parallel Interface with EOC Pulse to Allow
Stand-Alone Operation
APPLICATIONS
Data Acquisition Systems, DSP Front Ends
Disk Drives
Mobile Communication Systems, Subsampling
Applications
GENERAL DESCRIPTION
The AD7822, AD7825, and AD7829 are high speed, 1-, 4-, and
8-channel, microprocessor-compatible, 8-bit analog-to-digital
converters with a maximum throughput of 2 MSPS. The AD7822,
AD7825, and AD7829 contain an on-chip reference of 2.5 V
(2% tolerance), a track/hold amplifier, a 420 ns 8-bit half-flash
ADC and a high speed parallel interface. The converters can
operate from a single 3 V
±
10% and 5 V
±
10% supply.
The AD7822, AD7825, and AD7829 combine the convert start
and power-down functions at one pin, i.e., the
CONVST pin.
This allows a unique automatic power-down at the end of a
conversion to be implemented. The logic level on the
CONVST
pin is sampled after the end of a conversion when an
EOC (End
of Conversion) signal goes high, and if it is logic low at that
point, the ADC is powered down. The AD7822 and AD7825
also have a separate power-down pin. (See Operating Modes
section of the data sheet.)
The parallel interface is designed to allow easy interfacing to
microprocessors and DSPs. Using only address decoding logic,
the parts are easily mapped into the microprocessor address
space. The
EOC pulse allows the ADCs to be used in a stand-
alone manner. (See Parallel Interface section of the data sheet.)
The AD7822 and AD7825 are available in a 20-/24-lead 0.3"
wide, plastic dual-in-line package (DIP), a 20-/24-lead small
outline IC (SOIC) and a 20-/24-lead thin shrink small outline
package (TSSOP). The AD7829 is available in a 28-lead 0.6"
wide, plastic dual-in-line package (DIP), a 28-lead small outline
IC (SOIC) and in a 28-lead thin shrink small outline package
(TSSOP).
PRODUCT HIGHLIGHTS
1. Fast Conversion Time
The AD7822, AD7825, and AD7829 have a conversion time
of 420 ns. Faster conversion times maximize the DSP pro-
cessing time in a real time system.
2. Analog Input Span Adjustment
The V
MID
pin allows the user to offset the input span. This
feature can reduce the requirements of single supply op amps
and take into account any system offsets.
3. FPBW (Full Power Bandwidth) of Track and Hold
The track-and-hold amplifier has an excellent high frequency
performance. The AD7822, AD7825, and AD7829 are
capable of converting full-scale input signals up to a fre-
quency of 10 MHz. This makes the parts ideally suited to
subsampling applications.
4. Channel Selection
Channel selection is made without the necessity of writing to
the part.
2
REV. A
AD7822/AD7825/AD7829SPECIFICATIONS
Parameter
Version B
Unit
Test Condition/Comment
DYNAMIC PERFORMANCE
f
IN
= 30 kHz. f
SAMPLE
= 2 MHz
Signal to (Noise + Distortion) Ratio
1
48
dB min
Total Harmonic Distortion
1
55
dB max
Peak Harmonic or Spurious Noise
1
55
dB max
Intermodulation Distortion
1
fa = 27.3 kHz, fb = 28.3 kHz
2nd Order Terms
65
dB typ
3rd Order Terms
65
dB typ
Channel-to-Channel Isolation
1
70
dB typ
f
IN
= 20 kHz
DC ACCURACY
Resolution
8
Bits
Minimum Resolution for Which
No Missing Codes Are Guaranteed
8
Bits
Integral Nonlinearity (INL)
1
±
0.75
LSB max
Differential Nonlinearity (DNL)
1
±
0.75
LSB max
Gain Error
1
±
2
LSB max
Gain Error Match
1
±
0.1
LSB typ
Offset Error
1
±
1
LSB max
Offset Error Match
1
±
0.1
LSB typ
ANALOG INPUTS
2
See Analog Input Section
V
DD
= 5 V
±
10%
Input Voltage Span = 2.5 V
V
IN1
to V
IN8
Input Voltage
V
DD
V max
0
V min
V
MID
Input Voltage
V
DD
1.25
V max
Default V
MID
= 1.25 V
1.25
V min
V
DD
= 3 V
±
10%
Input Voltage Span = 2 V
V
IN1
to V
IN8
Input Voltage
V
DD
V max
0
V min
V
MID
Input Voltage
V
DD
1
V max
Default V
MID
= 1 V
1
V min
V
IN
Input Leakage Current
±
1
µ
A max
V
IN
Input Capacitance
15
pF max
V
MID
Input Impedance
6
k
typ
REFERENCE INPUT
V
REF IN
/
OUT
Input Voltage Range
2.55
V max
2.5 V + 2%
2.45
V min
2.5 V 2%
Input Current
1
µ
A typ
100
µ
A max
ON-CHIP REFERENCE
Nominal 2.5 V
Reference Error
±
50
mV max
Temperature Coefficient
50
ppm/
°
C typ
LOGIC INPUTS
Input High Voltage, V
INH
2.4
V min
V
DD
= 5 V
±
10%
Input Low Voltage, V
INL
0.8
V max
V
DD
= 5 V
±
10%
Input High Voltage, V
INH
2
V min
V
DD
= 3 V
±
10%
Input Low Voltage, V
INL
0.4
V max
V
DD
= 3 V
±
10%
Input Current, I
IN
±
1
µ
A max
Typically 10 nA, V
IN
= 0 V to V
DD
Input Capacitance, C
IN
10
pF max
LOGIC OUTPUTS
Output High Voltage, V
OH
I
SOURCE
= 200
µ
A
4
V min
V
DD
= 5 V
±
10%
2.4
V min
V
DD
= 3 V
±
10%
Output Low Voltage, V
OL
I
SINK
= 200
µ
A
0.4
V max
V
DD
= 5 V
±
10%
0.2
V max
V
DD
= 3 V
±
10%
High Impedance Leakage Current
±
1
µ
A max
High Impedance Capacitance
10
pF max
(V
DD
= 3 V 10%, V
DD
= 5 V 10%, GND = 0 V,
V
REF IN/OUT
= 2.5 V. All specifications 40 C to +85 C unless otherwise noted.)
Parameter
Version B
Unit
Test Condition/Comment
CONVERSION RATE
Track/Hold Acquisition Time
200
ns max
See Functional Description Section
Conversion Time
420
ns max
POWER SUPPLY REJECTION
V
DD
±
10%
±
1
LSB max
POWER REQUIREMENTS
V
DD
4.5
V min
5 V
±
10%. For Specified Performance
5.5
V max
V
DD
2.7
V min
3 V
±
10%. For Specified Performance
3.3
V max
I
DD
Normal Operation
12
mA max
8 mA Typically
Power-Down
5
µ
A max
Logic Inputs = 0 V or V
DD
0.2
µ
A typ
Power Dissipation
V
DD
= 3 V
Normal Operation
36
mW max
Typically 24 mW
Power-Down
200 kSPS
9.58
mW max
1 MSPS
47.88
mW max
NOTES
1
See Terminology section of this data sheet.
2
Refer to the Analog Input section for an explanation of the Analog Input(s).
Specifications subject to change without notice.
ORDERING GUIDE
Linearity
Package
Package
Model
Error
Description
Option
AD7822BN
±
0.75 LSB
Plastic DIP
N-20
AD7822BR
±
0.75 LSB
Small Outline IC
R-20
AD7822BRU
±
0.75 LSB
Thin Shrink Small
RU-20
Outline (TSSOP)
AD7825BN
±
0.75 LSB
Plastic DIP
N-24
AD7825BR
±
0.75 LSB
Small Outline IC
R-24
AD7825BRU
±
0.75 LSB
Thin Shrink Small
RU-24
Outline (TSSOP)
AD7829BN
±
0.75 LSB
Plastic DIP
N-28
AD7829BR
±
0.75 LSB
Small Outline IC
R-28
AD7829BRU
±
0.75 LSB
Thin Shrink Small
RU-28
Outline (TSSOP)
+2.1V
I
OL
200 A
200 A
I
OH
TO
OUTPUT
PIN
C
L
50pF
Figure 1. Load Circuit for Access Time and Bus
Relinquish Time
AD7822/AD7825/AD7829
3
REV. A
AD7822/AD7825/AD7829
4
REV. A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7822/AD7825/AD7829 features proprietary ESD protection circuitry, perma-
nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
TIMING CHARACTERISTICS
1, 2
Parameter 5 V 10%
3 V 10%
Unit
Conditions/Comments
t
1
420
420
ns max
Conversion Time.
t
2
20
20
ns min
Minimum
CONVST Pulsewidth.
t
3
30
30
ns min
Minimum time between the rising edge of
RD and next falling edge of convert start.
t
4
110
110
ns max
EOC Pulsewidth.
70
70
ns min
t
5
10
10
ns max
RD rising edge to EOC pulse high.
t
6
0
0
ns min
CS to RD setup time.
t
7
0
0
ns min
CS to RD hold time.
t
8
30
30
ns min
Minimum
RD Pulsewidth.
t
9
3
10
20
ns max
Data access time after
RD low.
t
10
4
5
5
ns min
Bus relinquish time after
RD high.
20
20
ns max
t
11
10
10
ns min
Address setup time before falling edge of
RD.
t
12
15
15
ns min
Address hold time after falling edge of
RD.
t
13
200
200
ns min
Minimum time between new channel selection and convert start.
t
POWER UP
25
25
µ
s typ
Power-up time from rising edge of
CONVST using on-chip reference.
t
POWER UP
1
1
µ
s max
Power-up time from rising edge of
CONVST using external 2.5 V reference.
NOTES
1
Sample tested to ensure compliance.
2
See Figures 20, 21 and 22.
3
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V with V
DD
= 5 V
±
10%, and time required for an out-
put to cross 0.4 V or 2.0 V with V
DD
= 3 V
±
10%.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
10
, quoted in the timing characteristics is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
*
(T
A
= +25
°
C unless otherwise noted)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
Analog Input Voltage to AGND
V
IN1
to V
IN8
. . . . . . . . . . . . . . . . . . . 0.3 V to V
DD
+ 0.3 V
Reference Input Voltage to AGND . . . 0.3 V to V
DD
+ 0.3 V
V
MID
Input Voltage to AGND . . . . . . . 0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to DGND . . . . . 0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to DGND . . . . 0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . 40
°
C to +85
°
C
Storage Temperature Range . . . . . . . . . . . . 65
°
C to +150
°
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150
°
C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105
°
C/W
Lead Temperature, (Soldering, 10 sec) . . . . . . . . . . . 260
°
C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75
°
C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215
°
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 220
°
C
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 128
°
C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215
°
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
°
C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
(V
REF IN/OUT
= 2.5 V. All specifications 40 C to +85 C unless otherwise noted)
WARNING!
ESD SENSITIVE DEVICE
AD7822/AD7825/AD7829
5
REV. A
PIN FUNCTION DESCRIPTIONS
Mnemonic
Description
V
IN1
to V
IN8
Analog Input Channels. The AD7822 has a single input channel; the AD7825 and AD7829 have four and eight
analog input channels respectively. The inputs have an input span of 2.5 V and 2 V depending on the sup-
ply voltage (V
DD
). This span may be centered anywhere in the range AGND to V
DD
using the V
MID
Pin. The
default input range (V
MID
unconnected) is AGND to 2 V (V
DD
= 3 V
±
10%) or AGND to 2.5 V (V
DD
= 5 V
±
10%). See Analog Input section of the data sheet for more information.
V
DD
Positive supply voltage, 3 V
±
10% and 5 V
±
10%.
AGND
Analog Ground. Ground reference for track/hold, comparators, reference circuit and multiplexer.
DGND
Digital Ground. Ground reference for digital circuitry.
CONVST
Logic Input Signal. The convert start signal initiates an 8-bit analog-to-digital conversion on the falling edge of
this signal. The falling edge of this signal places the track/hold in hold mode. The track/hold goes into track
mode again 120 ns after the start of a conversion. The state of the
CONVST signal is checked at the end of
a conversion. If it is logic low, the AD7822/AD7825/AD7829 will power down. (See Operating Mode section of
the data sheet.)
EOC
Logic Output. The End of Conversion signal indicates when a conversion has finished. The signal can be used
to interrupt a microcontroller when a conversion has finished or latch data into a gate array. (See Parallel Inter-
face section of this data sheet.)
CS
Logic input signal. The chip select signal is used to enable the parallel port of the AD7822, AD7825, and AD7829.
This is necessary if the ADC is sharing a common data bus with another device.
PD
Logic Input. The Power-Down pin is present on the AD7822 and AD7825 only. Bringing the
PD pin low
places the AD7822 and AD7825 in Power-Down mode. The ADCs will power-up when
PD is brought logic
high again.
RD
Logic Input Signal. The read signal is used to take the output buffers out of their high impedance state and
drive data onto the data bus. The signal is internally gated with the
CS signal. Both RD and CS must be logic
low to enable the data bus.
A0A2
Channel Address Inputs. The address of the next multiplexer channel must be present on these inputs when the
RD signal goes low.
DB0DB7
Data Output Lines. They are normally held in a high impedance state. Data is driven onto the data bus when
both
RD and CS go active low.
V
REF IN
/
OUT
Analog Input and Output. An external reference can be connected to the AD7822, AD7825, and AD7829 at this
pin. The on-chip reference is also available at this pin.
PIN CONFIGURATIONS
DIP/SOIC/TSSOP
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD7822
NC = NO CONNECT
DB2
DB6
DB5
DB4
DB3
DB1
DB0
CONVST
V
DD
AGND
DB7
CS
RD
DGND
EOC
PD
NC
V
IN1
V
MID
V
REF
13
16
15
14
24
23
22
21
20
19
18
17
TOP VIEW
(Not to Scale)
12
11
10
9
8
1
2
3
4
7
6
5
AD7825
DB2
DB6
DB5
DB4
DB3
DB1
DB0
CONVST
V
DD
AGND
DB7
CS
RD
DGND
EOC
A1
A0
V
IN1
V
MID
V
REF
PD
V
IN4
V
IN2
V
IN3
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
AD7829
DB2
DB6
DB5
DB4
DB3
DB1
DB0
CONVST
V
DD
AGND
DB7
CS
RD
DGND
EOC
A2
A1
V
IN1
V
MID
V
REF
A0
V
IN8
V
IN7
V
IN6
V
IN2
V
IN5
V
IN4
V
IN3
AD7822/AD7825/AD7829
6
REV. A
TERMINOLOGY
Signal-to-(Noise + Distortion) Ratio
This is the measured ratio of signal-to-(noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (f
S
/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal-to-(noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB
Thus, for an 8-bit converter, this is 50 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7822/AD7825/AD7829
it is defined as:
THD (dB)
=
20 log
V
2
2
+
V
3
2
+
V
4
2
+
V
5
2
+
V
6
2
V
1
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
, V
5
, and V
6
are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
S
/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa
±
nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second order
terms include (fa + fb) and (fa fb), while the third order terms
include (2fa + fb), (2fa fb), (fa + 2fb) and (fa 2fb).
The AD7822/AD7825/AD7829 are tested using the CCIF stan-
dard where two input frequencies near the top end of the input
bandwidth are used. In this case, the second and third order
terms are of different significance. The second order terms are
usually distanced in frequency from the original sine waves
while the third order terms are usually at a frequency close to
the input frequencies. As a result, the second and third order
terms are specified separately. The calculation of the intermodula-
tion distortion is as per the THD specification where it is the
ratio of the rms sum of the individual distortion products to the
rms amplitude of the fundamental expressed in dBs.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of crosstalk
between channels. It is measured by applying a full-scale 20 kHz
sine wave signal to one input channel and determining how
much that signal is attenuated in each of the other channels.
The figure given is the worst case across all four or eight chan-
nels of the AD7825 and AD7829 respectively.
Relative Accuracy
Relative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential Nonlinearity
The difference between the measured and the ideal 1 LSB change
between any two adjacent codes in the ADC.
Offset Error
The deviation of the 128th code transition (01111111) to
(10000000) from the ideal, i.e., V
MID
.
Offset Error Match
The difference in offset error between any two channels.
Zero-Scale Error
The deviation of the first code transition (00000000) to
(00000001) from the ideal, i.e., V
MID
1.25 V + 1 LSB (V
DD
=
5 V
±
10%), or V
MID
1.0 V + 1 LSB (V
DD
= 3 V
±
10%).
Full-Scale Error
The deviation of the last code transition (11111110) to
(11111111) from the ideal, i.e., V
MID
+ 1.25 V 1 LSB (V
DD
=
5 V
±
10%), or V
MID
+ 1.0 V 1 LSB (V
DD
= 3 V
±
10%).
Gain Error
The deviation of the last code transition (1111 . . . 110) to
(1111 . . . 111) from the ideal, i.e., V
REF
1 LSB, after the off-
set error has been adjusted out.
Gain Error Match
The difference in gain error between any two channels.
Track/Hold Acquisition Time
The time required for the output of the track/hold amplifier to
reach its final value, within
±
1/2 LSB, after the point at which
the track/hold returns to track mode. This happens approxi-
mately 120 ns after the falling edge of
CONVST.
It also applies to situations where a change in the selected input
channel takes place or where there is a step input change on the
input voltage applied to the selected V
IN
input of the AD7822/
AD7825/AD7829. It means that the user must wait for the dura-
tion of the track/hold acquisition time after a channel change/step
input change to V
IN
before starting another conversion, to
ensure that the part operates to specification.
PSR (Power Supply Rejection)
Variations in power supply will affect the full-scale transition,
but not the converter's linearity. Power supply rejection is the
maximum change in the full-scale transition point due to a
change in power supply voltage from the nominal value.
CIRCUIT DESCRIPTION
The AD7822, AD7825, and AD7829 consist of a track-and-hold
amplifier followed by a half-flash analog-to-digital converter.
These devices use a half-flash conversion technique where one
4-bit flash ADC is used to achieve an 8-bit result. The 4-bit
flash ADC contains a sampling capacitor followed by fifteen
comparators that compare the unknown input to a reference
ladder to achieve a 4-bit result. This first flash, i.e., coarse con-
version, provides the 4 MSBs. For a full 8-bit reading to be
realized, a second flash, i.e., a fine conversion, must be per-
formed to provide the 4 LSBs. The 8-bit word is then placed on
the data output bus.
AD7822/AD7825/AD7829
7
REV. A
Figures 2 and 3 below show simplified schematics of the ADC.
When the ADC starts a conversion, the track and hold goes into
hold mode and holds the analog input for 120 ns. This is the
acquisition phase as shown in Figure 2, when Switch 2 is in
Position A. At the point when the track and hold returns to
its track mode, this signal is sampled by the sampling capacitor
as Switch 2 moves into Position B. The first flash occurs at this
instant and is then followed by the second flash. Typically, the
first flash is complete after 100 ns, i.e., at 220 ns, while the end
of the second flash and hence the 8-bit conversion result is
available at 330 ns. As shown in Figure 4, the track-and-hold
returns to track mode after 120 ns, and starts the next acquisi-
tion before the end of the current conversion. Figure 6 shows
the ADC transfer function.
TIMING AND
CONTROL
LOGIC
R1
HOLD
SAMPLING
CAPACITOR
A
B
SW2
R16
R15
R14
R13
T/H 1
OUTPUT
REGISTER
OUTPUT
DRIVERS
V
IN
REFERENCE
D7
D6
D5
D4
D3
D2
D1
D0
DECODE
LOGIC
14
15
13
1
Figure 2. ADC Acquisition Phase
TIMING AND
CONTROL
LOGIC
R1
HOLD
SAMPLING
CAPACITOR
A
B
SW2
R16
R15
R14
R13
T/H 1
OUTPUT
REGISTER
OUTPUT
DRIVERS
V
IN
REFERENCE
D7
D6
D5
D4
D3
D2
D1
D0
DECODE
LOGIC
14
15
13
1
Figure 3. ADC Conversion Phase
HOLD
HOLD
120ns
CONVST
EOC
CS
RD
DB0-DB7
t
2
t
1
t
3
TRACK
TRACK
VALID
DATA
Figure 4. Track-and-Hold Timing
TYPICAL CONNECTION DIAGRAM
Figure 5 shows a typical connection diagram for the AD7822,
AD7825, and AD7829. The AGND and DGND are connected
together at the device for good noise suppression. The parallel
interface is implemented using an 8-bit data bus. The end of
conversion signal (
EOC) idles high, the falling edge of CONVST
initiates a conversion and at the end of conversion the falling
edge of
EOC is used to initiate an Interrupt Service Routine
(ISR) on a microprocessor. (See Parallel interface section for
more details.) V
REF
and V
MID
are connected to voltage source
such as the AD780, while V
DD
is connected to a voltage source
that can vary from 4.5 V to 5.5 V. (See Table I in Analog Input
section.) When V
DD
is first connected, the AD7822, AD7825, and
AD7829 power up in a low current mode, i.e., power-down, with
the default logic level on the
EOC pin on the AD7822 and
AD7825 equal to a low. Ensure the
CONVST line is not floating
when V
DD
is applied, as this could put the AD7822/AD7825/
AD7829 into an unknown state. A rising edge on the
CONVST
pin will cause the AD7829 to fully power up while a rising edge
on the
PD pin will cause the AD7822 and AD7825 to fully power
up. For applications where power consumption is of concern,
the automatic power-down at the end of a conversion should be
used to improve power performance. (See Power-Down Options
section of the data sheet.)
SUPPLY
+4.5V TO +5.5V
10 F
0.1 F
V
DD
V
REF
V
MID
V
IN1
1.25V TO
3.75V INPUT
V
IN2
V
IN4(8)
AGND
DB0-DB7
EOC
RD
CS
CONVST
A0
A1
A2
PD
PARALLEL
INTERFACE
C/ P
AD7822/
AD7825/
AD7829
DGND
2.5V
AD780
Figure 5. Typical Connection Diagram
AD7822/AD7825/AD7829
8
REV. A
ADC TRANSFER FUNCTION
The output coding of the AD7822, AD7825, and AD7829 is
straight binary. The designed code transitions occur at succes-
sive integer LSB values (i.e., 1 LSB, 2 LSBs, etc.). The LSB size
is = V
REF
/256 (V
DD
= 5 V) or the LSB size = (0.8 V
REF
)/256
(V
DD
= 3 V). The ideal transfer characteristic for the AD7822,
AD7825, and AD7829 is shown in Figure 6, below.
11111111
111...110
111...000
10000000
000...111
000...010
00000000
(V
DD
= 5V)
1LSB = V
REF
/256
(V
DD
= 3V)
1LSB = 0.8V
REF
/256
000...001
ADC CODE
1LSB
V
MID
(V
DD
= 5V) V
MID
1.25V
(V
DD
= 3V) V
MID
1V
V
MID
+1.25V1LSB
V
MID
+1V1LSB
ANALOG INPUT VOLTAGE
Figure 6. Transfer Characteristic
ANALOG INPUT
The AD7822 has a single input channel and the AD7825 and
AD7829 have four and eight input channels respectively. Each
input channel has an input span of 2.5 V or 2.0 V, depending on
the supply voltage (V
DD
). This input span is automatically set
up by an on-chip "V
DD
Detector" circuit. 5 V operation of the
ADCs is detected when V
DD
exceeds 4.1 V and 3 V operation is
detected when V
DD
falls below 3.8 V. This circuit also possesses
a degree of glitch rejection; for example, a glitch from 5.5 V to
2.7 V up to 60 ns wide will not trip the V
DD
detector.
The V
MID
pin is used to center this input span anywhere in the
range AGND to V
DD
. If no input voltage is applied to V
MID
, i.e.,
if V
MID
is left unconnected, the default input range is AGND
to 2.0 V (V
DD
= 3 V
±
10%) i.e., centered about 1.0 V, or
AGND to 2.5 V (V
DD
= 5 V
±
10%) i.e., centered about 1.25 V.
If, however, an external V
MID
is applied, the analog input range
will be from V
MID
1.0 V to V
MID
+ 1.0 V (V
DD
= 3 V
±
10%),
or from V
MID
1.25 V to V
MID
+ 1.25 V (V
DD
= 5 V
±
10%).
The range of values of V
MID
that can be applied depends on the
value of V
DD
. For V
DD
= 3 V
±
10%, the range of values that
can be applied to V
MID
is from 1.0 V to V
DD
1.0 V and is 1.25 V
to V
DD
1.25 V when V
DD
= 5 V
±
10%. Table I shows the rel-
evant ranges of V
MID
and the input span for various values of
V
DD
. Figure 7 illustrates the input signal range available with
various values of V
MID
.
Table I.
V
MID
V
MID
Ext
V
MID
Ext
V
DD
Internal
Max
V
IN
Span
Min
V
IN
Span
5.5
1.25
4.25
3.0 to 5.5
1.25
0 to 2.5
5.0
1.25
3.75
2.5 to 5.0
1.25
0 to 2.5
4.5
1.25
3.25
2.0 to 4.5
1.25
0 to 2.5
3.3
1.00
2.3
1.3 to 3.3
1.00
0 to 2.0
3.0
1.00
2.0
1.0 to 3.0
1.00
0 to 2.0
2.7
1.00
1.7
0.7 to 2.7
1.00
0 to 2.0
5V
4V
3V
2V
1V
V
DD
= 5V
INPUT SIGNAL RANGE
FOR VARIOUS V
MID
V
MID
= N/C (1.25V)
V
MID
= 2.5V
V
MID
= 3.75V
3V
2V
1V
V
DD
= 3V
INPUT SIGNAL RANGE
FOR VARIOUS V
MID
V
MID
= N/C (1V)
V
MID
= 1.5V
V
MID
= 2V
Figure 7. Analog Input Span Variation with V
MID
V
MID
may be used to remove offsets in a system by applying the
offset to the V
MID
pin as shown in Figure 8, or it may be used to
accommodate bipolar signals by applying V
MID
to a level-shifting
circuit before V
IN
, as shown in Figure 9. When V
MID
is being
driven by an external source, the source may be directly tied to
the level-shifting circuitry, see Figure 9; however, if the internal
V
MID
, i.e., the default value, is being used as an output, it must
be buffered before applying it to the level-shifting circuitry
as the V
MID
pin has an impedance of approximately 6 k
, see
Figure 10.
V
IN
V
MID
AD7822/
AD7825/
AD7829
V
MID
V
IN
V
MID
Figure 8. Removing Offsets Using V
MID
AD7822/AD7825/AD7829
9
REV. A
V
REF
V
MID
V
IN
R3
R4
R2
R1
V
V
0V
V
IN
0V
2.5V
AD7822/
AD7825/
AD7829
2.5V
Figure 9. Accommodating Bipolar Signals Using
External V
MID
R2
V
REF
V
MID
V
IN
EXTERNAL
2.5V
R3
R4
R1
V
V
0V
V
IN
0V
V
MID
AD7822/
AD7825/
AD7829
Figure 10. Accommodating Bipolar Signals Using
Internal V
MID
NOTE: Although there is a V
REF
pin from which a voltage
reference of 2.5 V may be sourced, or to which an external ref-
erence may be applied, this does not provide an option of
varying the value of the voltage reference. As stated in the
specifications for the AD7822, AD7825, and AD7829, the input
voltage range at this pin is 2.5 V
±
2%.
Analog Input Structure
Figure 11 shows an equivalent circuit of the analog input structure
of the AD7822, AD7825, and the AD7829. The two diodes, D1
and D2, provide ESD protection for the analog inputs. Care
must be taken to ensure that the analog input signal never exceeds
the supply rails by more than 200 mV. This will cause these
diodes to become forward biased and start conducting current into
the substrate. 20 mA is the maximum current these diodes can
conduct without causing irreversible damage to the part. How-
ever, it is worth noting that a small amount of current (1 mA)
being conducted into the substrate due to an over voltage on an
unselected channel, can cause inaccurate conversions on a se-
lected channel. The capacitor C2 in Figure 11 is typically about
4 pF and can be primarily attributed to pin capacitance. The
resistor, R1, is a lumped component made up of the on resis-
tance of several components, including that of the multiplexer
and the track and hold. This resistor is typically about 310
.
The capacitor C1 is the track-and-hold capacitor and has a ca-
pacitance of 0.5 pF. Switch 1 is the track-and-hold switch, while
Switch 2 is that of the sampling capacitor as shown in Figures
2 and 3.
When in track phase, Switch 1 is closed and Switch 2 is in
Position A; when in hold mode, Switch 1 opens while Switch
2 remains in Position A. The track-and-hold remains in hold
mode for 120 ns--see Circuit Description, after which it returns
to track mode and the ADC enters its conversion phase. At this
point Switch 1 opens and Switch 2 moves to Position B. At the
end of the conversion Switch 2 moves back to Position A.
V
IN
C2
4pF
D1
D2
R1
310
SW1
C1
0.5pF A
B
SW2
V
DD
Figure 11. Equivalent Analog Input Circuit
Analog Input Selection
On power-up, the default V
IN
selection is V
IN1
. When returning
to normal operation from power-down, the V
IN
selected will be
the same one that was selected prior to power-down being initiated.
Table II below shows the multiplexer address corresponding to
each analog input from V
IN1
to V
IN4(8)
for the AD7825 or AD7829.
Table II.
A2
A1
A0
Analog Input Selected
0
0
0
V
IN1
0
0
1
V
IN2
0
1
0
V
IN3
0
1
1
V
IN4
1
0
0
V
IN5
1
0
1
V
IN6
1
1
0
V
IN7
1
1
1
V
IN8
Channel selection on the AD7825 and AD7829 is made without
the necessity of a write operation. The address of the next channel
to be converted is latched at the start of the current read operation,
as shown in Figure 12. This allows for improved throughput rates
in "channel hopping" applications.
AD7822/AD7825/AD7829
10
REV. A
CONVST
DB0-DB7
A0-A2
EOC
CS
RD
t
2
t
1
t
3
t
13
VALID
DATA
ADDRESS CHANNEL y
TRACK CHx
TRACK CHx
HOLD CHx
TRACK CHy
HOLD CHy
120ns
Figure 12. Channel Hopping Timing
There is a minimum time delay between the falling edge of
RD
and the next falling edge of the
CONVST signal, t
13
. This is the
minimum acquisition time required of the track-and-hold in
order to maintain 8-bit performance. Figure 13 shows the typical
performance of the AD7825 when channel hopping for various
acquisition times. These results were obtained using an external
reference and internal V
MID
while channel hopping between
V
IN1
and V
IN4
with 0 V on Channel 4 and 0.5 V on Channel 1.
ACQUISITION TIME ns
8
5
500
10
200
ENOB
100
50
40
30
20
15
7.5
7
6.5
6
5.5
8.5
Figure 13. Effective Number of Bits vs. Acquisition Time
for the AD7825
The on-chip track-and-hold can accommodate input frequen-
cies to 10 MHz, making the AD7822, AD7825, and AD7829
ideal for subsampling applications. When the AD7825 is con-
verting a 10 MHz input signal at a sampling rate of 2 MSPS,
the effective number of bits typically remains above seven,
corresponding to a signal-to-noise ratio of 42 dBs as shown
in Figure 14.
INPUT FREQUENCY MHz
50
38
0.2
10
1
SNR dB
3
4
5
6
8
48
46
44
42
40
F
SAMPLE
= 2MHz
Figure 14. SNR vs. Input Frequency on the AD7825
POWER-UP TIMES
The AD7822/AD7825/AD7829 have a 1
µ
s power-up time
when using an external reference and a 25
µ
s power-up time
when using the on-chip reference. When V
DD
is first connected,
the AD7822, AD7825, and AD7829 are in a low current mode
of operation. Ensure that the
CONVST line is not floating when
V
DD
is applied, as this could put the AD7822/AD7825/AD7829
into an unknown state. In order to carry out a conversion the
AD7822, AD7825, and AD7829 must first be powered up. The
AD7829 is powered up by a rising edge on the
CONVST pin
and a conversion is initiated on the falling edge of
CONVST.
Figure 15 shows how to power up the AD7829 when V
DD
is first
connected or after the AD7829 has been powered down using
the
CONVST pin when using either the on-chip, or an external,
reference. When using an external reference, the falling edge of
CONVST may occur before the required power-up time has
elapsed; however, the conversion will not be initiated on the fall-
ing edge of
CONVST but rather at the moment when the part
has completely powered up, i.e., after 1
µ
s. If the falling edge of
CONVST occurs after the required power-up time has elapsed,
then it is upon this falling edge that a conversion is initiated.
When using the on-chip reference, it is necessary to wait the
required power-up time of approximately 25
µ
s before initiating
a conversion; i.e., a falling edge on
CONVST may not occur
before the required power-up time has elapsed, when V
DD
is
first connected or after the AD7829 has been powered down
using the
CONVST pin as shown in Figure 15.
V
DD
t
POWER-UP
1 s
CONVST
V
DD
CONVST
t
POWER-UP
25 s
CONVERSION
INITIATED HERE
CONVERSION
INITIATED HERE
EXTERNAL REFERENCE
ON-CHIP REFERENCE
Figure 15. AD7829 Power-Up Time
AD7822/AD7825/AD7829
11
REV. A
Figure 16 shows how to power up the AD7822 or AD7825 when
V
DD
is first connected or after the ADCs have been powered
down using the
PD pin, or the CONVST pin, with either the
on-chip or an external reference. When the supplies are first
connected or after the part has been powered down by the
PD
pin, only a rising edge on the
PD pin will cause the part to
power up. When the part has been powered down using the
CONVST pin, a rising edge on either the PD pin or the CONVST
pin will power the part up again.
As with the AD7829, when using an external reference with the
AD7822 or AD7825, the falling edge of
CONVST may occur
before the required power-up time has elapsed, however, if this
is the case, the conversion will not be initiated on the falling edge
of
CONVST, but rather at the moment when the part has powered
up completely, i.e., after 1
µ
s. If the falling edge of
CONVST
occurs after the required power-up time has elapsed, it is upon
this falling edge that a conversion is initiated. When using the
on-chip reference it is necessary to wait the required power-
up time of approximately 25
µ
s before initiating a conversion;
i.e., a falling edge on
CONVST may not occur before the
required power-up time has elapsed, when supplies are first
connected to the AD7822 or AD7825, or when the ADCs have
been powered down using the PD pin or the
CONVST pin as
shown in Figure 16.
V
DD
PD
CONVST
t
POWER-UP
1 s
t
POWER-UP
1 s
CONVERSION
INITIATED HERE
CONVERSION
INITIATED HERE
V
DD
PD
CONVST
t
POWER-UP
25 s
t
POWER-UP
25 s
CONVERSION
INITIATED HERE
CONVERSION
INITIATED HERE
EXTERNAL REFERENCE
ON-CHIP REFERENCE
Figure 16. AD7822/AD7825 Power-Up Time
POWER VS. THROUGHPUT
Superior power performance can be achieved by using the auto-
matic power-down (Mode 2) at the end of a conversion--see
Operating Modes section of the data sheet.
Figure 17 shows how the automatic power-down is implemented
using the
CONVST signal to achieve the optimum power per-
formance for the AD7822, AD7825, and AD7829. The duration
of the
CONVST pulse is set to be equal to or less than the
power-up time of the devices--see Operating Modes section. As
the throughput rate is reduced, the device remains in its power-
down state longer and the average power consumption over time
drops accordingly.
t
POWER-UP
1 s
330ns
t
CONVERT
POWER-DOWN
t
CYCLE
10 s @ 100kSPS
CONVST
Figure 17. Automatic Power-Down
For example, if the AD7822 is operated in a continuous sam-
pling mode, with a throughput rate of 100 kSPS and using an
external reference, the power consumption is calculated as fol-
lows. The power dissipation during normal operation is 36 mW,
V
DD
= 3 V. If the power-up time is 1
µ
s and the conversion time
is 330 ns (@ +25
°
C), the AD7822 can be said to dissipate
36 mW for 1.33
µ
s (worst case) during each conversion cycle.
If the throughput rate is 100 kSPS, the cycle time is 10
µ
s
and the average power dissipated during each cycle is (1.33/10)
×
(36 mW) = 4.79 mW.
Figure 18 shows the power vs. throughput rate for automatic
full power-down.
THROUGHPUT kSPS
100
10
0
0
500
100
POWER mW
1
200
300
400
0.1
50
150
250
350
450
Figure 18. AD7822/AD7825/AD7829 Power vs. Throughput
FREQUENCY kHz
0
10
80
dB 40
50
60
70
20
30
0
113
142
170
198
227
255
283
312
340
368
396
425
453
481 510
538
566
595
623
651
680
708
736
765
793
821
850
878
906
935
963
28
57
85
991
2048 POINT FFT
SAMPLING
2MSPS
F
IN
= 200kHz
Figure 19. AD7822/AD7825/AD7829 SNR
AD7822/AD7825/AD7829
12
REV. A
OPERATING MODES
The AD7822, AD7825, and AD7829 have two possible modes
of operation, depending on the state of the
CONVST pulse
approximately 100 ns after the end of a conversion, i.e., upon
the rising edge of the
EOC pulse.
Mode 1 Operation (High Speed Sampling)
When the AD7822, AD7825, and AD7829 are operated in
Mode 1 they are not powered-down between conversions. This
mode of operation allows high throughput rates to be achieved.
Figure 20 shows how this optimum throughput rate is achieved
by bringing
CONVST high before the end of a conversion, i.e.,
before the
EOC pulses low. When operating in this mode a new
conversion should not be initiated until 30 ns after the end of a
read operation. This is to allow the track/hold to acquire the
analog signal to 0.5 LSB accuracy.
Mode 2 Operation (Automatic Power-Down)
When the AD7822, AD7825, and AD7829 are operated in
Mode 2 (see Figure 21), they automatically power down at the
end of a conversion. The
CONVST signal is brought low to ini-
tiate a conversion and is left logic low until after the
EOC goes
high, i.e., approximately 100 ns after the end of the conversion.
The state of the
CONVST signal is sampled at this point (i.e.,
530 ns maximum after
CONVST falling edge) and the AD7822,
AD7825, and AD7829 will power down as long as
CONVST
is low. The ADC is powered up again on the rising edge of the
CONVST signal. Superior power performance can be achieved
in this mode of operation by only powering up the AD7822,
AD7825, and AD7829 to carry out a conversion. The parallel
interface of the AD7822, AD7825, and AD7829 is still fully
operational while the ADCs are powered down. A read may occur
while the part is powered down, and so it does not necessarily
need to be placed within the
EOC pulse as shown in Figure 21.
t
2
t
1
t
3
VALID
DATA
CONVST
EOC
CS
RD
DB0-DB7
TRACK
HOLD
TRACK
HOLD
120ns
Figure 20. Mode 1 Operation
CONVST
EOC
CS
RD
DB0-DB7
t
POWER-UP
t
1
VALID
DATA
POWER
DOWN
HERE
Figure 21. Mode 2 Operation
AD7822/AD7825/AD7829
13
REV. A
PARALLEL INTERFACE
The parallel interface of the AD7822, AD7825, and AD7829 is
eight bits wide. Figure 22 shows a timing diagram illustrating
the operational sequence of the AD7822/AD7825/AD7829
parallel interface. The multiplexer address is latched into the
AD7822/AD7825/AD7829 on the falling edge of the
RD input.
The on-chip track/hold goes into hold mode on the falling
edge of
CONVST and a conversion is also initiated at this
point. When the conversion is complete, the end of conversion
line (
EOC) pulses low to indicate that new data is available in
the output register of the AD7822, AD7825, and AD7829. The
EOC pulse will stay logic low for a maximum time of 110 ns.
However, the
EOC pulse can be reset high by a rising edge of
CONVST
EOC
CS
RD
DB0-DB7
A0-A2
t
1
t
4
t
5
t
6
t
7
t
8
t
3
t
9
t
10
t
11
t
12
t
13
VALID
DATA
NEXT
CHANNEL
ADDRESS
t
2
Figure 22. AD7822/AD7825/AD7829 Parallel Port Timing
RD. This EOC line can be used to drive an edge-triggered inter-
rupt of a microprocessor.
CS and RD going low accesses the
8-bit conversion result. It is possible to tie
CS permanently low
and use only
RD to access the data. In systems where the part is
interfaced to a gate array or ASIC, this
EOC pulse can be applied
to the
CS and RD inputs to latch data out of the AD7822,
AD7825, and AD7829 and into the gate array or ASIC. This
means that the gate array or ASIC does not need any conver-
sion status recognition logic and it also eliminates the logic
required in the gate array or ASIC to generate the read signal
for the AD7822, AD7825, and AD7829.
AD7822/AD7825/AD7829
14
REV. A
MICROPROCESSOR INTERFACING
The parallel port on the AD7822/AD7825/AD7829 allows the
ADCs to be interfaced to a range of many different micro-
controllers. This section explains how to interface the AD7822,
AD7825, and AD7829 with some of the more common micro-
controller parallel interface protocols.
AD7822/AD7825/AD7829 to 8051
Figure 23 below shows a parallel interface between the AD7822,
AD7825, and AD7829 and the 8051 microcontroller. The
EOC
signal on the AD7822, AD7825, and AD7829 provides an inter-
rupt request to the 8051 when a conversion ends and data is
ready. Port 0 of the 8051 may serve as an input or output port,
or as in this case when used together, may be used as a bidirec-
tional low order address and data bus. The address latch enable
output of the 8051 is used to latch the low byte of the address
during accesses to the device, while the high order address byte
is supplied from Port 2. Port 2 latches remain stable when the
AD7822, AD7825, and AD7829 are addressed, as they do not
have to be turned around (set to 1) for data input as is the case for
Port 0.
AD0-AD7
ALE
A8-A15
RD
INT
8051*
LATCH
DECODER
DB0-DB7
RD
EOC
CS
*ADDITIONAL PINS OMITTED FOR CLARITY
AD7822/
AD7825/
AD7829*
Figure 23. Interfacing to the 8051
AD7822/AD7825/AD7829 to PIC16C6x/7x
Figure 24 shows a parallel interface between the AD7822,
AD7825, and AD7829 and the PIC16C64/65/74. The
EOC
signal on the AD7822, AD7825, and AD7829 provides an
interrupt request to the microcontroller when a conversion
begins. Of the PIC16C6x/7x range of microcontrollers only
the PIC16C64/65/74 can provide the option of a parallel slave
port. Port D of the microcontroller will operate as an 8-bit wide
parallel slave port when control bit PSPMODE in the TRISE
register is set. Setting PSPMODE enables the port pin RE0 to
be the
RD output and RE2 to be the CS (chip select) output.
For this functionality, the corresponding data direction bits
of the TRISE register must be configured as outputs (reset to
0). See PIC16/17 Microcontroller User Manual.
PSP0-PSP7
RD
INT
PIC16C6x/7x*
DB0-DB7
RD
EOC
CS
*ADDITIONAL PINS OMITTED FOR CLARITY
CS
AD7822/
AD7825/
AD7829*
Figure 24. Interfacing to the PIC16C6x/7x
AD7822/AD7825/AD7829 to ADSP-21xx
Figure 25 below shows a parallel interface between the AD7822,
AD7825, and AD7829 and the ADSP-21xx series of DSPs. As
before, the
EOC signal on the AD7822, AD7825, and AD7829
provides an interrupt request to the DSP when a conversion
ends.
D7-D0
RD
IRQ
ADSP-21xx*
DB0-DB7
RD
EOC
CS
*ADDITIONAL PINS OMITTED FOR CLARITY
DMS
EN
ADDRESS
DECODE
LOGIC
A13-A0
AD7822/
AD7825/
AD7829*
Figure 25. Interfacing to the ADSP-21xx
AD7822/AD7825/AD7829
15
REV. A
Interfacing Multiplexer Address Inputs
Figure 26 shows a simplified interfacing scheme between the
AD7825/AD7829 and any microprocessor or microcontroller,
which facilitates easy channel selection on the ADCs. The mul-
tiplexer address is latched on the falling edge of the
RD signal,
as outlined in the Parallel Interface section, which allows the use
of the 3 LSBs of the address bus to select the channel address.
As shown in Figure 26, only address bits A3 to A15 are address
decoded allowing A0 to A2 to be changed according to desired
channel selection without affecting chip selection.
AD7825/
AD7829
A0
A1
A2
CS
RD
DB7-DB0
A15-A3
CS
RD
DB0-DB7
A15-A3
A2-A0
ADC I/O ADDRESS
MUX ADDRESS
A/D RESULT
MUX ADDRESS
(CHANNEL SELECTION A0-A2)
LATCHED
MICROPROCESSOR READ CYCLE
ADDRESS
DECODE
SYSTEM BUS
Figure 26. AD7825/AD7829 Simplified Micro Interfacing Scheme
CONVST
RD
CS
EOC
DB7-DB0
AD7822
DSP/
LATCH/ASIC
CONVST
EOC
RD
CS
DB0-DB7
A/D RESULT
t
1
t
4
Figure 27. AD7822 Stand-Alone Operation
The AD7822, being the single channel device, does not have
any multiplexer addressing associated with it and can in fact be
controlled with just one signal, i.e., the
CONVST signal. As
shown in Figure 27 the
RD and CS pins are both tied to the
EOC pin and the resulting signal may be used as an interrupt
request signal (IRQ) on a DSP, as a
WR signal to memory or as
a CLK to a latch or ASIC. The timing for this interface,
as shown in Figure 27, demonstrates how with the
CONVST
signal alone, a conversion may be initiated, data is latched out
and the operating mode of the AD7822 can be selected.
AD7822/AD7825/AD7829
16
REV. A
20-Lead Plastic DIP
(N-20)
20
1
10
11
1.060 (26.90)
0.925 (23.50)
0.280 (7.11)
0.240 (6.10)
PIN 1
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.060 (1.52)
0.015 (0.38)
0.160 (4.06)
0.115 (2.93)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
20-Lead Small Outline Package
(R-20)
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC
0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0291 (0.74)
0.0098 (0.25)
x 45°
20
11
10
1
0.5118 (13.00)
0.4961 (12.60)
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
20-Lead Thin Shrink Small Outline Package
(RU-20)
20
11
10
1
0.260 (6.60)
0.252 (6.40)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8°
0°
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
AD7822/AD7825/AD7829
17
REV. A
24-Lead Plastic DIP
(N-24)
24
1
12
13
0.280 (7.11)
0.240 (6.10)
PIN 1
1.275 (32.30)
1.125 (28.60)
0.150
(3.81)
MIN
0.200 (5.05)
0.125 (3.18)
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.070 (1.77)
0.045 (1.15)
0.100 (2.54)
BSC
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
24-Lead Small Outline Package
(R-24)
24
13
12
1
0.6141 (15.60)
0.5985 (15.20)
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC
0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0291 (0.74)
0.0098 (0.25)
x 45°
24-Lead Thin Shrink Small Outline Package
(RU-24)
24
13
12
1
0.311 (7.90)
0.303 (7.70)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8°
0°
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
AD7822/AD7825/AD7829
18
REV. A
28-Lead Plastic DIP
(N-28)
28
1
14
15
1.565 (39.70)
1.380 (35.10)
PIN 1
0.580 (14.73)
0.485 (12.32)
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.200 (5.05)
0.125 (3.18)
0.150
(3.81)
MIN
SEATING
PLANE
0.250
(6.35)
MAX
0.100
(2.54)
BSC
0.070
(1.77)
MAX
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.125 (3.18)
0.625 (15.87)
0.600 (15.24)
28-Lead Small Outline Package
(R-28)
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC
0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0291 (0.74)
0.0098 (0.25)
x 45°
0.7125 (18.10)
0.6969 (17.70)
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
28
15
14
1
28-Lead Thin Shrink Small Outline Package
(RU-28)
28
15
14
1
0.386 (9.80)
0.378 (9.60)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8°
0°
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C3203a012/99
PRINTED IN U.S.A.
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