Äîêóìåíòàöèÿ è îïèñàíèÿ www.docs.chipfind.ru

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

AD7751*

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 2000

Energy Metering IC

With On-Chip Fault Detection

FEATURES
High Accuracy, Supports 50 Hz/60 Hz IEC 687/1036
Less than 0.1% Error Over a Dynamic Range of 500 to 1
Supplies

Average Real Power on the Frequency

Outputs F1 and F2

High-Frequency Output CF Is Intended for Calibration

and Supplies

Instantaneous Real Power

Continuous Monitoring of the Phase and Neutral

Current Allows Fault Detection in Two-Wire
Distribution Systems

AD7751 Uses the Larger of the Two Currents (Phase

or Neutral) to Bill--Even During a Fault Condition

Two Logic Outputs (FAULT and REVP) Can be Used to

Indicate a Potential Miswiring or Fault Condition

Direct Drive for Electromechanical Counters and

Two-Phase Stepper Motors (F1 and F2)

A PGA in the Current Channel Allows the Use of Small

Values of

Shunt and Burden Resistance

Proprietary ADCs and DSP Provide High Accuracy Over

Large Variations in Environmental Conditions and Time

On-Chip Power Supply Monitoring
On-Chip Creep Protection (No Load Threshold)
On-Chip Reference 2.5 V 8% (30 ppm/ C Typical)

with External Overdrive Capability

Single 5 V Supply, Low Power (15 mW Typical)
Low-Cost CMOS Process

GENERAL DESCRIPTION

The AD7751 is a high-accuracy fault-tolerant electrical energy
measurement IC that is intended for use with 2-wire distribution
systems. The part specifications surpass the accuracy require-
ments as quoted in the IEC1036 standard.

FUNCTIONAL BLOCK DIAGRAM

AC/

HPF

AGND

DGND

PHASE
CORRECTION

...

110101

...

SIGNAL

PROCESSING

BLOCK

PGA

1, 2, 8, 16

POWER

SUPPLY MONITOR

AD7751

...

11011001

...

2.5V

REFERENCE

PGA

1, 2, 8, 16

ADC

...

110101

...

B>A

A>B

A<>B

ADC

FAULT

MULTIPLIER

LPF

DIGITAL-TO-FREQUENCY

CONVERTER

G0 G1

V1A

V1N

V2P

V2N

V1B

CLKOUT

CLKIN

REF

IN/OUT

RESET

F1 F2

REVP

SCF S0 S1

*US Patent 5,745,323; 5,760,617; 5,862,069; 5,872,469.

The only analog circuitry used in the AD7751 is in the ADCs
and reference circuit. All other signal processing (e.g., multipli-
cation and filtering) is carried out in the digital domain. This
approach provides superior stability and accuracy over extremes
in environmental conditions and over time.

The AD7751 incorporates a novel fault detection scheme that
warns of fault conditions and allows the AD7751 to continue
accurate billing during a fault event. The AD7751 does this
by continuously monitoring both the phase and neutral (re-
turn) currents. A fault is indicated when these currents differ by
more than 12.5%. Billing is continued using the larger of the
two currents.

The AD7751 supplies average real power information on the
low-frequency outputs F1 and F2. These logic outputs may be
used to directly drive an electromechanical counter or interface
to an MCU. The CF logic output gives instantaneous real power
information. This output is intended to be used for calibration
purposes.

The AD7751 includes a power supply monitoring circuit on the
AV

supply pin. The AD7751 will remain in a reset condition

until the supply voltage on AV

reaches 4 V. If the supply falls

below 4 V, the AD7751 will also be reset and no pulses will be
issued on F1, F2, and CF.

Internal phase matching circuitry ensures that the voltage and
current channels are matched whether the HPF in Channel 1 is
on or off. The AD7751 also has anticreep protection.

The AD7751 is available in 24-lead DIP and SSOP packages.

REV. A

AD7751SPECIFICATIONS

1, 2

(AV

= DV

= 5 V 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN =

3.58 MHz, T

MIN

to T

MAX

= 40 C to +85 C)

Parameter

A Version

B Version

Unit

Test Conditions/Comments

ACCURACY

Measurement Error

on Channels 1 and 2

One Channel with Full-Scale Signal (

±660 mV)

Gain = 1

0.1

% Reading typ

Over a Dynamic Range 500 to 1

Gain = 2

0.1

% Reading typ

Over a Dynamic Range 500 to 1

Gain = 8

0.1

% Reading typ

Over a Dynamic Range 500 to 1

Gain = 16

0.1

% Reading typ

Over a Dynamic Range 500 to 1

Phase Error

Between Channels

Line Frequency = 45 Hz to 55 Hz

V1 Phase Lead 37

(PF = 0.8 Capacitive)

±0.1

Degrees(

°) max AC/DC = 0 and AC/DC = 1

V1 Phase Lag 60

(PF = 0.5 Inductive)

±0.1

Degrees(

°) max AC/DC = 0 and AC/DC = 1

AC Power Supply Rejection

AC/

DC = 1, S0 = S1 = 1, G0 = G1 = 0

Output Frequency Variation (CF)

0.2

% Reading typ

V1 = 100 mV rms, V2 = 100 mV rms @ 50 Hz
Ripple on AV

of 200 mV rms @ 100 Hz

DC Power Supply Rejection

AC/

DC = 1, S0 = S1 = 1, G0 = G1 = 0

Output Frequency Variation (CF)

±0.3

% Reading typ

V1 = 100 mV rms, V2 = 100 mV rms,
AV

= DV

= 5 V

± 250 mV

FAULT DETECTION

1, 4

See Fault Detection Section

Fault Detection Threshold

Inactive i/p <> Active i/p

12.5

% typ

(V1A or V1B Active)

Input Swap Threshold

Inactive i/p > Active i/p

% of Active typ

(V1A or V1B Active)

Accuracy Fault Mode Operation

V1A Active, V1B = AGND

0.1

% Reading typ

Over a Dynamic Range 500 to 1

V1B Active, V1A = AGND

0.1

% Reading typ

Over a Dynamic Range 500 to 1

Fault Detection Delay

Second typ

Swap Delay

Second typ

ANALOG INPUTS

See Analog Inputs Section

Maximum Signal Levels

± 1

V max

V1A, V1B

V1N, V2N and V2P to AGND

Input Impedance (DC)

390

min

CLKIN = 3.58 MHz

Bandwidth

kHz typ

CLKIN/256, CLKIN = 3.58 MHz

ADC Offset Error

±20

mV max

See Terminology and Performance Graphs

Gain Error

± 4

% Ideal typ

External 2.5 V Reference, Gain = 1,
V1 = V2 = 660 mV dc

Gain Error Match

±0.2

% Ideal typ

External 2.5 V Reference

REFERENCE INPUT

REF

IN/OUT

Input Voltage Range

2.7

V max

2.5 V + 8%

2.3

V min

2.5 V 8%

Input Impedance

3.2

min

Input Capacitance

pF max

ON-CHIP REFERENCE

Nominal 2.5 V

Reference Error

±200

mV max

Temperature Coefficient

±30

ppm/

°C typ

±60

ppm/

°C max

CLKIN

Note All Specifications for CLKIN of 3.58 MHz

Input Clock Frequency

MHz max

MHz min

LOGIC INPUTS

SCF, S0, S1, AC/

DC,

RESET, G0 and G1

Input High Voltage, V

INH

2.4

V min

= 5 V

± 5%

Input Low Voltage, V

INL

0.8

V max

= 5 V

± 5%

Input Current, I

± 3

µA max

Typically 10 nA, V

= 0 V to DV

Input Capacitance, C

pF max

REV. A

AD7751

Parameter

A Version

B Version

Unit

Test Conditions/Comments

LOGIC OUTPUTS

F1 and F2

Output High Voltage, V

SOURCE

= 10 mA

4.5

V min

= 5 V

Output Low Voltage, V

SINK

= 10 mA

0.5

V max

= 5 V

CF, FAULT, and REVP

Output High Voltage, V

SOURCE

= 5 mA

V min

= 5 V

Output Low Voltage, V

SINK

= 5 mA

0.5

V max

= 5 V

POWER SUPPLY

For Specified Performance

4.75

V min

5 V 5%

5.25

V max

5 V + 5%

4.75

V min

5 V 5%

5.25

V max

5 V + 5%

mA max

Typically 2 mA

2.5

mA max

Typically 1.5 mA

NOTES

See Terminology section for explanation of specifications.

See plots in Typical Performance Characteristics graphs.

See Fault Detection section of data sheet for explanation of fault detection functionality.

Sample tested during initial release and after any redesign or process change that may affect this parameter.

Specifications subject to change without notice.

TIMING CHARACTERISTICS

1, 2

Parameter

A, B Versions

Unit

Test Conditions/Comments

275

F1 and F2 Pulsewidth (Logic Low)

See Table III

sec

Output Pulse Period. See Transfer Function Section

1/2 t

sec

Time Between F1 Falling Edge and F2 Falling Edge

CF Pulsewidth (Logic High)

See Table IV

sec

CF Pulse Period. See Transfer Function Section

CLKIN/4

sec

Minimum Time Between F1 and F2 Pulse

NOTES

Sample tested during initial release and after any redesign or process change that may affect this parameter.

See Figure 1.

The pulsewidths of F1, F2 and CF are not fixed for higher output frequencies. See Frequency Outputs section.

Specifications subject to change without notice.

Figure 1. Timing Diagram for Frequency Outputs

(AV

= DV

= 5 V 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.58 MHz,

MIN

to T

MAX

= 40 C to +85 C)

ORDERING GUIDE

Package

Model

Package Description

Option

AD7751AAN

Plastic DIP

N-24

AD7751AARS

Shrink Small Outline Package

RS-24

AD7751ABRS

Shrink Small Outline Package

RS-24

EVAL-AD7751EB

AD7751 Evaluation Board

AD7751AAN-REF

AD7751 Reference Design
PCB (See AN-563)

REV. A

AD7751

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7751 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

= 25

°C unless otherwise noted)

to AGND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V

to DGND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V

to AV

. . . . . . . . . . . . . . . . . . . . . . 0.3 V to +0.3 V

Analog Input Voltage to AGND

V1A, V1B, V1N, V2P, and V2N . . . . . . . . . . 6 V to +6 V

Reference Input Voltage to AGND . . 0.3 V to AV

+ 0.3 V

Digital Input Voltage to DGND . . . . 0.3 V to DV

+ 0.3 V

Digital Output Voltage to DGND . . . 0.3 V to DV

+ 0.3 V

Operating Temperature Range

Industrial (A, B Versions) . . . . . . . . . . . . . 40

°C to +85°C

Storage Temperature Range . . . . . . . . . . . . 65

°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150

°C

24-Lead Plastic DIP, Power Dissipation . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105

°C/W

Lead Temperature, (Soldering 10 sec) . . . . . . . . . . . 260

°C

24-Lead SSOP, Power Dissipation . . . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 112

°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . 215

°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220

°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.

TERMINOLOGY

MEASUREMENT ERROR

The error associated with the energy measurement made by the
AD7751 is defined by the following formula:

Percentage Error =

Energy Registered by the AD7751 True Energy

True Energy

× 100%

PHASE ERROR BETWEEN CHANNELS

The HPF (High-Pass Filter) in Channel 1 has a phase lead
response. To offset this phase response and equalize the phase
response between channels a phase correction network is also
placed in Channel 1. The phase correction network matches the
phase to within

±0.1° over a range of 45 Hz to 65 Hz and ±0.2°

over a range 40 Hz to 1 kHz (see Figures 10 and 11).

ADC OFFSET ERROR

This refers to the dc offset associated with the analog inputs to
the ADCs. It means that with the analog inputs connected to
AGND the ADCs still see an analog input signal of 1 mV to
10 mV. However, when the HPF is switched on the offset is
removed from the current channel and the power calculation is
not affected by this offset.

POWER SUPPLY REJECTION

This quantifies the AD7751 measurement error as a percentage
of reading when the power supplies are varied.

For the ac PSR measurement a reading at nominal supplies
(5 V) is taken. A 200 mV rms/100 Hz signal is then introduced
onto the supplies and a second reading obtained under the same
input signal levels. Any error introduced is expressed as a per-
centage of reading--see Measurement Error definition.

For the dc PSR measurement a reading at nominal supplies
(5 V) is taken. The supplies are then varied

±5% and a second

reading is obtained with the same input signal levels. Any error
introduced is again expressed as a percentage of reading.

GAIN ERROR

The gain error of the AD7751 is defined as the difference between
the measured output frequency (minus the offset) and the ideal
output frequency. It is measured with a gain of 1 in Channel
V1A. The difference is expressed as a percentage of the ideal
frequency. The ideal frequency is obtained from the transfer
function--see Transfer Function section.

GAIN ERROR MATCH

The gain error match is defined as the gain error (minus the
offset) obtained when switching between a gain of 1 and a gain
of 2, 8, or 16. It is expressed as a percentage of the output
frequency obtained under a gain of 1. This gives the gain
error observed when the gain selection is changed from
1 to 2, 8, or 16.

REV. A

AD7751

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

Description

Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the AD7751.
The supply voltage should be maintained at 5 V

± 5% for specified operation. This pin should be

decoupled with a 10

µF capacitor in parallel with a ceramic 100 nF capacitor.

AC/

High-Pass Filter Select. This logic input is used to enable the HPF in Channel 1 (the current
channel). A Logic 1 on this pin enables the HPF. The associated phase response of this filter has
been internally compensated over a frequency range of 45 Hz to 1 kHz. The HPF filter should be
enabled in energy metering applications.

Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the AD7751.
The supply should be maintained at 5 V

± 5% for specified operation. Every effort should be made

to minimize power supply ripple and noise at this pin by the use of proper decoupling. This pin
should be decoupled to AGND with a 10

µF capacitor in parallel with a ceramic 100 nF capacitor.

4, 5

V1A, V1B

Analog Inputs for Channel 1 (Current Channel). These inputs are fully differential voltage inputs
with a maximum signal level of

±660 mV with respect to Pin V1N for specified operation. The

maximum signal level at these pins is

±1 V with respect to AGND. Both inputs have internal ESD

protection circuitry and an overvoltage of

±6 V can also be sustained on these inputs without risk of

permanent damage.

V1N

Negative Input Pin for Differential Voltage Inputs V1A and V1B. The maximum signal level at this
pin is

±1 V with respect to AGND. The input has internal ESD protection circuitry and in addition,

an overvoltage of

±6 V can be sustained without risk of permanent damage. This input should be

directly connected to the burden resistor and held at a fixed potential, i.e., AGND. See Analog
Input section.

7, 8

V2N, V2P

Negative and Positive Inputs for Channel 2 (Voltage Channel). These inputs provide a fully differ-
ential input pair. The maximum differential input voltage is

±660 mV for specified operation. The

maximum signal level at these pins is

±1 V with respect to AGND. Both inputs have internal ESD

protection circuitry and an overvoltage of

±6 V can also be sustained on these inputs without risk of

permanent damage.

RESET

Reset Pin for the AD7751. A logic low on this pin will hold the ADCs and digital circuitry in a reset
condition. Bringing this pin logic low will clear the AD7751 internal registers.

REF

IN/OUT

Provides Access to the On-Chip Voltage Reference. The on-chip reference has a nominal value of
2.5 V

± 8% and a typical temperature coefficient of 30 ppm/°C. An external reference source may also

be connected at this pin. In either case, this pin should be decoupled to AGND with a 1

µF ceramic

capacitor and 100 nF ceramic capacitor.

AGND

Provides the Ground Reference for the Analog Circuitry in the AD7751, i.e., ADCs and Reference.
This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the
ground reference for all analog circuitry, e.g., antialiasing filters, current and voltage transduc-
ers, etc. For good noise suppression the analog ground plane should only be connected to the digital
ground plane at one point. A star ground configuration will help to keep noisy digital return currents
away from the analog circuits.

SCF

Select Calibration Frequency. This logic input is used to select the frequency on the calibration
output CF. Table IV shows how the calibration frequencies are selected.

13, 14

S1, S0

These logic inputs are used to select one of four possible frequencies for the digital-to-frequency
conversion. This offers the designer greater flexibility when designing the energy meter. See Select-
ing a Frequency for an Energy Meter Application section.

15, 16

G1, G0

These logic inputs are used to select one of four possible gains for the analog inputs V1A and V1B.
The possible gains are 1, 2, 8 and 16. See Analog Input section.

CLKIN

An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can
be connected across CLKIN and CLKOUT to provide a clock source for the AD7751. The clock
frequency for specified operation is 3.579545 MHz. Crystal load capacitors of between 22 pF
and 33 pF (ceramic) should be used with the gate oscillator circuit.

CLKOUT

A crystal can be connected across this pin and CLKIN as described above to provide a clock source
for the AD7751. The CLKOUT pin can drive one CMOS load when an external clock is supplied
at CLKIN or by gate oscillator circuit.

FAULT

This logic output will go active high when a fault condition occurs. A fault is defined as a condition
under which the signals on V1A and V1B differ by more than 12.5%. The logic output will be reset
to zero when a fault condition is no longer detected. See Fault Detection section.

Part Number AD7751