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AD7714*

FUNCTIONAL BLOCK DIAGRAM

FEATURES
Charge Balancing ADC

24 Bits No Missing Codes
0.0015% Nonlinearity

Five-Channel Programmable Gain Front End

Gains from 1 to 128
Can Be Configured as Three Fully Differential
Inputs or Five Pseudo-Differential Inputs

Three-Wire Serial Interface

SPITM, QSPITM, MICROWIRETM and DSP Compatible

3 V (AD7714-3) or 5 V (AD7714-5) Operation
Low Noise (<150 nV rms)
Low Current (350

A typ) with Power-Down (5 A typ)

AD7714Y Grade:

+2.7 V to 3.3 V or +4.75 V to +5.25 V Operation
0.0010% Linearity Error
40 C to +105 C Temperature Range
Schmitt Trigger on SCLK and DIN
Low Current (226

A typ) with Power-Down (4 A typ)

Lower Power Dissipation than Standard AD7714
Available in 24-Lead TSSOP Package

Low-Pass Filter with Programmable Filter Cutoffs
Ability to Read/Write Calibration Coefficients

APPLICATIONS
Portable Industrial Instruments
Portable Weigh Scales
Loop-Powered Systems
Pressure Transducers

3 V/5 V, CMOS, 500

Signal Conditioning ADC

GENERAL DESCRIPTION

The AD7714 is a complete analog front end for low-frequency
measurement applications. The device accepts low level signals
directly from a transducer and outputs a serial digital word. It
employs a sigma-delta conversion technique to realize up to 24
bits of no missing codes performance. The input signal is applied
to a proprietary programmable gain front end based around an
analog modulator. The modulator output is processed by an on-
chip digital filter. The first notch of this digital filter can be
programmed via the on-chip control register allowing adjust-
ment of the filter cutoff and settling time.

The part features three differential analog inputs (which can also
be configured as five pseudo-differential analog inputs) as well as a
differential reference input. It operates from a single supply (+3 V
or +5 V). The AD7714 thus performs all signal conditioning and
conversion for a system consisting of up to five channels.

The AD7714 is ideal for use in smart, microcontroller- or DSP-
based systems. It features a serial interface that can be configured

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

for three-wire operation. Gain settings, signal polarity and channel
selection can be configured in software using the serial port. The
AD7714 provides self-calibration, system calibration and back-
ground calibration options and also allows the user to read and
write the on-chip calibration registers.

CMOS construction ensures very low power dissipation, and the
power-down mode reduces the standby power consumption to
15

W typ. The part is available in a 24-pin, 0.3 inch-wide, plastic

dual-in-line package (DIP); a 24-lead small outline (SOIC)
package, a 28-lead shrink small outline package (SSOP) and a
24-lead thin shrink small outline package (TSSOP).

PRODUCT HIGHLIGHTS

1. The AD7714Y offers the following features in addition to the

standard AD7714: wider temperature range, Schmitt trigger
on SCLK and DIN, operation down to 2.7 V, lower power
consumption, better linearity, and availability in 24-lead
TSSOP package.

2. The AD7714 consumes less than 500

A (f

CLK IN

= 1 MHz)

or 1 mA (f

CLK IN

= 2.5 MHz) in total supply current, making

it ideal for use in loop-powered systems.

3. The programmable gain channels allow the AD7714 to ac-

cept input signals directly from a strain gage or transducer
removing a considerable amount of signal conditioning.

4. The AD7714 is ideal for microcontroller or DSP processor

applications with a three-wire serial interface reducing the num-
ber of interconnect lines and reducing the number of opto-
couplers required in isolated systems. The part contains
on-chip registers that allow control over filter cutoff, input gain,
channel selection, signal polarity and calibration modes.

5. The part features excellent static performance specifications

with 24-bit no missing codes,

0.0015% accuracy and low

rms noise (140 nV). Endpoint errors and the effects of tem-
perature drift are eliminated by on-chip self-calibration,
which removes zero-scale and full-scale errors.

*Protected by U.S. Patent No. 5,134,401.
See page 39 for data sheet index.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 1998

REF IN(+)

MCLK IN

MCLK OUT

A = 1128

CHARGE

BALANCING

A/D CONVERTER

REF IN()

AD7714

BUFFER

AGND

BUFFER

SERIAL INTERFACE

AGND

DGND

REGISTER BANK

MODULATOR

SYNC

STANDBY

DIGITAL FILTER

PGA

1 A

AIN1
AIN2
AIN3
AIN4
AIN5
AIN6

SWITCHING

MATRIX

CLOCK

GENERATION

SCLK

DIN

DOUT

POL

DRDY

RESET

Parameter

A Versions

Units

Conditions/Comments

STATIC PERFORMANCE

No Missing Codes

Bits min

Guaranteed by Design. Bipolar Mode. For Filter Notches

60 Hz

Bits min

For Filter Notch = 100 Hz

Bits min

For Filter Notch = 250 Hz

Bits min

For Filter Notch = 500 Hz

Bits min

For Filter Notch = 1 kHz

Output Noise

See Tables I to IV

Depends on Filter Cutoffs and Selected Gain

Integral Nonlinearity

0.0015

% of FSR max

Filter Notches

60 Hz

Unipolar Offset Error

See Note 2

Unipolar Offset Drift

0.5

C typ

For Gains of 1, 2, 4

0.3

C typ

For Gains of 8, 16, 32, 64, 128

Bipolar Zero Error

See Note 2

Bipolar Zero Drift

0.5

C typ

For Gains of 1, 2, 4

0.3

C typ

For Gains of 8, 16, 32, 64, 128

Positive Full-Scale Error

See Note 2

Full-Scale Drift

3, 5

0.5

C typ

For Gains of 1, 2, 4

0.3

C typ

For Gains of 8, 16, 32, 64, 128

Gain Error

See Note 2

Gain Drift

3, 7

0.5

ppm of FSR/

C typ

Bipolar Negative Full-Scale Error

0.0015

% of FSR max

Typically

0.0004%

Bipolar Negative Full-Scale Drift

C typ

For Gains of 1, 2, 4

0.6

C typ

For Gains of 8, 16, 32, 64, 128

ANALOG INPUTS/REFERENCE INPUTS

Specifications for AIN and REF IN Unless Noted

Input Common-Mode Rejection (CMR)

dB min

At DC. Typically 102 dB

Normal-Mode 50 Hz Rejection

100

dB min

For Filter Notches of 10

, 25

, 50 Hz,

0.02

NOTCH

Normal-Mode 60 Hz Rejection

100

dB min

For Filter Notches of 10

, 30

, 60 Hz,

0.02

NOTCH

Common-Mode 50 Hz Rejection

150

dB min

For Filter Notches of 10

, 25

, 50 Hz,

0.02

NOTCH

Common-Mode 60 Hz Rejection

150

dB min

For Filter Notches of 10

, 30

, 60 Hz,

0.02

NOTCH

Common-Mode Voltage Range

AGND to AV

V min to V max

AIN for BUFFER = 0 and REF IN

Absolute AIN/REF IN Voltage

AGND 30 mV

V min

AIN for BUFFER = 0 and REF IN

+ 30 mV

V max

Absolute/Common-Mode AIN Voltage

AGND + 50 mV

V min

BUFFER = 1. A Version

1.5 V

V max

AIN Input Current

nA max

A Version

AIN Sampling Capacitance

pF max

AIN Differential Voltage Range

0 to +V

REF

/GAIN

nom

Unipolar Input Range (B/U Bit of Filter High Register = 1)

REF

/GAIN

nom

Bipolar Input Range (B/U Bit of Filter High Register = 0)

AIN Input Sampling Rate, f

GAIN

CLK IN

/64

For Gains of 1, 2, 4

CLK IN

For Gains of 8, 16, 32, 64, 128

REF IN(+) REF IN() Voltage

+2.5

V nom

1% for Specified Performance. Functional with Lower V

REF

REF IN Input Sampling Rate, f

CLK IN

/64

LOGIC INPUTS

Input Current

A max

All Inputs Except MCLK IN

INL

, Input Low Voltage

0.8

V max

= +5 V

INL

, Input Low Voltage

0.4

V max

= +3.3 V

INH

, Input High Voltage

2.4

V min

= +5 V

INH

, Input High Voltage

2.0

V min

= +3.3 V

MCLK IN Only

INL

, Input Low Voltage

0.8

V max

= +5 V

INL

, Input Low Voltage

0.4

V max

= +3.3 V

INH

, Input High Voltage

3.5

V min

= +5 V

INH

, Input High Voltage

2.5

V min

= +3.3 V

LOGIC OUTPUTS (Including MCLK OUT)

, Output Low Voltage

0.4

V max

SINK

= 800

A Except for MCLK OUT.

= +5 V

, Output Low Voltage

0.4

V max

SINK

= 100

A Except for MCLK OUT.

= +3.3 V

, Output High Voltage

4.0

V min

SOURCE

= 200

A Except for MCLK OUT.

= +5 V

, Output High Voltage

0.6 V

V min

SOURCE

= 100

A Except for MCLK OUT.

= +3.3 V

Floating State Leakage Current

A max

Floating State Output Capacitance

pF typ

Data Output Coding

Binary

Unipolar Mode

Offset Binary

Bipolar Mode

NOTES

Temperature range is as follows: A Versions: 40

C to +85

A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables I to IV. This applies after calibration at the temperature of interest.

Recalibration at any temperature will remove these drift errors.

Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges.

Full-Scale Drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.

Gain Error does not include Zero-Scale Errors. It is calculated as Full-Scale Error--Unipolar Offset Error for unipolar ranges and Full-Scale Error--Bipolar Zero Error for

bipolar ranges.

AD7714-5SPECIFICATIONS

(AV

= +5 V, DV

= +3.3 V or +5 V, REF IN(+) = +2.5 V; REF IN() = AGND;

CLK IN

= 2.4576 MHz unless otherwise noted. All specifications T

MIN

to T

MAX

unless otherwise noted.)

REV. C

Parameter

A Versions

Units

Conditions/Comments

STATIC PERFORMANCE

No Missing Codes

Bits min

Guaranteed by Design. Bipolar Mode. For Filter Notches

60 Hz

Bits min

For Filter Notch = 100 Hz

Bits min

For Filter Notch = 250 Hz

Bits min

For Filter Notch = 500 Hz

Bits min

For Filter Notch = 1 kHz

Output Noise

See Tables I to IV

Depends on Filter Cutoffs and Selected Gain

Integral Nonlinearity

0.0015

% of FSR max

Filter Notches

60 Hz

Unipolar Offset Error

See Note 2

Unipolar Offset Drift

0.4

C typ

For Gains of 1, 2, 4

0.1

C typ

For Gains of 8, 16, 32, 64, 128

Bipolar Zero Error

See Note 2

Bipolar Zero Drift

0.4

C typ

For Gains of 1, 2, 4

0.1

C typ

For Gains of 8, 16, 32, 64, 128

Positive Full-Scale Error

See Note 2

Full-Scale Drift

3, 5

0.4

C typ

For Gains of 1, 2, 4

0.1

C typ

For Gains of 8, 16, 32, 64, 128

Gain Error

See Note 2

Gain Drift

3, 7

0.2

ppm of FSR/

C typ

Bipolar Negative Full-Scale Error

0.003

% of FSR max

Typically

0.0004%

Bipolar Negative Full-Scale Drift

C typ

For Gains of 1, 2, 4

0.6

C typ

For Gains of 8, 16, 32, 64, 128

ANALOG INPUTS/REFERENCE INPUTS

Specifications for AIN and REF IN Unless Noted

Input Common-Mode Rejection (CMR)

dB min

At DC. Typically 102 dB.

Normal-Mode 50 Hz Rejection

100

dB min

For Filter Notches of 10 Hz, 25 Hz, 50 Hz,

0.02

NOTCH

Normal-Mode 60 Hz Rejection

100

dB min

For Filter Notches of 10 Hz, 30 Hz, 60 Hz,

0.02

NOTCH

Common-Mode 50 Hz Rejection

150

dB min

For Filter Notches of 10 Hz, 25 Hz, 50 Hz,

0.02

NOTCH

Common-Mode 60 Hz Rejection

150

dB min

For Filter Notches of 10 Hz, 30 Hz, 60 Hz,

0.02

NOTCH

Common-Mode Voltage Range

AGND to AV

V min to V max

AIN for BUFFER = 0 and REF IN

Absolute AIN/REF IN Voltage

AGND 30 mV

V min

AIN for BUFFER = 0 and REF IN

+ 30 mV

V max

Absolute/Common-Mode AIN Voltage

AGND + 50 mV

V min

BUFFER = 1

1.5 V

V max

AIN Input Current

nA max

AIN Sampling Capacitance

pF max

AIN Differential Voltage Range

0 to +V

REF

/GAIN

nom

Unipolar Input Range (B/U Bit of Filter High Register = 1)

REF

/GAIN

nom

Bipolar Input Range (B/U Bit of Filter High Register = 0)

AIN Input Sampling Rate, f

GAIN

CLK IN

/64

For Gains of 1, 2, 4

CLK IN

For Gains of 8, 16, 32, 64, 128

REF IN(+) REF IN() Voltage

+1.25

V nom

1% for Specified Performance. Part Functions with

Lower V

REF

REF IN Input Sampling Rate, f

CLK IN

/64

LOGIC INPUTS

Input Current

A max

All Inputs Except MCLK IN

INL

, Input Low Voltage

0.4

V max

INH

, Input High Voltage

2.0

V min

MCLK IN Only

INL

, Input Low Voltage

0.4

V max

INH

, Input High Voltage

2.5

V min

LOGIC OUTPUTS (Including MCLK OUT)

, Output Low Voltage

0.4

V max

SINK

= 100

A Except for MCLK OUT

, Output High Voltage

0.6

V min

SOURCE

= 100

A Except for MCLK OUT

Floating State Leakage Current

A max

Floating State Output Capacitance

pF typ

Data Output Coding

Binary

Unipolar Mode

Offset Binary

Bipolar Mode

NOTES

Gain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero-scale calibrations only were performed as is the case with

background calibration.

These numbers are guaranteed by design and/or characterization.

The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed.

The input voltage range on the analog inputs is given here with respect to the voltage on the respective negative input of its differential or pseudo-differential pair. See Table VII

for which inputs form differential pairs.

REF

= REF IN(+) REF IN().

These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load.

Sample tested at +25

C to ensure compliance.

See Burnout Current section.

AD7714-3SPECIFICATIONS

(AV

= +3.3 V, DV

= +3.3 V, REF IN(+) = +1.25 V; REF IN() = AGND;

CLK IN

= 2.4576 MHz unless otherwise noted. All specifications T

MIN

to T

MAX

unless otherwise noted.)

AD7714

REV. C

AD7714SPECIFICATIONS

Parameter

A Versions

Units

Conditions/Comments

TRANSDUCER BURNOUT

Current

A nom

Initial Tolerance

% typ

Drift

0.1

C typ

SYSTEM CALIBRATION

Positive Full-Scale Calibration Limit

(1.05

REF

)/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

Negative Full-Scale Calibration Limit

(1.05

REF

)/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

Offset Calibration Limit

(1.05

REF

)/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

Input Span

0.8

REF

/GAIN

V min

GAIN Is the Selected PGA Gain (Between 1 and 128)

(2.1

REF

)/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

POWER REQUIREMENTS

Power Supply Voltages

Voltage (AD7714-3)

+3 to +3.6

For Specified Performance

Voltage (AD7714-5)

+4.75 to +5.25

For Specified Performance

Voltage

+3 to +5.25

For Specified Performance

Power Supply Currents

Current

= 3.3 V or 5 V. BST Bit of Filter High Register = 0

0.27

mA max

Typically 0.2 mA. BUFFER = 0 V. f

CLK IN

= 1 MHz or 2.4576 MHz

0.6

mA max

Typically 0.4 mA. BUFFER = DV

. f

CLK IN

= 1 MHz or 2.4576 MHz

= 3.3 V or 5 V. BST Bit of Filter High Register = 1

0.5

mA max

Typically 0.3 mA. BUFFER = 0 V. f

CLK IN

= 2.4576 MHz

1.1

mA max

Typically 0.8 mA. BUFFER = DV

. f

CLK IN

= 2.4576 MHz

Current

Digital I/Ps = 0 V or DV

DD.

External MCLK IN

0.23

mA max

Typically 0.15 mA. DV

= 3.3 V. f

CLK IN

= 1 MHz

0.4

mA max

Typically 0.3 mA. DV

= 5 V. f

CLK IN

= 1 MHz

0.5

mA max

Typically 0.4 mA. DV

= 3.3 V. f

CLK IN

= 2.4576 MHz

0.8

mA max

Typically 0.6 mA. DV

= 5 V. f

CLK IN

= 2.4576 MHz

Power Supply Rejection

See Note 20

dB typ

Normal-Mode Power Dissipation

= DV

= +3.3 V. Digital I/Ps = 0 V or DV

. External MCLK IN

1.65

mW max

Typically 1.25 mW. BUFFER = 0 V. f

CLK IN

= 1 MHz. BST Bit = 0

2.75

mW max

Typically 1.8 mW. BUFFER = +3.3 V. f

CLK IN

= 1 MHz. BST Bit = 0

2.55

mW max

Typically 2 mW. BUFFER = 0 V. f

CLK IN

= 2.4576 MHz. BST Bit = 0

3.65

mW max

Typically 2.6 mW. BUFFER = +3.3 V. f

CLK IN

= 2.4576 MHz. BST Bit = 0

Normal-Mode Power Dissipation

= DV

= +5 V. Digital I/Ps = 0 V or DV

. External MCLK IN

3.35

mW max

Typically 2.5 mW. BUFFER = 0 V. f

CLK IN

= 1 MHz. BST Bit = 0

mW max

Typically 3.5 mW. BUFFER = +5 V. f

CLK IN

= 1 MHz. BST Bit = 0

5.35

mW max

Typically 4 mW. BUFFER = 0 V. f

CLK IN

= 2.4576 MHz. BST Bit = 0

mW max

Typically 5 mW. BUFFER = +5 V. f

CLK IN

= 2.4576 MHz. BST Bit = 0

Standby (Power-Down) Current

A max

External MCLK IN = 0 V or DV

. Typically 20

A. V

= +5 V

Standby (Power-Down) Current

A max

External MCLK IN = 0 V or DV

. Typically 5

A. V

= +3.3 V

NOTES

After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, then the device outputs all 0s.

These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV

+ 30 mV or go more negative than AGND 30 mV. The

offset calibration limit applies to both the unipolar zero point and the bipolar zero point.

For higher gains (

8) at f

CLK IN

= 2.4576 MHz, the BST bit of the Filter High Register must be set to 1. For other conditions, it can be set to 0.

When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DV

current and power dissipation will vary depending on the crystal

or resonator type (see Clocking and Oscillator Circuit section).

Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 5 Hz, 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz will exceed 120 dB

with filter notches of 6 Hz, 10 Hz, 30 Hz or 60 Hz.

PSRR depends on gain. For Gain of 1 : 70 dB typ: For Gain of 2 : 75 dB typ; For Gain of 4 : 80 dB typ; For Gains of 8 to 128 : 85 dB typ.

If the external master clock continues to run in standby mode, the standby current increases to 150

A typical with 5 V supplies and 75

A typical with 3.3 V supplies. When

using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation
depends on the crystal or resonator type (see Standby Mode section).

Specifications subject to change without notice.

(AV

= + 3.3 V to +5 V, DV

= +3.3 V to +5 V, REF IN(+) = +1.25 V (AD7714-3) or +2.5 V

(AD7714-5); REF IN() = AGND; MCLK IN = 1 MHz to 2.4576 MHz unless otherwise noted. All specifications T

MIN

to T

MAX

unless otherwise noted.)

REV. C

Parameter

Y Versions

Units

Conditions/Comments

STATIC PERFORMANCE

No Missing Codes

Bits min

Guaranteed by Design. For Filter Notches

60 Hz

Bits min

For Filter Notch = 100 Hz

Bits min

For Filter Notch = 250 Hz

Bits min

For Filter Notch = 500 Hz

Bits min

For Filter Notch = 1 kHz

Output Noise

See Tables I to IV

Depends on Filter Cutoffs and Selected Gain

Integral Nonlinearity

0.001

% of FSR max

Filter Notches

60 Hz.

Unipolar Offset Error

See Note 2

Unipolar Offset Drift

0.4

C typ

For Gains of 1, 2, 4

0.1

C typ

For Gains of 8, 16, 32, 64, 128

Bipolar Zero Error

See Note 2

Bipolar Zero Drift

0.4

C typ

For Gains of 1, 2, 4

0.1

C typ

For Gains of 8, 16, 32, 64, 128

Positive Full-Scale Error

See Note 2

Full-Scale Drift

3, 5

0.4

C typ

For Gains of 1, 2, 4

0.1

C typ

For Gains of 8, 16, 32, 64, 128

Gain Error

See Note 2

Gain Drift

3, 7

0.2

ppm of FSR/

C typ

Bipolar Negative Full-Scale Error

0.0015

% of FSR max

= 5 V. Typically

0.0004%

0.003

% of FSR max

= 3 V. Typically

0.0004%

Bipolar Negative Full-Scale Drift

C typ

For Gains of 1 to 4

0.6

C typ

For Gains of 8 to 128

ANALOG INPUTS/REFERENCE INPUTS

Specifications for AIN and REF IN Unless Noted

Input Common-Mode Rejection (CMR)

dB min

At DC. Typically 102 dB.

Normal-Mode 50 Hz Rejection

100

dB min

For Filter Notches of 10 Hz, 25 Hz, 50 Hz,

0.02

NOTCH

Normal-Mode 60 Hz Rejection

100

dB min

For Filter Notches of 10 Hz, 30 Hz, 60 Hz,

0.02

NOTCH

Common-Mode 50 Hz Rejection

150

dB min

For Filter Notches of 10 Hz, 25 Hz, 50 Hz,

0.02

NOTCH

Common-Mode 60 Hz Rejection

150

dB min

For Filter Notches of 10 Hz, 30 Hz, 60 Hz,

0.02

NOTCH

Absolute/Common-Mode REF IN Voltage

AGND to AV

V min to V max

Absolute/Common-Mode AIN Voltage

AGND 30 mV

V min

BUF Bit of Setup Register = 0

+ 30 mV

V max

Absolute/Common-Mode AIN Voltage

8, 9

AGND + 50 mV

V min

BUF Bit of Setup Register = 1

1.5 V

V max

AIN DC Input Current

nA max

AIN Sampling Capacitance

pF max

AIN Differential Voltage Range

0 to +V

REF

/GAIN

nom

Unipolar Input Range (B/U Bit of Filter High Register = 1)

REF

/GAIN

nom

Bipolar Input Range (B/U Bit of Filter High Register = 0)

AIN Input Sampling Rate, f

GAIN

CLK IN

/64

For Gains of 1 to 4

CLK IN

For Gains of 8 to 128

Reference Input Range

REF IN(+) REF IN() Voltage

1/1.75

V min/max

= 2.7 V to 3.3 V. V

REF

= 1.25

1% for Specified Performance

REF IN(+) REF IN() Voltage

1/3.5

V min/max

= 4.75 V to 5.25 V. V

REF

= 2.5

1% for Specified Performance

REF IN Input Sampling Rate, f

CLK IN

/64

LOGIC INPUTS

Input Current

A max

All Inputs Except MCLK IN

INL

, Input Low Voltage

0.8

V max

= 5 V

0.4

V max

= 3 V

INH

, Input High Voltage

2.4

V min

= 5 V

V min

= 3 V

SCLK & DIN Only (Schmitt Triggered Input)

= 5 V NOMINAL

T+

1.4/3

V min/V max

0.8/1.4

V min/V max

T+

0.4/0.8

V min/V max

SCLK & DIN Only (Schmitt Triggered Input)

= 3 V NOMINAL

T+

1/2.5

V min/V max

0.4/1.1

V min/V max

T+

0.375/0.8

V min/V max

MCLK In Only

= 5 V NOMINAL

INL

, Input Low Voltage

0.8

V max

INH

, Input High Voltage

3.5

V min

MCLK In Only

= 3 V NOMINAL

INL

, Input Low Voltage

0.4

V max

INH

, Input High Voltage

2.5

V min

LOGIC OUTPUTS (Including MCLK OUT)

, Output Low Voltage

0.4

V max

SINK

= 800

A with DV

= 5 V. Except for MCLK OUT

, Output Low Voltage

0.4

V max

SINK

= 100

A with DV

= 3 V. Except for MCLK OUT

, Output High Voltage

V min

SOURCE

= 200

A with DV

= 5 V. Except for MCLK OUT

AD7714YSPECIFICATIONS

(AV

= DV

= +2.7 V to +3.3 V or 4.75 V to 5.25 V, REF IN(+) = +1.25 V; with AV

= 3 V

and +2.5 V with AV

= 5 V; REF IN() = AGND; MCLK IN = 2.4576 MHz unless otherwise noted. All specifications T

MIN

to T

MAX

unless otherwise noted.)

AD7714

REV. C

Part Number AD7714