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FUNCTIONAL BLOCK DIAGRAM

AD7713

AIN2(+)

AIN2()

AIN3

STANDBY

CLOCK

GENERATION

SERIAL INTERFACE

CONTROL

REGISTER

OUTPUT

REGISTER

CHARGING BALANCING A/D

CONVERTER

AUTO-ZEROED

MODULATOR

DIGITAL

FILTER

AGND

DGND

MODE SDATA SCLK

MCLK
OUT

MCLK
IN

AIN1(+)

AIN1()

REF

IN()

REF

IN(+)

1µA

A = 1 128

200µA

BIAS

SYNC

DRDY

TFS

RFS

RTD2

PGA

200µA

RTD1

INPUT

SCALING

M
U
X

FEATURES
Charge Balancing ADC

24 Bits No Missing Codes

0.0015% Nonlinearity

Three-Channel Programmable Gain Front End

Gains from 1 to 128
Two Differential Inputs
One Single Ended High Voltage Input

Low-Pass Filter with Programmable Filter Cutoffs
Ability to Read/Write Calibration Coefficients
Bidirectional Microcontroller Serial Interface
Single Supply Operation
Low Power (3.5 mW typ) with Power-Down Mode

(150 W typ)

APPLICATIONS
Loop Powered (Smart) Transmitters
RTD Transducers
Process Control
Portable Industrial Instruments

MOS

Loop-Powered Signal Conditioning ADC

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

AD7713*

One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700

Fax: 617/326-8703

CMOS construction ensures low power dissipation and a hard-
ware programmable power-down mode reduces the standby
power consumption to only 150

W typical. The part is avail-

able in a 24-pin, 0.3 inch wide, plastic and hermetic dual-in-line
package (DIP) as well as a 24-lead small outline (SOIC) package.

PRODUCT HIGHLIGHTS

1. The AD7713 consumes less than 1 mA in total supply cur-

rent, making it ideal for use in loop-powered systems.

2. The two programmable gain channels allow the AD7713 to

accept input signals directly from a transducer removing a
considerable amount of signal conditioning. To maximize the
flexibility of the part, the high level analog input accepts
4

REF

signals. On-chip current sources provide excitation

for three-wire and four-wire RTD configurations.

3. No Missing Codes ensures true, usable, 24-bit dynamic

range coupled with excellent

0.0015% accuracy. The effects

of temperature drift are eliminated by on-chip self-calibration,
which removes zero-scale and full-scale errors.

4. The AD7713 is ideal for microcontroller or DSP processor

applications with an on-chip control register which allows
control over filter cutoff, input gain, signal polarity and cali-
bration modes. The AD7713 allows the user to read and
write the on-chip calibration registers.

GENERAL DESCRIPTION

The AD7713 is a complete analog front end for low frequency
measurement applications. The device accepts low level signals
directly from a transducer or high level signals (4

REF

) and

outputs a serial digital word. It employs a sigma-delta con-
version technique to realize up to 24 bits of no missing codes
performance. The input signal is applied to a proprietary pro-
grammable gain front end based around an analog modulator.
The modulator output is processed by an on-chip digital filter.
The first notch of this digital filter can be programmed via the
on-chip control register allowing adjustment of the filter cutoff
and settling time.

The part features two differential analog inputs and one single-
ended high level analog input as well as a differential reference
input. It can be operated from a single supply (AV

and DV

at +5 V). The part provides two current sources which can be
used to provide excitation in three-wire and four-wire RTD con-
figurations. The AD7713 thus performs all signal conditioning
and conversion for a single, dual or three-channel system.

The AD7713 is ideal for use in smart, microcontroller-based
systems. Gain settings, signal polarity and RTD current control
can be configured in software using the bidirectional serial port.
The AD7713 contains self-calibration, system calibration and
background calibration options and also allows the user to read
and to write the on-chip calibration registers.

*Protected by U.S. Patent No. 5,134,401.

Parameter

A, S Versions

Units

Conditions/Comments

STATIC PERFORMANCE

No Missing Codes

Bits min

Guaranteed by Design. For Filter Notches

12 Hz

Bits min

For Filter Notch = 20 Hz

Bits min

For Filter Notch = 50 Hz

Bits min

For Filter Notch = 100 Hz

Bits min

For Filter Notch = 200 Hz

Output Noise

See Tables I & II

Depends on Filter Cutoffs and Selected Gain

Integral Nonlinearity

0.0015

% of FSR max

Filter Notches

12 Hz; Typically

0.0003%

Positive Full-Scale Error

2, 3

See Note 4

Full-Scale Drift

C typ

For Gains of 1, 2

0.3

C typ

For Gains of 4, 8, 16, 32, 64, 128

Unipolar Offset Error

See Note 4

Unipolar Offset Drift

0.5

C typ

For Gains of 1, 2

0.25

C typ

For Gains of 4, 8, 16, 32, 64, 128

Bipolar Zero Error

See Note 4

Bipolar Zero Drift

0.5

C typ

For Gains of 1, 2

0.25

C typ

For Gains of 4, 8, 16, 32, 64, 128

Gain Drift

ppm/

C typ

Bipolar Negative Full-Scale Error

0.004

% of FSR max

Typically

0.0006%

Bipolar Negative Full-Scale Drift

C typ

For Gains of 1, 2

0.3

C typ

For Gains of 4, 8, 16, 32, 64, 128

ANALOG INPUTS

Input Sampling Rate, f

See Table III

Normal-Mode 50 Hz Rejection

100

dB min

For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz,

0.02

NOTCH

Normal-Mode 60 Hz Rejection

100

dB min

For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz,

0.02

NOTCH

AIN1, AIN2

Input Voltage Range

For Normal Operation. Depends on Gain Selected.

0 to +V

REF

V max

Unipolar Input Range (B/U Bit of Control Register = 1)

REF

V max

Bipolar Input Range (B/U Bit of Control Register = 0)

Common-Mode Rejection (CMR)

100

dB min

At DC

Common-Mode 50 Hz Rejection

150

dB min

For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz,

0.02

NOTCH

Common-Mode 60 Hz Rejection

150

dB min

For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz,

0.02

NOTCH

Common-Mode Voltage Range

AGND to AV

V min to V max

DC Input Leakage Current @ +25

pA max

MIN

to T

MAX

nA max

Sampling Capacitance

pF max

AIN3

Input Voltage Range

0 to + 4

REF

V max

For Normal Operation. Depends on Gain Selected

Gain Error

0.05

% typ

Additional Error Contributed by Resistor Attenuator

Gain Drift

ppm/

C typ

Additional Drift Contributed by Resistor Attenuator

Offset Error

mV max

Additional Error Contributed by Resistor Attenuator

Input Impedance

min

NOTES

Temperature range is as follows: A Version, 40

C to +85

C; S Version, 55

C to +125

Applies after calibration at the temperature of interest.

Positive full-scale error applies to both unipolar and bipolar input ranges.

These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20

V typical after self-calibration

or background calibration.

Recalibration at any temperature or use of the background calibration mode will remove these drift errors.

These numbers are guaranteed by design and/or characterization.

The AIN1 and AIN2 analog inputs presents a very high impedance dynamic load which varies with clock frequency and input sample rate. The maximum

recommended source resistance depends on the selected gain.

The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1() and AIN2 () inputs. The input

voltage range on the AIN3 input is with respect to AGND. The absolute voltage on the AIN1 and AIN2 inputs should not go more positive than A V

+ 30 mV or

more negative than AGND 30 mV.

REF

= REF IN(+) REF IN().

This common-mode voltage range is allowed provided that the input voltage on AIN(+) and AIN() does not exceed A V

+ 30 mV and AGND 30 mV.

This error can be removed using the system calibration capabilities of the AD7713. This error is not removed by the AD7713's self-calibration feature. The offset

drift on the AIN3 input is four times the value given in the Static Performance section.

REV. C

(AV

= +5 V

5%; DV

= +5 V 5%; REF IN(+) = +2.5 V; REF IN() = AGND;

MCLK IN = 2 MHz unless otherwise noted. All specifications T

MIN

to T

MAX

unless otherwise noted.)

AD7713SPECIFICATIONS

Parameter

A, S Versions

Units

Conditions/Comments

REFERENCE INPUT

REF IN(+) REF IN() Voltage

+2.5 to AV

/1.8

V min to V max

For Specified Performance. Part Is Functional with Lower
V

REF

Voltages

Input Sampling Rate, f

CLK IN

/512

Normal-Mode 50 Hz Rejection

100

dB min

For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz,

0.02

NOTCH

Normal-Mode 60 Hz Rejection

100

dB min

For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz,

0.02

NOTCH

Common-Mode Rejection (CMR)

100

dB min

At DC

Common-Mode 50 Hz Rejection

150

dB min

For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz,

0.02

NOTCH

Common-Mode 60 Hz Rejection

150

dB min

For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz,

0.02

NOTCH

Common-Mode Voltage Range

AGND to AV

V min to V max

DC Input Leakage Current @ +25

pA max

MIN

to T

MAX

nA max

LOGIC INPUTS

Input Current

A max

All Inputs Except MCLK IN

INL

, Input Low Voltage

0.8

V max

INH

, Input High Voltage

2.0

V min

MCLK IN Only

INL

, Input Low Voltage

0.8

V max

INH

, Input High Voltage

3.5

V min

LOGIC OUTPUTS

, Output Low Voltage

0.4

V max

SINK

= 1.6 mA

, Output High Voltage

4.0

V min

SOURCE

= 100

Floating State Leakage Current

A max

Floating State Output Capacitance

pF typ

TRANSDUCER BURN-OUT

Current

A nom

Initial Tolerance @ +25

% typ

Drift

0.1

C typ

RTD EXCITATION CURRENTS

(RTD1, RTD2)

Output Current

200

A nom

Initial Tolerance @ +25

% max

Drift

ppm/

C typ

Initial Matching @ +25

% max

Matching Between RTD1 and RTD2 Currents

Drift Matching

ppm/

C typ

Matching Between RTD1 and RTD2 Current Drift

Line Regulation (AV

)

200

nA/V max

= +5 V

Load Regulation

200

nA/V max

SYSTEM CALIBRATION

AIN1, AIN2

Positive Full-Scale Calibration Limit

+(1.05

REF

)/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

Negative Full-Scale Calibration Limit

(1.05

REF

)/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

Offset Calibration Limit

14, 15

(1.05

REF

)/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

Input Span

+0.8

REF

/GAIN

V min

GAIN Is the Selected PGA Gain (Between 1 and 128)

+(2.1

REF

)/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

AIN3

Positive Full-Scale Calibration Limit

+(4.2

REF

)/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

Offset Calibration Limit

0 to V

REF

/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

Input Span

+3.2

REF

/GAIN

V min

GAIN Is the Selected PGA Gain (Between 1 and 128)

+(4.2

REF

)/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

NOTES

Guaranteed by design, not production tested.

After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will

output all 0s.

These calibration and span limits apply provided the absolute voltage on the AIN1 and AIN2 analog inputs does not exceed AV

+ 30 mV or go more negative

than AGND 30 mV.

The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.

AD7713

REV. C

Parameter

A, S Versions

Units

Conditions/Comments

POWER REQUIREMENTS

Power Supply Voltages

Voltage

+5 to +10

V nom

5% for Specified Performance

Voltage

V nom

5% for Specified Performance

Power Supply Currents

Current

0.6

mA max

= +5 V

0.7

mA max

= +10 V

Current

0.5

mA max

CLK IN

= 1 MHz. Digital Inputs 0 V to DV

mA max

CLK IN

= 2 MHz. Digital Inputs 0 V to DV

Power Supply Rejection

Rejection w.r.t. AGND

(AV

and DV

)

See Note 18

dB typ

Power Dissipation

Normal Mode

5.5

mW max

= DV

= +5 V, f

CLK IN

= 1 MHz; Typically 3.5 mW

Standby (Power-Down) Mode

300

W max

= DV

= +5 V, Typically 150

NOTES

The

5% tolerance on the DV

input is allowed provided that DV

does not exceed AV

by more than 0.3 V.

Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz

will exceed 120 dB with filter notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz or 60 Hz.

PSRR depends on gain: gain of 1 = 70 dB typ; gain of 2 = 75 dB typ; gain of 4 = 80 dB typ; gains of 8 to 128 = 85 dB typ.

Specifications subject to change without notice.

AD7713SPECIFICATIONS

REV. C

TIMING CHARACTERISTICS

1, 2

Limit at T

MIN

, T

MAX

Parameter

(A, S Versions)

Units

Conditions/Comments

CLK IN

3, 4

400

kHz min

Master Clock Frequency: Crystal Oscillator or

MHz max

Externally Supplied for Specified Performance

CLK IN LO

0.4

CLK IN

ns min

Master Clock Input Low Time; t

CLK IN

= 1/f

CLK IN

CLK IN HI

0.4

CLK IN

ns min

Master Clock Input High Time

ns max

Digital Output Rise Time; Typically 20 ns

ns max

Digital Output Fall Time; Typically 20 ns

1000

ns min

SYNC

Pulse Width

Self-Clocking Mode

ns min

DRDY

to RFS Setup Time

ns min

DRDY

to RFS Hold Time

CLK IN

ns min

A0 to RFS Setup Time

ns min

A0 to RFS Hold Time

CLK IN

+ 20

ns max

RFS

Low to SCLK Falling Edge

CLK IN

+20

ns max

Data Access Time (RFS Low to Data Valid)

CLK IN

ns min

SCLK Falling Edge to Data Valid Delay

CLK IN

+ 30

ns max

CLK IN

ns nom

SCLK High Pulse Width

CLK IN

ns nom

SCLK Low Pulse Width

ns min

A0 to TFS Setup Time

ns min

A0 to TFS Hold Time

CLK IN

+ 20

ns max

TFS

to SCLK Falling Edge Delay Time

CLK IN

ns min

TFS

to SCLK Falling Edge Hold Time

ns min

Data Valid to SCLK Setup Time

ns min

Data Valid to SCLK Hold Time

(DV

= +5 V

5%; AV

= +5 V or +10 V

5%; AGND = DGND = 0 V; f

CLKIN

=2 MHz;

Input Logic 0 = 0 V, Logic 1 = DV

unless otherwise noted.)

REV. C

AD7713

Limit at T

MIN

, T

MAX

Parameter

(A, S Versions)

Units

Conditions/Comments

External-Clocking Mode

SCLK

CLK IN

MHz max

Serial Clock Input Frequency

ns min

DRDY

to RFS Setup Time

ns min

DRDY

to RFS Hold Time

CLK IN

ns min

A0 to RFS Setup Time

ns min

A0 to RFS Hold Time

CLK IN

ns max

Data Access Time (RFS Low to Data Valid)

ns min

SCLK Falling Edge to Data Valid Delay

CLK IN

+ 20

ns max

CLK IN

ns min

SCLK High Pulse Width

CLK IN

ns min

SCLK Low Pulse Width

CLK IN

+ 10

ns max

SCLK Falling Edge to DRDY High

ns min

SCLK to Data Valid Hold Time

CLK IN

+ 10

ns max

ns min

RFS

/TFS to SCLK Falling Edge Hold Time

CLK IN

/2 + 50

ns max

RFS

to Data Valid Hold Time

ns min

A0 to TFS Setup Time

ns min

A0 to TFS Hold Time

CLK IN

ns min

SCLK Falling Edge to TFS Hold Time

CLK IN

SCLK High

ns min

Data Valid to SCLK Setup Time

ns min

Data Valid to SCLK Hold Time

NOTES

Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

See Figures 10 to 13.

CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7713 is not in STANDBY mode. If no clock is present in this case, the

device can draw higher current than specified and possibly become uncalibrated.

The AD7713 is production tested with f

CLK IN

at 2 MHz. It is guaranteed by characterization to operate at 400 kHz.

Specified using 10% and 90% points on waveform of interest.

These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number

is then extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are
the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.

TO OUTPUT

PIN

+2.1V

1.6mA

200µA

100pF

Figure 1. Load Circuit for Access Time and Bus Relinquish Time

Part Number AD7713