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FUNCTIONAL BLOCK DIAGRAM

CLOCK

GENERATION

SERIAL INTERFACE

OUTPUT

REGISTER

CHARGE-BALANCING A/D

CONVERTER

AUTO-ZEROED

MODULATOR

DIGITAL

FILTER

AD7712

AGND DGND

MODE SDATA SCLK

MCLK
OUT

MCLK
IN

AIN1()

REF

IN ()

REF

IN (+)

SYNC

4.5 A

A = 1 128

DRDY

TFS

RFS

REF OUT

BIAS

VOLTAGE

ATTENUATION

AIN2

STANDBY

CONTROL

REGISTER

2.5V REFERENCE

U
X

AIN1(+)

PGA

FEATURES
Charge Balancing ADC

24 Bits No Missing Codes

0.0015% Nonlinearity

High Level and Low Level Analog Input Channels
Programmable Gain for Both Inputs

Gains from 1 to 128
Differential Input for Low Level Channel

Low-Pass Filter with Programmable Filter Cutoffs
Ability to Read/Write Calibration Coefficients
Bidirectional Microcontroller Serial Interface
Internal/External Reference Option
Single or Dual Supply Operation
Low Power (25 mW typ) with Power-Down Mode

(100 W typ)

APPLICATIONS
Process Control
Smart Transmitters
Portable Industrial Instruments

MOS

Signal Conditioning ADC

REV. E

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

GENERAL DESCRIPTION

The AD7712 is a complete analog front end for low frequency
measurement applications. The device has two analog input
channels and accepts either low level signals directly from a
transducer or high level (

REF

) signals and outputs a serial

digital word. It employs a sigma-delta conversion technique to
realize up to 24 bits of no missing codes performance. The low
level input signal is applied to a proprietary programmable gain
front end based around an analog modulator. The high level
analog input is attenuated before being applied to the same
modulator. The modulator output is processed by an on-chip
digital filter. The first notch of this digital filter can be pro-
grammed via the on-chip control register allowing adjustment of
the filter cutoff and settling time.

Normally, one of the channels will be used as the main channel
with the second channel used as an auxiliary input to periodi-
cally measure a second voltage. The part can be operated from a
single supply (by tying the V

pin to AGND) provided that the

input signals on the low level analog input are more positive
than 30 mV. By taking the V

pin negative, the part can con-

vert signals down to V

REF

on this low level input. This low level

input, as well as the reference input, features differential input
capability.

The AD7712 is ideal for use in smart, microcontroller-based
systems. Input channel selection, gain settings and signal polar-
ity can be configured in software using the bidirectional serial

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 1998

port. The AD7712 also contains self-calibration, system calibra-
tion and background calibration options and also allows the user
to read and to write the on-chip calibration registers.

CMOS construction ensures low power dissipation and a hard-
ware programmable power-down mode reduces the standby
power consumption to only 100

W typical. The part is avail-

able in a 24-lead, 0.3 inch wide, plastic and hermetic dual-in-
line package (DIP) as well as a 24-lead small outline (SOIC)
package.

PRODUCT HIGHLIGHTS

1. The low level analog input channel allows the AD7712 to

accept input signals directly from a strain gage or transducer,
removing a considerable amount of signal conditioning. To
maximize the flexibility of the part, the high level analog
input accepts signals of

REF

/GAIN.

2. The AD7712 is ideal for microcontroller or DSP processor

applications with an on-chip control register that allows
control over filter cutoff, input gain, channel selection, signal
polarity and calibration modes.

3. The AD7712 allows the user to read and to write the on-chip

calibration registers. This means that the microcontroller has
much greater control over the calibration procedure.

4. No Missing Codes ensures true, usable, 23-bit dynamic

range coupled with excellent

0.0015% accuracy. The effects

of temperature drift are eliminated by on-chip self-calibration,
which removes zero-scale and full-scale errors.

AD7712*

*Protected by U.S. Patent No. 5,134,401.

Parameter

A, S Versions

Units

Conditions/Comments

STATIC PERFORMANCE

No Missing Codes

Bits min

Guaranteed by Design. For Filter Notches

60 Hz

Bits min

For Filter Notch = 100 Hz

Bits min

For Filter Notch = 250 Hz

Bits min

For Filter Notch = 500 Hz

Bits min

For Filter Notch = 1 kHz

Output Noise

See Tables I & II

Depends on Filter Cutoffs and Selected Gain

Integral Nonlinearity @ +25

0.0015

% FSR max

Filter Notches

60 Hz

MIN

to T

MAX

0.003

% FSR max

Typically

0.0003%

Positive Full-Scale Error

2, 3

See Note 4

Excluding Reference

Full-Scale Drift

C typ

Excluding Reference. For Gains of 1, 2

0.3

C typ

Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128

Unipolar Offset Error

See Note 4

Unipolar Offset Drift

0.5

C typ

For Gains of 1, 2

0.25

C typ

For Gains of 4, 8, 16, 32, 64, 128

Bipolar Zero Error

See Note 4

Bipolar Zero Drift

0.5

C typ

For Gains of 1, 2

0.25

C typ

For Gains of 4, 8, 16, 32, 64, 128

Gain Drift

ppm/

C typ

Bipolar Negative Full-Scale Error

@ +25

0.003

% FSR max

Excluding Reference

MIN

to T

MAX

0.006

% FSR max

Typically

0.0006%

Bipolar Negative Full-Scale Drift

C typ

Excluding Reference. For Gains of 1, 2

0.3

C typ

Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128

ANALOG INPUTS/REFERENCE INPUTS

Normal-Mode 50 Hz Rejection

100

dB min

For Filter Notches of 10 Hz, 25 Hz, 50 Hz,

0.02

NOTCH

Normal-Mode 60 Hz Rejection

100

dB min

For Filter Notches of 10 Hz, 30 Hz, 60 Hz,

0.02

NOTCH

AIN1/REF IN

DC Input Leakage Current

@ +25

pA max

MIN

to T

MAX

nA max

Sampling Capacitance

pF max

Common-Mode Rejection (CMR)

100

dB min

At DC

Common-Mode 50 Hz Rejection

150

dB min

For Filter Notches of 10 Hz, 25 Hz, 50 Hz,

0.02

NOTCH

Common-Mode 60 Hz Rejection

150

dB min

For Filter Notches of 10 Hz, 30 Hz, 60 Hz,

0.02

NOTCH

Common-Mode Voltage Range

to AV

V min to V max

Analog Inputs

Input Sampling Rate, f

See Table III

AIN1 Input Voltage Range

For Normal Operation. Depends on Gain Selected

0 to +V

REF

V max

Unipolar Input Range (B/U Bit of Control Register = 1)

REF

V max

Bipolar Input Range (B/U Bit of Control Register = 0)

AIN2 Input Voltage Range

For Normal Operation. Depends on Gain Selected

0 to + 4

REF

V max

Unipolar Input Range (B/U Bit of Control Register = 1)

REF

V max

Bipolar Input Range (B/U Bit of Control Register = 0)

AIN2 DC Input Impedance

AIN2 Gain Error

0.05

% typ

Additional Error Contributed by Resistor Attenuator

AIN2 Gain Drift

ppm/

C typ

Additional Drift Contributed by Resistor Attenuator

AIN2 Offset Error

mV max

Additional Error Contributed by Resistor Attenuator

AIN2 Offset Drift

C typ

Reference Inputs

REF IN(+) REF IN() Voltage

+2.5 to +5

V min to V max

For Specified Performance. Part Is Functional with
Lower V

REF

Voltages

Input Sampling Rate, f

CLK IN

/256

NOTES

Temperature range is as follows: A Version, 40

C to +85

C; S Version 55

C to +125

C. See also Note 18.

Applies after calibration at the temperature of interest.

Positive full-scale error applies to both unipolar and bipolar input ranges.

These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20

V typical after self-calibration

or background calibration.

Recalibration at any temperature or use of the background calibration mode will remove these drift errors.

These numbers are guaranteed by design and/or characterization.

This common-mode voltage range is allowed provided that the input voltage on AIN1(+) and AIN1() does not exceed AV

+ 30 mV and V

30 mV.

The AIN1 analog input presents a very high impedance dynamic load which varies with clock frequency and input sample rate. The maximum recommended

source resistance depends on the selected gain (see Tables IV and V).

The analog input voltage range on the AIN1(+) input is given here with respect to the voltage on the AIN1() input. The input voltage range on the AIN2

input is with respect to AGND. The absolute voltage on the AIN1 input should not go more positive than AV

+ 30 mV or more negative than V

30 mV.

REF

= REF IN(+) REF IN().

This error can be removed using the system calibration capabilities of the AD7712. This error is not removed by the AD7712's self-calibration features. The offset

drift on the AIN2 input is 4 times the value given in the STATIC PERFORMANCE section.

The reference input voltage range may be restricted by the input voltage range requirement on the V

BIAS

input.

REV. E

(AV

= +5 V 5%; DV

= +5 V 5%; V

= 0 V or 5 V 5%; REF IN(+) = +2.5 V;

REF IN() = AGND; MCLK IN = 10 MHz unless otherwise stated. All specifications T

MIN

to T

MAX

unless otherwise noted.)

AD7712SPECIFICATIONS

Parameter

A, S Versions

Units

Conditions/Comments

REFERENCE OUTPUT

Output Voltage

2.5

V nom

Initial Tolerance

% max

Drift

ppm/

C typ

Output Noise

V typ

pk-pk Noise; 0.1 Hz to 10 Hz Bandwidth

Line Regulation (AV

)

mV/V max

Load Regulation

1.5

mV/mA max

Maximum Load Current 1 mA

External Current

mA max

BIAS

INPUT

Input Voltage Range

0.85

REF

See V

BIAS

Input Section

or AV

3.5

V max

Whichever Is Smaller; +5 V/5 V or +10 V/0 V
Nominal AV

or AV

2.1

V max

Whichever Is Smaller; +5 V/0 V Nominal AV

+ 0.85

REF

See V

BIAS

Input Section

or V

+ 3

V min

Whichever Is Greater; +5 V/5 V or +10 V/0 V
Nominal AV

or V

+ 2.1

V min

Whichever Is Greater; +5 V/0 V Nominal AV

BIAS

Rejection

65 to 85

dB typ

Increasing with Gain

LOGIC INPUTS

Input Current

A max

All Inputs except MCLK IN

INL

, Input Low Voltage

0.8

V max

INH

, Input High Voltage

2.0

V min

MCLK IN Only

INL

, Input Low Voltage

0.8

V max

INH

, Input High Voltage

3.5

V min

LOGIC OUTPUTS

, Output Low Voltage

0.4

V max

SINK

= 1.6 mA

, Output High Voltage

4.0

V min

SOURCE

= 100

Floating State Leakage Current

A max

Floating State Output Capacitance

pF typ

TRANSDUCER BURNOUT

Current

4.5

A nom

Initial Tolerance

% typ

Drift

0.1

C typ

SYSTEM CALIBRATION

AIN1

Positive Full-Scale Calibration Limit

(1.05

REF

)/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

Negative Full-Scale Calibration Limit

(1.05

REF

)/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

Offset Calibration Limit

16, 17

(1.05

REF

)/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

Input Span

0.8

REF

/GAIN

V min

GAIN Is the Selected PGA Gain (Between 1 and 128)

(2.1

REF

)/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

AIN2

Positive Full-Scale Calibration Limit

(4.2

REF

)/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

Negative Full-Scale Calibration Limit

(4.2

REF

)/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

Offset Calibration Limit

(4.2

REF

)/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

Input Span

3.2

REF

/GAIN

V min

GAIN Is the Selected PGA Gain (Between 1 and 128)

(8.4

REF

)/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

NOTES

The AD7712 is tested with the following V

BIAS

voltages. With AV

= +5 V and V

= 0 V, V

BIAS

= +2.5 V; with AV

= +10 V and V

= 0 V, V

BIAS

= +5 V and

with AV

= +5 V and V

= 5 V, V

BIAS

= 0 V.

Guaranteed by design, not production tested.

After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will

output all 0s.

These calibration and span limits apply provided the absolute voltage on the AIN1 analog inputs does not exceed AV

+ 30 mV or does not go more negative

than V

30 mV.

The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.

AD7712

REV. E

Parameter

A, S Versions

Units

Conditions/Comments

POWER REQUIREMENTS

Power Supply Voltages

Voltage

+5 to +10

V nom

5% for Specified Performance

Voltage

V nom

5% for Specified Performance

Voltage

+10.5

V max

For Specified Performance

Power Supply Currents

Current

mA max

Current

4.5

mA max

Current

1.5

mA max

= 5 V

Power Supply Rejection

Rejection w.r.t. AGND; Assumes V

BIAS

Is Fixed

Positive Supply (AV

and DV

)

See Note 21

dB typ

Negative Supply (V

)

dB typ

Power Dissipation

Normal Mode

mW max

= DV

= +5 V, V

= 0 V; Typically 25 mW

Normal Mode

52.5

mW max

= DV

= +5 V, V

= 5 V; Typically 30 mW

Standby (Power-Down) Mode

200

W max

= DV

= +5 V, V

= 0 V or 5 V; Typically 100

NOTES

The AD7712 is specified with a 10 MHz clock for AV

voltages of +5 V

5%. It is specified with an 8 MHz clock for AV

voltages greater than 5.25 V and less

than 10.5 V.

The

5% tolerance on the DV

input is allowed provided that DV

does not exceed AV

by more than 0.3 V.

Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz will

exceed 120 dB with filter notches of 10 Hz, 30 Hz or 60 Hz.

PSRR depends on gain: gain of 1 = 70 dB typ; gain of 2 = 75 dB typ; gain of 4 = 80 dB typ; gains of 8 to 128 = 85 dB typ. These numbers can be improved

(to 95 dB typ) by deriving the V

BIAS

voltage (via Zener diode or reference) from the AV

supply.

Using the hardware STANDBY pin. Standby power dissipation using the software standby bit (PD) of the Control Register is 8 mW typ.

Specifications subject to change without notice.

AD7712SPECIFICATIONS

REV. E

CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-
static fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are inserted.

REF OUT to AGND . . . . . . . . . . . . . . . . . . . . 0.3 V to AV

Digital Input Voltage to DGND . . . . . 0.3 V to AV

+ 0.3 V

Digital Output Voltage to DGND . . . 0.3 V to DV

+ 0.3 V

Operating Temperature Range

Commercial (A Version) . . . . . . . . . . . . . . . 40

C to +85

Extended (S Version) . . . . . . . . . . . . . . . . . 55

C to +125

Storage Temperature Range . . . . . . . . . . . . . 65

C to +150

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300

Power Dissipation (Any Package) to +75

C . . . . . . . . 450 mW

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*

= +25

C, unless otherwise noted)

to DV

. . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +12 V

to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +12 V

to AGND . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +12 V

to DGND . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +12 V

to AGND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +6 V

to DGND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +6 V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to 6 V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to 6 V

AIN1 Input Voltage to AGND . . V

0.3 V to AV

+ 0.3 V

Reference Input Voltage to AGND

. . . . . . . . . . . . . . . . . . . . . . . . . V

0.3 V to AV

+ 0.3 V

ORDERING GUIDE

Model

Temperature Range

Package Options*

AD7712AN

C to +85

N-24

AD7712AR

C to +85

R-24

AD7712AQ

C to +85

Q-24

AD7712SQ

C to +125

Q-24

EVAL-AD7712EB Evaluation Board

*N = Plastic DIP, Q = Cerdip; R = SOIC.

WARNING!

ESD SENSITIVE DEVICE

REV. E

AD7712

TIMING CHARACTERISTICS

1, 2

Limit at T

MIN

, T

MAX

Parameter

(A, S Versions)

Units

Conditions/Comments

CLK IN

4, 5

Master Clock Frequency: Crystal Oscillator or
Externally Supplied

400

kHz min

= +5 V

MHz max

For Specified Performance

MHz

= +5.25 V to +10.5 V

CLK IN LO

0.4

CLK IN

ns min

Master Clock Input Low Time; t

CLK IN

= 1/f

CLK IN

CLK IN HI

0.4

CLK IN

ns min

Master Clock Input High Time

ns max

Digital Output Rise Time; Typically 20 ns

ns max

Digital Output Fall Time; Typically 20 ns

1000

ns min

SYNC Pulsewidth

Self-Clocking Mode

ns min

DRDY to RFS Setup Time; t

CLK IN

= 1/f

CLK IN

ns min

DRDY to RFS Hold Time

CLK IN

ns min

A0 to

RFS Setup Time

ns min

A0 to

RFS Hold Time

CLK IN

+ 20

ns max

RFS Low to SCLK Falling Edge

CLK IN

+ 20

ns max

Data Access Time (

RFS Low to Data Valid)

CLK IN

ns min

SCLK Falling Edge to Data Valid Delay

CLK IN

+ 30

ns max

CLK IN

ns nom

SCLK High Pulsewidth

CLK IN

ns nom

SCLK Low Pulsewidth

ns min

A0 to

TFS Setup Time

ns min

A0 to

TFS Hold Time

CLK IN

+ 20

ns max

TFS to SCLK Falling Edge Delay Time

CLK IN

ns min

TFS to SCLK Falling Edge Hold Time

ns min

Data Valid to SCLK Setup Time

ns min

Data Valid to SCLK Hold Time

(DV

= +5 V 5%; AV

= +5 V or +10 V

5%; V

= 0 V or 5 V 5%; AGND = DGND =

0 V; f

CLKIN

=10 MHz; Input Logic 0 = 0 V, Logic 1 = DV

unless otherwise noted.)

Part Number AD7712