Äîêóìåíòàöèÿ è îïèñàíèÿ www.docs.chipfind.ru
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD7664*
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
16-Bit, 570 kSPS CMOS ADC
FUNCTIONAL BLOCK DIAGRAM
SWITCHED
CAP DAC
16
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
CLOCK
AD7664
DATA[15:0]
BUSY
RD
CS
SER/
PAR
OB/
2C
OGND
OVDD
DGND
DVDD
AVDD AGND REF REFGND
IN
INGND
PD
RESET
SERIAL
PORT
PARALLEL
INTERFACE
CNVST
WARP
IMPULSE
FEATURES
Throughput:
570 kSPS (Warp Mode)
500 kSPS (Normal Mode)
INL: 2.5 LSB Max ( 0.0038% of Full-Scale)
16 Bits Resolution with No Missing Codes
S/(N+D): 90 dB Typ @ 10 kHz
THD: 100 dB Typ @ 10 kHz
Analog Input Voltage Range: 0 V to 2.5 V
Both AC and DC Specifications
No Pipeline Delay
Parallel and Serial 5 V/3 V Interface
Single 5 V Supply Operation
Power Dissipation
97 mW Typical,
21 W @ 100 SPS
Power-Down Mode: 7 W Max
Package: 48-Lead Quad Flat Pack (LQFP)
Pin-to-Pin Compatible Upgrade of the AD7660
APPLICATIONS
Data Acquisition
Instrumentation
Digital Signal Processing
Spectrum Analysis
Medical Instruments
Battery-Powered Systems
Process Control
GENERAL DESCRIPTION
The AD7664 is a 16-bit, 570 kSPS, charge redistribution SAR,
analog-to-digital converter that operates from a single 5 V power
supply. The part contains a high-speed 16-bit sampling ADC,
an internal conversion clock, error correction circuits, and both
serial and parallel system interface ports.
The AD7664 is hardware factory calibrated and is comprehensively
tested to ensure such ac parameters as signal-to-noise ratio (SNR)
and total harmonic distortion (THD), in addition to the more
traditional dc parameters of gain, offset, and linearity.
It features a very high sampling rate mode (Warp) and, for asyn-
chronous conversion rate applications, a fast mode (Normal)
and, for low power applications, a reduced power mode (Impulse)
where the power is scaled with the throughput.
It is fabricated using Analog Devices' high-performance, 0.6
micron CMOS process, with correspondingly low cost and is
available in a 48-lead LQFP with operation specified from 40
°C
to +85
°C.
PRODUCT HIGHLIGHTS
1. Fast Throughput
The AD7664 is a 570 kSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.
2. Superior INL
The AD7664 has a maximum integral nonlinearity of 2.5 LSBs
with no missing 16-bit code.
3. Single-Supply Operation
The AD7664 operates from a single 5 V supply and typically
dissipates only 97 mW. In impulse mode, its power dissipa-
tion decreases with the throughput to, for instance, only 21
µW
at a 100 SPS throughput. It consumes 7
µW maximum when in
power-down.
4. Serial or Parallel Interface
Versatile parallel or 2-wire serial interface arrangement com-
patible with both 3 V or 5 V logic.
*Patent pending.
AD7664SPECIFICATIONS
(40 C to +85 C, AVDD = DVDD= 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
REV. 0
2
Parameter
Conditions
Min
Typ
Max
Unit
RESOLUTION
16
Bits
ANALOG INPUT
Voltage Range
V
IN
V
INGND
0
V
REF
V
Operating Input Voltage
V
IN
0.1
+3
V
V
INGND
0.1
+0.5
V
Analog Input CMRR
f
IN
= 10 kHz
62
dB
Input Current
570 kSPS Throughput
7
µA
Input Impedance
See Analog Input Section
THROUGHPUT SPEED
Complete Cycle
In Warp Mode
1.75
µs
Throughput Rate
In Warp Mode
1
570
kSPS
Time Between Conversions
In Warp Mode
1
ms
Complete Cycle
In Normal Mode
2
µs
Throughput Rate
In Normal Mode
0
500
kSPS
Complete Cycle
In Impulse Mode
2.25
µs
Throughput Rate
In Impulse Mode
0
444
kSPS
DC ACCURACY
Integral Linearity Error
2.5
+2.5
LSB
1
Differential Linearity Error
1
+1.5
LSB
No Missing Codes
16
Bits
Transition Noise
0.7
LSB
Full-Scale Error
2
REF = 2.5 V
±0.08
% of FSR
Unipolar Zero Error
2
±5
±15
LSB
Power Supply Sensitivity
AVDD = 5 V
± 5%
±3
LSB
AC ACCURACY
Signal-to-Noise
f
IN
= 10 kHz
90
dB
3
f
IN
= 100 kHz
88
dB
Spurious Free Dynamic Range
f
IN
= 10 kHz
100
dB
f
IN
= 100 kHz
90
dB
Total Harmonic Distortion
f
IN
= 10 kHz
100
dB
f
IN
= 100 kHz
90
dB
Signal-to-(Noise+Distortion)
f
IN
= 10 kHz
90
dB
f
IN
= 100 kHz
85
dB
60 dB Input
30
dB
3 dB Input Bandwidth
18
MHz
SAMPLING DYNAMICS
Aperture Delay
2
ns
Aperture Jitter
5
ps rms
Transient Response
Full-Scale Step
250
ns
REFERENCE
External Reference Voltage Range
2.3
2.5
2.7
V
External Reference Current Drain
570 kSPS Throughput
115
µA
DIGITAL INPUTS
Logic Levels
V
IL
0.3
+0.8
V
V
IH
+2.0
OVDD + 0.3
V
I
IL
1
+1
µA
I
IH
1
+1
µA
DIGITAL OUTPUTS
Data Format
Parallel or Serial 16-Bits
Pipeline Delay
Conversion Results Available Immediately
After Completed Conversion
V
OL
I
SINK
= 1.6 mA
0.4
V
V
OH
I
SOURCE
= 500
µA
OVDD 0.6
V
POWER SUPPLIES
Specified Performance
AVDD
4.75
5
5.25
V
DVDD
4.75
5
5.25
V
OVDD
2.7
5.25
V
Operating Current
4
570 kSPS Throughput
AVDD
15.5
mA
DVDD
5
3.8
mA
OVDD
5
100
µA
REV. 0
3
AD7664
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLIES (Continued)
Power Dissipation
7
570 kSPS Throughput
4
97
115
mW
100 SPS Througput
6
21
µW
In Power-Down Mode
7
7
µW
TEMPERATURE RANGE
8
Specified Performance
T
MIN
to T
MAX
40
+85
°C
NOTES
1
LSB means Least Significant Bit. With the 0 V to 2.5 V input range, one LSB is 38.15
µV.
2
See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.
4
In normal mode.
5
Tested in parallel reading mode.
6
In impulse mode.
7
With all digital inputs forced to OVDD or OGND respect
ively.
8
Contact factory for extended temperature range.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Symbol
Min
Typ
Max
Unit
Refer to Figures 11 and 12
Convert Pulsewidth
t
1
5
ns
Time Between Conversions
t
2
1.75/2/2.25
Note 1
µs
(Wrap Mode/Normal Mode/Impulse Mode)
CNVST LOW to BUSY HIGH Delay
t
3
25
ns
BUSY HIGH All Modes Except in
t
4
1.5/1.75/2
µs
Master Serial Read After Convert Mode
(Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay
t
5
2
ns
End of Conversion to BUSY LOW Delay
t
6
10
ns
Conversion Time
t
7
1.5/1.75/2
µs
(Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time
t
8
250
ns
RESET Pulsewidth
t
9
10
ns
Refer to Figures 13, 14, and 15 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay
t
10
1.5/1.75/2
µs
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay
t
11
45
ns
Bus Access Request to DATA Valid
t
12
40
ns
Bus Relinquish Time
t
13
5
50
ns
Refer to Figures 16 and 17 (Master Serial Interface Modes)
2
CS LOW to SYNC Valid Delay
t
14
10
ns
CS LOW to Internal SCLK Valid Delay
2
t
15
10
ns
CS LOW to SDOUT Delay
t
16
10
ns
CNVST LOW to SYNC Delay
t
17
25/275/525
ns
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay
t
18
4
ns
Internal SCLK Period
t
19
40
75
ns
Internal SCLK HIGH (INVSCLK Low)
3
t
20
30
ns
Internal SCLK LOW (INVSCLK Low)
3
t
21
9.5
ns
SDOUT Valid Setup Time
t
22
4.5
ns
SDOUT Valid Hold Time
t
23
3
ns
SCLK Last Edge to SYNC Delay
t
24
3
CS HIGH to SYNC HI-Z
t
25
10
ns
CS HIGH to Internal SCLK HI-Z
t
26
10
ns
CS HIGH to SDOUT HI-Z
t
27
10
ns
BUSY HIGH in Master Serial Read After Convert
t
28
2.75/3/3.25
µs
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to SYNC Asserted Delay
t
29
1/1.25/1.5
µs
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY LOW Delay
t
30
50
ns
(40 C to +85 C, AVDD = DVDD
= 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
REV. 0
AD7664
4
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7664 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1
Analog Inputs
IN
2
, REF . . . . . . . . . . . . AVDD + 0.3 V to AGND 0.3 V
INGND, REFGND . . . . . . . . . . . . . . . . . . AGND
± 0.3 V
Ground Voltage Differences
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . .
±0.3 V
Supply Voltages
AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . . . . . . . . . 7 V
AVDD to DVDD,
AVDD to OVDD . . . . . . . . . . . . . .
±7 V
DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±7 V
Digital Inputs
Except the Data Bus D(7:4) . . . 0.3 V to DVDD + 0.3 V
Data Bus Inputs D(7:4) . . . . . . 0.3 V to OVDD + 0.3 V
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD7664AST
40
°C to +85°C
Quad Flatpack (LQFP)
ST-48
AD7664ASTRL
40
°C to +85°C
Quad Flatpack (LQFP)
ST-48
EVAL-AD7664CB
1
Evaluation Board
EVAL-CONTROL BOARD
2
Controller Board
NOTES
1
This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.
2
This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
Internal Power Dissipation
3
. . . . . . . . . . . . . . . . . . . 700 mW
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150
°C
Storage Temperature Range . . . . . . . . . . . . 65
°C to +150°C
Lead Temperature Range
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
See Analog Input section.
3
Specification is for device in free air:
48-Lead LQFP:
JA
= 91
°C/W,
JC
= 30
°C/W.
TIMING SPECIFICATIONS (Continued)
Symbol
Min
Typ
Max
Unit
Refer to Figures 18 and 20 (Slave Serial Interface Modes)
2
External SCLK Setup Time
t
31
5
ns
External SCLK Active Edge to SDOUT Delay
t
32
3
16
ns
SDIN Setup Time
t
33
5
ns
SDIN Hold Time
t
34
5
ns
External SCLK Period
t
35
25
ns
External SCLK HIGH
t
36
10
ns
External SCLK LOW
t
37
10
ns
NOTES
1
In warp mode only, the maximum time between conversions is 1 ms, otherwise, there is no required maximum time.
2
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
3
If the polarity of SCLK is inverted, the timing references of SCLK are also inverted.
Specifications subject to change without notice.
REV. 0
AD7664
5
TO OUTPUT
PIN
1.6mA
I
OL
C
L
60pF
1
500 A
I
OH
1.4V
Figure 1. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, C
L
= 10 pF
0.8V
2V
2V
0.8V
0.8V
2V
t
DELAY
t
DELAY
Figure 2. Voltage Reference Levels for Timing
PIN CONFIGURATION
48-Lead LQFP
(ST-48)
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AGND
CNVST
PD
RESET
CS
RD
DGND
AGND
AVDD
NC
DGND
OB/
2C
WARP
IMPULSE
NC = NO CONNECT
SER/
PAR
D0
D1
D2
BUSY
D15
D14
D13
AD7664
D3
D12
D4/EXT/
INT
D5/INVSYNC
D6/INVSCLK
D7/RDC/SDIN
OGND
OVDD
DVDD
DGND
D8/SDOUT
D9/SCLK
D10/SYNC
D11/RDERROR
NC
NC
NC
NC
NC
NC
NC
NC
NC
INGND
REFGND
REF
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Type
Description
1
AGND
P
Analog Power Ground Pin.
2
AVDD
P
Input Analog Power Pins. Nominally 5 V.
3, 4048
NC
No Connect.
4, 30
DGND
DI
Must Be Tied to Analog Ground.
5
OB/
2C
DI
Straight Binary/Binary Two's Complement. When OB/
2C is HIGH, the digital output is
straight binary; when LOW, the MSB is inverted resulting in a two's complement output
from its internal shift register.
6
WARP
DI
Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the
maximum throughput is achievable, and a minimum conversion rate must be applied in order
to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of
the minimum conversion rate.
7
IMPULSE
DI
Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode. In
this mode, the power dissipation is approximately proportional to the sampling rate.
8
SER/
PAR
DI
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the
serial interface mode is selected and some bits of the DATA bus are used as a serial port.
912
DATA[0:3]
DO
Bit 0 to Bit 3 of the Parallel Port Data Output Bus. These pins are always outputs, regardless
of the state of SER/
PAR.
13
DATA[4]
DI/O
When SER/
PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus.
or EXT/
INT
When SER/
PAR is HIGH, this input, part of the serial port, is used as a digital select input
for choosing the internal or an external data clock. With EXT/
INT tied LOW, the internal
clock is selected on SCLK output. With EXT/
INT set to a logic HIGH, output data is syn-
chronized to an external clock signal connected to the SCLK input.
14
DATA[5]
DI/O
When SER/
PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.
or INVSYNC
When SER/
PAR is HIGH, this input, part of the serial port, is used to select the active state
of the SYNC signal. It is active in both master and slave mode. When LOW, SYNC is active
HIGH. When HIGH, SYNC is active LOW.
15
DATA[6]
DI/O
When SER/
PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus.
or INVSCLK
When SER/
PAR is HIGH, this input, part of the serial port, is used to invert the SCLK sig-
nal. It is active in both master and slave mode.
REV. 0
AD7664
6
Pin
No.
Mnemonic
Type
Description
16
DATA[7]
DI/O
When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus.
or RDC/SDIN
When SER/
PAR is HIGH, this input, part of the serial port, is used as either an external data
input or a read mode selection input depending on the state of EXT/
INT.
When EXT/
INT is HIGH, RDC/SDIN could be used as a data input to daisy chain the conver-
sion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is
output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence.
When EXT/
INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is
HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the
data can be output on SDOUT only when the conversion is complete.
17
OGND
P
Input/Output interface Digital Power Ground.
18
OVDD
P
Input/Output interface Digital Power. Nominally at the same supply than the supply of the
host interface (5 V or 3 V).
19
DVDD
P
Digital Power. Nominally at 5 V.
20
DGND
P
Digital Power Ground.
21
DATA[8]
DO
When SER/
PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.
or SDOUT
When SER/
PAR is HIGH, this output, part of the serial port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7664
provides the conversion result, MSB first, from its internal shift register. The DATA format is
determined by the logic level of OB/
2C. In serial mode, when EXT/INT is LOW, SDOUT is
valid on both edges of SCLK.
In serial mode, when EXT/
INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next
falling edge.
If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising
edge.
22
DATA[9]
DI/O
When SER/
PAR is LOW, this output is used as the Bit 9 of the Parallel Port Data
or SCLK
Output Bus.
When SER/
PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input
or output, dependent upon the logic state of the EXT/
INT pin. The active edge where the
data SDOUT is updated depends upon the logic state of the INVSCLK pin.
23
DATA[10]
DO
When SER/
PAR is LOW, this output is used as the Bit 10 of the Parallel Port Data Output Bus.
or SYNC
When SER
/PAR is HIGH, this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/
INT = Logic LOW). When a read
sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH
while SDOUT output is valid. When a read sequence is initiated and INVSYNC is High,
SYNC is driven LOW and remains LOW while SDOUT output is valid.
24
DATA[11]
DO
When SER/
PAR is LOW, this output is used as the Bit 11 of the Parallel Port Data Output Bus.
or RDERROR
When SER/
PAR is HIGH and EXT/INT is HIGH, this output, part of the serial port, is used
as a incomplete read error flag. In slave mode, when a data read is started and not complete
when the following conversion is complete, the current data is lost and RDERROR is pulsed
high.
2528
DATA[12:15]
DO
Bit 12 to Bit 15 of the Parallel Port Data output bus. These pins are always outputs regardless
of the state of SER/
PAR.
29
BUSY
DO
Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the
conversion is complete and the data is latched into the on-chip shift register. The falling edge
of BUSY could be used as a data ready clock signal.
30
DGND
P
Must Be Tied to Digital Ground.
31
RD
DI
Read Data. When
CS and RD are both LOW, the interface parallel or serial output bus is
enabled.
RD and CS are OR'd together internally.
32
CS
DI
Chip Select. When
CS and RD are both LOW, the interface parallel or serial output bus is
enabled.
RD and CS are OR'd together internally.
33
RESET
DI
Reset Input. When set to a logic HIGH, reset the AD7664. Current conversion if any is aborted.
34
PD
DI
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conver-
sions are inhibited after the current one is completed.
REV. 0
AD7664
7
Pin
No.
Mnemonic
Type
Description
35
CNVST
DI
Start Conversion. A falling edge on
CNVST puts the internal sample/hold into the hold state and
initiates a conversion. In impulse mode (IMPULSE HIGH and WARP LOW), if
CNVST is
held low when the acquisition phase
(t
8
) is complete, the internal sample/hold is put into the
hold state and a conversion is immediately started.
36
AGND
P
Must Be Tied to Analog Ground.
37
REF
AI
Reference Input Voltage.
38
REFGND
AI
Reference Input Analog Ground.
39
INGND
AI
Analog Input Ground.
43
IN
AI
Primary Analog Input with a Range of 0 V to V
REF.
NOTES
AI = Analog Input
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power
DEFINITION OF SPECIFICATIONS
INTEGRAL NONLINEARITY ERROR (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from "negative full scale" through "positive full
scale." The point used as "negative full scale" occurs 1/2 LSB
before the first code transition. "Positive full scale" is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
DIFFERENTIAL NONLINEARITY ERROR (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It is
often specified in terms of resolution for which no missing codes
are guaranteed.
FULL-SCALE ERROR
The last transition (from 011 . . . 10 to 011 . . . 11 in two's
complement coding) should occur for an analog voltage 1 1/2 LSB
below the nominal full scale (2.49994278 V for the 0 V2.5 V
range). The full-scale error is the deviation of the actual level of
the last transition from the ideal level.
UNIPOLAR ZERO ERROR
The first transition should occur at a level 1/2 LSB above analog
ground (19.073
µV for the 0 V2.5 V range). Unipolar zero error is
the deviation of the actual transition from that point.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
EFFECTIVE NUMBER OF BITS (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) by the following formula:
ENOB = (S/[N+D]
dB
1.76)/6.02)
and is expressed in bits.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
SIGNAL-TO-NOISE RATIO (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
SIGNAL TO (NOISE + DISTORTION) RATIO
(S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.
APERTURE DELAY
Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the
CNVST input to when
the input signal is held for a conversion.
TRANSIENT RESPONSE
The time required for the AD7664 to achieve its rated accuracy
after a full-scale step function is applied to its input.
OVERVOLTAGE RECOVERY
The time required for the ADC to recover to full accuracy after
an analog input signal 150% of full-scale is reduced to 50% of
the full-scale value.
REV. 0
AD7664
8
Typical Performance Characteristics
2.5
INL LSB
CODE
65536
1.5
0
1.5
2.5
49152
32768
16384
0
1.0
0.5
2.0
2.0
0.5
1.0
TPC 1. Integral Nonlinearity vs. Code
8000
7F86
COUNTS
CODE Hexa
7F87
7F8F
7F8E
7F8D
7F8C
7F8B
7F8A
7F89
7F88
7000
6000
5000
4000
3000
2000
1000
0
753
7288 7148
1173
10
0
0
12
0
0
TPC 2. Histogram of 16,384 Conversions of a DC Input
at the Code Transition
0
0
AMPLITUDE
dB of Full Scale
50
100
150
200
250
300
FREQUENCY kHz
20
40
60
80
100
120
140
160
180
4096 POINT FFT
f
S
= 570kHz
f
IN
= 10.39kHz, 0.5dB
SNR = 90.1dB
SINAD = 89.6dB
THD = 98.7dB
SFDR = 100.3dB
TPC 3. FFT Plot
1.50
DNL
LSB
CODE
65536
1.00
0.25
0.50
1.00
49152
32768
16384
0
0.75
0
0.75
1.25
0.50
0.25
TPC 4. Differential Nonlinearity vs. Code
10000
7FB3
COUNTS
CODE Hexa
7FB4
7FBB
7FBA
7FB9
7FB8
7FB7
7FB6
7FB5
8000
6000
5000
4000
3000
2000
1000
0
3340
9008
3643
257
0
0
136
0
0
9000
7000
TPC 5. Histogram of 16,384 Conversions of a DC Input
at the Code Center
96
55
SNR AND S/(N+D)
dB
TEMPERATURE C
35
125
105
85
65
45
25
5
15
93
90
87
84
96
98
100
102
104
THD
dB
THD
SNR
TPC 6. SNR, THD vs. Temperature
REV. 0
AD7664
9
100
1
SNR AND S/(N+D)
dB
FREQUENCY kHz
1000
100
10
90
80
70
15.0
14.0
13.0
12.0
11.0
ENOB
Bits
ENOB
SNR
85
75
95
14.5
13.5
12.5
11.5
S/(N+D)
TPC 7. SNR, S/(N+D), and ENOB vs. Frequency
92
60
SNR (REFERRED TO FULL SCALE)
d
INPUT LEVEL dB
0
20
40
90
88
86
SNR
S/(N+D)
50
30
10
TPC 8. SNR and S/(N+D) vs. Input Level
OVDD, ALL MODES
DVDD, IMPULSE
AVDD, IMPULSE
DVDD, WARP/NORMAL
AVDD, WARP/NORMAL
100k
0.1
OPERATING CURRENTS
A
SAMPLING RATE SPS
100k
1k
10
1
100
10k
1000k
10k
1k
100
10
1
0.1
0.01
0.001
TPC 9. Operating Currents vs. Sample Rate
1
THD, HARMINICS
dB
FREQUENCY kHz
1k
100
10
110
SFDR
dB
SFDR
2ND HARMONICS
105
100
95
90
85
80
75
70
65
60
60
65
70
75
80
85
90
95
100
105
110
THD
3RD HARMONICS
TPC 10. THD, Harmonics, and SFDR vs. Frequency
50
0
t
12
DELAY
ns
C
L
pF
200
50
20
10
0
100
150
30
40
OVDD = 5V, 25 C
OVDD = 5V, 85 C
OVDD = 2.7V, 85 C
OVDD = 2.7V, 25 C
TPC 11. Typical Delay vs. Load Capacitance C
L
TEMPERATURE C
POWER-DOWN OPERATING CURRENTS
nA
0
20
50
25
0
25
50
75
100
40
60
80
100
10
30
50
70
90
AVDD
OVDD
DVDD
TPC 12. Power-Down Operating Currents vs. Temperature
REV. 0
AD7664
10
CIRCUIT INFORMATION
The AD7664 is a very fast, low power, single supply, precise
16-bit analog-to-digital converter (ADC). The AD7664 fea-
tures different modes to optimize performances according to
the applications.
In warp mode, the AD7664 is capable of converting 570,000
samples per second (570 kSPS).
The AD7664 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any pipe-
line or latency, making it ideal for multiple multiplexed channel
applications.
The AD7664 can be operated from a single 5 V supply and
be interfaced to either 5 V or 3 V digital logic. It is housed in
a 48-lead LQFP package that saves space and allows flexible con-
figurations as either serial or parallel interface. The AD7664 is a
pin-to-pin compatible upgrade of the AD7660.
CONVERTER OPERATION
The AD7664 is a successive-approximation analog-to-digital
converter based on a charge redistribution DAC. Figure 3 shows
the simplified schematic of the ADC. The capacitive DAC consists
of an array of 16 binary weighted capacitors and an additional
"LSB" capacitor. The comparator's negative input is connected
to a "dummy" capacitor of the same value as the capacitive
DAC array.
During the acquisition phase, the common terminal of the array
tied to the comparator's positive input is connected to AGND
via SW
A
. All independent switches are connected to the analog
input IN. Thus, the capacitor array is used as a sampling capaci-
tor and acquires the analog signal on IN input. Similarly, the
"dummy" capacitor acquires the analog signal on INGND input.
When the
CNVST input goes low, a conversion phase is
initiated. When the conversion phase begins, SW
A
and SW
B
are opened first. The capacitor array and the "dummy" capaci-
tor are then disconnected from the inputs and connected to
the REFGND input. Therefore, the differential voltage between
IN and INGND captured at the end of the acquisition phase is
applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between REFGND or REF, the comparator input varies by
binary-weighted voltage steps (V
REF
/2, V
REF
/4, . . . V
REF
/65536).
The control logic toggles these switches, starting with the MSB
first, to bring the comparator back into a balanced condition. After
the completion of this process, the control logic generates the
ADC output code and brings BUSY output low.
SW
A
COMP
SW
B
IN
REF
REFGND
LSB
MSB
32,768C
INGND
16,384C
4C
2C
C
C
65,536C
CONTROL
LOGIC
SWITCHES
CONTROL
BUSY
OUTPUT
CODE
CNVST
Figure 3. ADC Simplified Schematic
Modes of Operation
The AD7664 features three modes of operations, Warp, Normal,
and Impulse. Each of these modes is more suitable for specific
applications.
The Warp mode allows the fastest conversion rate up to 570 kSPS.
However, in this mode, and this mode only, the full specified accu-
racy is guaranteed only when the time between conversion does
not exceed 1 ms. If the time between two consecutive conversions
is longer than 1 ms, for instance, after power-up, the first conver-
sion result should be ignored. This mode makes the AD7664
ideal for applications where both high accuracy and fast sample
rate are required.
The normal mode is the fastest mode (500 kSPS ) without any
limitation about the time between conversions. This mode makes
the AD7664 ideal for asynchronous applications such as data
acquisition systems, where both high accuracy and fast sample
rate are required.
The impulse mode, the lowest power dissipation mode, allows
power saving between conversions. When operating at 100 SPS,
for example, it typically consumes only 21
µW. This feature
makes the AD7664 ideal for battery-powered applications.
Transfer Functions
Using the OB/
2C digital input, the AD7664 offers two output
codings: straight binary and two's complement. The LSB size is
V
REF
/65536, which is about 38.15
µV. The ideal transfer charac-
teristic for the AD7664 is shown in Figure 4 and Table I.
000...000
000...001
000...010
111...101
111...110
111...111
ADC CODE
Straight Binary
ANALOG INPUT
V
REF
1.5 LSB
V
REF
1 LSB
1 LSB
0V
0.5 LSB
1 LSB = V
REF
/65536
Figure 4. ADC Ideal Transfer Function
REV. 0
AD7664
11
Table I. Output Codes and Ideal Input Voltages
Digital Output Code
Hexa
Analog
Straight
Two's
D
escription
Input
Binary
Complement
FSR 1 LSB
2.499962 V
FFFF
1
7FFF
1
FSR 2 LSB
2.499923 V
FFFE
7FFE
Midscale + 1 LSB
1.250038 V
8001
0001
Midscale
1.25 V
8000
0000
Midscale 1 LSB
1.249962 V
7FFF
FFFF
FSR + 1 LSB
38
µV
0001
8001
FSR
0 V
0000
2
8000
2
NOTES
1
This is also the code for overrange analog input (V
IN
V
INGND
above
V
REF
V
REFGND
).
2
This is also the code for underrange analog input (V
IN
below V
INGND
)
TYPICAL CONNECTION DIAGRAM
Figure 5 shows a typical connection diagram for the AD7664.
Analog Input
Figure 6 shows an equivalent circuit of the input structure of
the AD7664.
C2
R1
D1
D2
C1
IN
OR INGND
AGND
AVDD
Figure 6. Equivalent Analog Input Circuit
The two diodes D1 and D2 provide ESD protection for the
analog inputs IN and INGND. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by more
than 0.3 V. This will cause these diodes to become forward-
biased and start conducting current. These diodes can handle
a forward-biased current of 100 mA maximum. For instance,
these conditions could eventually occur when the input buffer's
(U1) supplies are different from AVDD. In such case, an input
buffer with a short circuit current limitation can be used to
protect the part.
100nF
10 F
100nF
10 F
AVDD
10 F
100nF
AGND
DGND
DVDD
OVDD
OGND
WARP
IMPULSE
SER/
PAR
CNVST
BUSY
SDOUT
SCLK
RD
CS
RESET
PD
IN
INGND
REFGND
100nF
C
REF
1
2.5V REF
1
REF
100
D
3
CLOCK
AD7664
ANALOG INPUT
(0V TO 2.5V)
C/ P/DSP
SERIAL
PORT
DIGITAL SUPPLY
(3.3V OR 5V)
ANALOG
SUPPLY
(5V)
NOTES:
1
THE AD780 IS RECOMMENDED WITH C
REF
= 47 F.
2
THE AD829 IS RECOMMENDED WITH A COMPENSATION CAPACITOR C
C
= 82 pF, TYPE CERAMIC NPO.
3
OPTIONAL LOW JITTER
CNVST.
DVDD
C
C
OB/
2C
2.7nF
U1
2
15
Figure 5. Typical Connection Diagram
REV. 0
AD7664
12
This analog input structure allows the sampling of the differen-
tial signal between IN and INGND. Unlike other converters,
the INGND input is sampled at the same time as the IN input.
By using this differential input, small signals common to both
inputs are rejected, as shown in Figure 7, which represents the
typical CMR over frequency. For instance, by using INGND to
sense a remote signal ground, difference of ground potentials
between the sensor and the local ADC ground are eliminated.
70
1
CMRR
dB
FREQUENCY kHz
1k
50
30
0
100
60
40
20
10
10
Figure 7. Analog Input CMR vs. Frequency
During the acquisition phase, the impedance of the analog input
IN can be modeled as a parallel combination of capacitor C1
and the network formed by the series connection of R1 and C2.
Capacitor C1 is primarily the pin capacitance. The resistor R1 is
typically 140
and is a lumped component made up of some
serial resistors and the on resistance of the switches. The capacitor
C2 is typically 60 pF and is mainly the ADC sampling capacitor.
During the conversion phase, where the switches are opened, the
input impedance is limited to C1. The R1, C2 makes a one-pole
low-pass filter that reduces undesirable aliasing effect and limits
the noise.
When the source impedance of the driving circuit is low, the
AD7664 can be driven directly. Large source impedances will
significantly affect the ac performances, especially the total
harmonic distortion. The maximum source impedance depends
on the amount of total harmonic distortion (THD) that can be
tolerated. The THD degrades in function of the source imped-
ance and the maximum input frequency as shown in Figure 8.
70
10
THD
dB
FREQUENCY kHz
1k
80
90
100
100
75
85
95
R
S
= 100
R
S
= 50
R
S
= 20
R
S
= 11
Figure 8. THD vs. Analog Input Frequency and
Source Resistance
Driver Amplifier Choice
Although the AD7664 is easy to drive, the driver amplifier needs
to meet at least the following requirements:
·
The driver amplifier and the AD7664 analog input circuit
have to be able together to settle for a full-scale step the
capacitor array at a 16-bit level (0.0015%). For instance,
operation at the maximum throughput of 570 kSPS requires
a minimum gain bandwidth product of 39 MHz.
·
The noise generated by the driver amplifier needs to be kept
as low as possible in order to preserve the SNR and transi-
tion noise performance of the AD7664. The noise coming
from the driver is filtered by the AD7664 analog input circuit
one-pole low-pass filter made by R1 and C2. For instance, a
driver such as the AD829, with an equivalent input noise of
2 nV/
Hz and configured as a buffer, thus, with a noise gain
of 1, degrades the SNR by only 0.45 dB. A driver amplifier
with an equivalent input noise of 5 nV/
Hz in the same con-
figuration will add 1.9 dB degradation.
·
To even further reduce the noise filtering done by the AD7664
analog input circuit, an external simple one-pole RC filter
between the amplifier output and the ADC analog input will
slightly improve the ac performances, specially, the SNR and
the transition noise. For example, as shown in Figure 5, a 15
source resistor with a 2.7 nF good linearity capacitor (NPO or
mica type) limit the bandwidth to 4 MHz.
·
The driver needs to have a THD performance suitable to that
of the AD7664. TPC 10 gives the THD versus frequency
that the driver should preferably exceed. The AD829 meets
these requirements. The AD829 requires an external compensa-
tion capacitor of 82 pF. This capacitor should have good
linearity as an NPO ceramic or mica or prolypropylene type.
Moreover, the use of a noninverting 1 gain arrangement is
recommended and helps to obtain the best signal-to-noise ratio.
Voltage Reference Input
The AD7664 uses an external 2.5 V voltage reference. The voltage
reference input REF of the AD7664 has a dynamic input imped-
ance. Therefore, it should be driven by a low impedance source
with an efficient decoupling between REF and REFGND inputs.
This decoupling depends on the choice of the voltage reference,
but usually consists of a low ESR tantalum capacitor and a 100 nF
ceramic capacitor. Appropriate value for the tantalum capacitor
is 47
µF with the low-cost, low-power ADR291 voltage reference,
or with the low-noise, low-drift AD780 voltage reference. For
applications using multiple AD7664s, it is more effective to buffer
the reference voltage with a low-noise, very stable op amp like
the AD8031.
Care should also be taken with the reference temperature coeffi-
cient of the voltage reference which directly affects the full-scale
accuracy if this parameter matters. For instance, a
±15 ppm/°C
tempco of the reference changes the full scale by
±1 LSB/°C.
Power Supply
The AD7664 uses three sets of power supply pins: an analog 5 V
supply AVDD, a digital 5 V core supply DVDD, and a digital
input/output interface supply OVDD. The OVDD supply allows
direct interface with any logic working between 2.7 V and 5.25 V.
To reduce the number of supplies needed, the digital core
(DVDD) can be supplied through a simple RC filter from the
analog supply as shown in Figure 5. The AD7664 is independent
REV. 0
AD7664
13
of power supply sequencing and thus free from supply voltage
induced latchup. Additionally, it is very insensitive to power supply
variations over a wide frequency range as shown in Figure 9.
50
1
PSRR
dB
INPUT FREQUENCY kHz
1000
60
70
80
100
55
65
75
10
Figure 9. PSRR vs. Frequency
POWER DISSIPATION VS. THROUGHPUT
Operating currents are very low during the acquisition phase,
which allows a significant power saving when the conversion
rate is reduced as shown in Figure 10. This power saving depends
on the mode used. In impulse mode, the AD7664 automatically
reduces its power consumption at the end of each conversion
phase. This feature makes the AD7664 ideal for very low power
battery applications. It should be noted that the digital inter-
face remains active even during the acquisition phase. To reduce
the operating digital supply currents even further, the digital
inputs need to be driven close to the power supply rails (i.e.,
DVDD or DGND for all inputs except EXT/
INT, INVSYNC,
INVSCLK, RDC/SDIN, and OVDD or OGND for these last
four inputs).
100k
0.1
OPERATING CURRENTS
A
SAMPLING RATE SPS
100k
1k
10
1
100
10k
1M
10k
1k
100
10
1
0.1
WARP/NORMAL
IMPULSE
Figure 10. Power Dissipation vs. Sample Rate
CONVERSION CONTROL
Figure 11 shows the detailed timing diagrams of the conversion
process. The AD7664 is controlled by the signal
CNVST which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conver-
sion is complete. The
CNVST signal operates independently of
CS and RD signals.
CNVST
BUSY
MODE
t
2
t
1
t
3
t
4
t
5
t
6
t
7
t
8
ACQUIRE
CONVERT
ACQUIRE
CONVERT
Figure 11. Basic Conversion Timing
In impulse mode, conversions can be automatically initiated. If
CNVST is held low when BUSY is low, the AD7664 controls the
acquisition phase and then automatically initiates a new conver-
sion. By keeping
CNVST low, the AD7664 keeps the conversion
process running by itself. It should be noted that the analog
input has to be settled when BUSY goes low. Also, at power-up,
CNVST should be brought low once to initiate the conversion
process. In this mode, the AD7664 could sometimes run slightly
faster then the guaranteed limits in the impulse mode of 444 kSPS.
This feature does not exist in warp or normal modes.
t
9
t
8
RESET
DATA
BUSY
CNVST
Figure 12. RESET Timing
Although
CNVST is a digital signal, it should be designed with
special care with fast, clean edges, and levels with minimum
overshoot and undershoot or ringing.
For applications where the SNR is critical,
CNVST signal
should have a very low jitter. Some solutions to achieve that is
to use a dedicated oscillator for
CNVST generation or, at least,
to clock it with a high-frequency low-jitter clock as shown in
Figure 5.
REV. 0
AD7664
14
DIGITAL INTERFACE
The AD7664 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7664 digital interface also accommodates both 3 V or 5 V logic
by simply connecting the OVDD supply pin of the AD7664 to
the host system interface digital supply. Finally, by using the
OB/
2C input pin, both two's complement or straight binary
coding can be used.
The two signals
CS and RD control the interface. CS and RD
have a similar effect because they are OR'd together internally.
When at least one of these signals is high, the interface outputs
are in high impedance. Usually,
CS allows the selection of each
AD7664 in multicircuits applications and is held low in a single
AD7664 design.
RD is generally used to enable the conversion
result on the data bus.
t
1
t
3
t
4
t
11
CNVST
BUSY
DATA
BUS
CS = RD = 0
t
10
PREVIOUS CONVERSION DATA
NEW DATA
Figure 13. Master Parallel Data Timing for Reading
(Continuous Read)
PARALLEL INTERFACE
The AD7664 is configured to use the parallel interface when the
SER/
PAR is held low. The data can be read either after each
conversion, which is during the next acquisition phase, or dur-
ing the following conversion as shown, respectively, in Figure 14
and Figure 15. When the data is read during the conversion,
however, it is recommended that it is read only during the first
half of the conversion phase. That avoids any potential feed-
through between voltage transients on the digital interface and
the most critical analog conversion circuitry.
CURRENT
CONVERSION
BUSY
DATA
BUS
CS
RD
t
12
t
13
Figure 14. Slave Parallel Data Timing for Reading
(Read After Convert)
PREVIOUS
CONVERSION
t
1
t
3
t
12
t
13
t
4
CS = 0
CNVST,
RD
BUSY
DATA
BUS
Figure 15. Slave Parallel Data Timing for Reading
(Read During Convert)
SERIAL INTERFACE
The AD7664 is configured to use the serial interface when the
SER/
PAR is held high. The AD7664 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on SCLK pin. The output data is
valid on both the rising and falling edge of the data clock.
MASTER SERIAL INTERFACE
Internal Clock
The AD7664 is configured to generate and provide the serial data
clock SCLK when the EXT/
INT pin is held low. The AD7664
also generates a SYNC signal to indicate to the host when the
serial data is valid. The serial clock SCLK and the SYNC signal
can be inverted if desired. Depending on RDC/SDIN input, the
data can be read after each conversion or during the following
conversion. Figure 16 and Figure 17 show the detailed timing
diagrams of these two modes.
Usually, because the AD7664 is used with a fast throughput, the
mode master, read during conversion is the most recommended
serial mode when it can be used.
In read-during-conversion mode, the serial clock and data toggle
at appropriate instants which minimize potential feedthrough
between digital activity and the critical conversion decisions.
In read-after-conversion mode, it should be noted that, unlike in
other modes, the signal BUSY returns low after the 16 data bits
are pulsed out and not at the end of the conversion phase which
results in a longer BUSY width.
SLAVE SERIAL INTERFACE
External Clock
The AD7664 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/
INT pin is
held high. In this mode, several methods can be used to read the
data. When
CS and RD are both low, the data can be read after
each conversion or during the following conversion. The exter-
nal clock can be either a continuous or discontinuous clock. A
discontinuous clock can be either normally high or normally low
when inactive. Figure 18 and Figure 20 show the detailed tim-
ing diagrams of these methods.
REV. 0
AD7664
15
t
3
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
t
28
t
29
t
14
t
18
t
19
t
20
t
21
t
24
t
26
t
27
t
23
t
22
t
16
t
15
1
2
3
14
15
16
D15
D14
D2
D1
D0
X
EXT/
INT = 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t
25
t
30
Figure 16. Master Serial Data Timing for Reading (Read After Convert)
EXT/
INT = 0
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
t
3
t
1
t
17
t
14
t
19
t
20
t
21
t
24
t
26
t
25
t
27
t
23
t
22
t
16
t
15
D15
D14
D2
D1
D0
X
1
2
3
14
15
16
t
18
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
Figure 17. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)
REV. 0
AD7664
16
While the AD7664 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
degradation of the conversion result could occur. This is par-
ticularly important during the second half of the conversion
phase because the AD7664 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is recom-
mended that when an external clock is being provided, it is a
discontinuous clock that is toggling only when BUSY is low or,
more importantly, that is does not transition during the latter
half of BUSY high.
External Discontinuous Clock Data Read After Conversion
Though the maximum throughput cannot be achieved using this
mode, it is the most recommended of the serial slave modes.
Figure 18 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
low, the result of this conversion can be read while both
CS and
RD are low. The data is shifted out, MSB first, with 16 clock
pulses and is valid on both rising and falling edge of the clock.
Among the advantages of this method, the conversion perfor-
mance is not degraded because there are no voltage transients
on the digital interface during the conversion process.
Another advantage is to be able to read the data at any speed up
to 40 MHz which accommodates both slow digital host interface
and the fastest serial reading.
Finally, in this mode only, the AD7664 provides a "daisy chain"
feature using the RDC/SDIN input pin for cascading multiple
converters together. This feature is useful for reducing component
count and wiring connections when desired as, for instance, in
isolated multiconverter applications.
An example of the concatenation of two devices is shown in
Figure 19. Simultaneous sampling is possible by using a com-
mon
CNVST signal. It should be noted that the RDC/SDIN
input is latched on the opposite edge of SCLK of the one used to
shift out the data on SDOUT. Hence, the MSB of the "upstream"
converter just follows the LSB of the "downstream" converter
on the next SCLK cycle.
SCLK
SDOUT
D15
D14
D1
D0
D13
X15
X14
X13
X1
X0
Y15
Y14
CS, RD
BUSY
SDIN
EXT/I
NT = 1
INVSCLK = 0
t
35
t
36
t
37
t
31
t
32
t
16
t
33
t
34
X15
X14
X
1
2
3
14
15
16
17
18
Figure 18. Slave Serial Data Timing for Reading (Read After Convert)
CNVST
CS
SCLK
SDOUT
RDC/SDIN
BUSY
BUSY
DATA
OUT
AD7664
#1
(DOWNSTREAM)
BUSY
OUT
CNVST
CS
SCLK
AD7664
#2
(UPSTREAM)
RDC/SDIN
SDOUT
SCLK IN
CS IN
CNVST IN
Figure 19. Two AD7664s in a "Daisy Chain" Configuration
External Clock Data Read During Conversion
Figure 20 shows the detailed timing diagrams of this method.
During a conversion, while both
CS and RD are both low, the
result of the previous conversion can be read. The data is shifted
out, MSB first, with 16 clock pulses and is valid on both rising and
falling edge of the clock. The 16 bits have to be read before the
current conversion is complete. If that is not done, RDERROR is
pulsed high and can be used to interrupt the host interface to
prevent incomplete data reading. There is no "daisy chain"
feature in this mode and RDC/SDIN input should always be
tied either high or low.
To reduce performance degradation due to digital activity, a fast
discontinuous clock of, at least 18 MHz, when impulse mode is
used, 25 MHz when normal mode is used or 40 MHz when warp
mode is used, is recommended to ensure that all the bits are read
during the first half of the conversion phase. It is also possible
to begin to read the data after conversion and continue to read
the last bits even after a new conversion has been initiated. That
allows the use of a slower clock speed like 14 MHz in impulse
mode, 18 MHz in normal mode and 25 MHz in warp mode.
REV. 0
AD7664
17
MICROPROCESSOR INTERFACING
The AD7664 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and ac signal processing
applications interfacing to a digital signal processor. The AD7664
is designed to interface either with a parallel 16-bit-wide interface
or with a general-purpose serial port or I/O ports on a microcon-
troller. A variety of external buffers can be used with the AD7664
to prevent digital noise from coupling into the ADC. The following
sections illustrate the use of the AD7664 with an SPI-equipped
microcontroller, the ADSP-21065L and ADSP-218x signal
processors.
SPI Interface (MC68HC11)
Figure 21 shows an interface diagram between the AD7664 and
an SPI-equipped microcontroller like the MC68HC11. To accom-
modate the slower speed of the microcontroller, the AD7664 acts
as a slave device and data must be read after conversion. This
mode allows also the "daisy chain" feature.
The convert command could be initiated in response to an
internal timer interrupt. The reading of output data, one byte
at a time, if necessary, could be initiated in response to the
end-of-conversion signal (BUSY going low) using to an interrupt
line of the microcontroller. The Serial Peripheral Interface
(SPI) on the MC68HC11 is configured for master mode
(MSTR = 1), Clock Polarity Bit (CPOL) = 0, Clock Phase Bit
(CPHA) = 1 and SPI Interrupt Enable (SPIE = 1) by writing to
the SPI Control Register (SPCR). The IRQ is configured for
edge-sensitive-only operation (IRQE = 1 in OPTION register).
IRQ
MC68HC11*
CNVST
AD7664*
CS
BUSY
MISO/SDI
SCK
I/O PORT
SDOUT
SCLK
RD
INVSCLK
EXT/
INT
SER/
PAR
DVDD
*ADDITIONAL PINS OMITTED FOR CLARITY
OVDD
Figure 21. Interfacing the AD7664 to SPI Interface
ADSP-21065L in Master Serial Interface
As shown in Figure 22, the AD7664 can be interfaced to the
ADSP-21065L using the serial interface in master mode without
any glue logic required. This mode combines the advantages of
reducing the number of wire connections and being able to read
the data during or after conversion at user convenience.
The AD7664 is configured for the internal clock mode (EXT/
INT
low) and acts, therefore, as the master device. The convert com-
mand can be generated by either an external low jitter oscillator
or, as shown, by a FLAG output of the ADSP-21065L or by a
frame output TFS of one serial port of the ADSP-21065L which
can be used as a timer. The serial port on the ADSP-21065L is
configured for external clock (IRFS = 0), rising edge active
(CKRE = 1), external late framed sync signals (IRFS = 0,
LAFS = 1, RFSR = 1) and active high (LRFS = 0). The serial
port of the ADSP-21065L is configured by writing to its receive
control register (SRCTL)--see ADSP-2106x SHARC User's
Manual. Because the serial port within the ADSP-21065L will
be seeing a discontinuous clock, an initial word reading has to be
done after the ADSP-21065L has been reset to ensure that the
serial port is properly synchronized to this clock during each
following data read operation.
RFS
ADSP-21065L*
SHARC
CNVST
AD7664*
CS
SYNC
RD
DR
RCLK
FLAG OR TFS
SDOUT
SCLK
INVSYNC
INVSCLK
EXT/
INT
RDC/SDIN
SER/
PAR
DVDD
*
ADDITIONAL PINS OMITTED FOR CLARITY
OVDD
OR
OGND
Figure 22. Interfacing to the ADSP-21065L Using the
Serial Master Mode
SDOUT
CS, RD
SCLK
D1
D0
X
D15
D14
D13
1
2
3
14
15
16
t
3
t
35
t
36
t
37
t
31
t
32
t
16
CNVST
BUSY
EXT/I
NT = 1
INVSCLK = 0
Figure 20. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
REV. 0
AD7664
18
APPLICATION HINTS
Bipolar and Wider Input Ranges
In some applications, it is desired to use a bipolar or wider ana-
log input range like, for instance,
±10 V, ±5 V or 0 V to 5 V.
Although the AD7664 has only one unipolar range, by simple
modifications of the input driver circuitry, bipolar and wider
input ranges can be used without any performance degradation.
Figure 23 shows a connection diagram which allows that. Com-
ponents values required and resulting full-scale ranges are shown in
Table II.
For applications where accurate gain and offset are desired, they
can be calibrated by acquiring a ground and a voltage reference
using an analog multiplexer, U2, as shown in Figure 23. Also,
C
F
can be used as a one-pole antialiasing filter.
Layout
The AD7664 has very good immunity to noise on the power
supplies as can be seen in Figure 9. However, care should still
be taken with regard to grounding layout.
The printed circuit board that houses the AD7664 should be
designed so the analog and digital sections are separated and
confined to certain areas of the board. This facilitates the use of
ground planes that can be easily separated. Digital and analog
ground planes should be joined in only one place, preferably
underneath the AD7664, or, at least, as close as possible to the
AD7664. If the AD7664 is in a system where multiple devices
require analog-to-digital ground connections, the connection
should still be made at one point only, a star ground point,
which should be established as close as possible to the AD7664.
It is recommended to avoid running digital lines under the
device as these will couple noise onto the die. The analog ground
plane should be allowed to run under the AD7664 to avoid noise
coupling. Fast switching signals like
CNVST or clocks should be
shielded with digital ground to avoid radiating noise to other
sections of the board, and should never run near analog signal
paths. Crossover of digital and analog signals should be avoided.
Traces on different but close layers of the board should run at right
angles to each other. This will reduce the effect of feedthrough
through the board.
The power supplies lines to the AD7664 should use as large trace
as possible to provide low impedance paths and reduce the effect
of glitches on the power supplies lines. Good decoupling is also
important to lower the supplies impedance presented to the
AD7664 and reduce the magnitude of the supply spikes. Decou-
pling ceramic capacitors, typically 100 nF, should be placed on
each power supplies pins AVDD, DVDD, and OVDD close to,
and ideally right up against, these pins and their corresponding
ground pins. Additionally, low ESR 10
µF capacitors should be
located in the vicinity of the ADC to further reduce low frequency
ripple.
The DVDD supply of the AD7664 can be either a separate supply
or come from the analog supply AVDD or the digital interface
supply OVDD. When the system digital supply is noisy, or fast
switching digital signals are present, it is recommended that if no
separate supply available, connect the DVDD digital supply to
the analog supply, AVDD, through an RC filter as shown in
Figure 5, and connect the system supply to the interface digital
supply, OVDD, and the remaining digital circuitry. When DVDD
is powered from the system supply, it is useful to insert a bead
to further reduce high-frequency spikes.
U1
2.5V REF
ANALOG
INPUT
R2
R3
R4
100nF
R1
C
F
U2
C
REF
IN
INGND
REF
REFGND
100nF
AD7664
Figure 23. Using the AD7664 in 16-Bit Bipolar and/or
Wider Input Ranges
Table II. Component Values and Input Ranges
Input Range
R1
R2
R3
R4
±10 V
250
2 k
10 k
8 k
±5 V
500
2 k
10 k
6.67 k
0 V to 5 V
1 k
1 k
None
0
The AD7664 has five different ground pins: INGND, REFGND,
AGND, DGND, and OGND. INGND is used to sense the ana-
log input signal. REFGND senses the reference voltage and
should be a low impedance return to the reference because it
carries pulsed currents. AGND is the ground to which most
internal ADC analog signals are referenced. This ground must
be connected with the least resistance to the analog ground
plane. DGND must be tied to the analog or digital ground plane
depending on the configuration. OGND is connected to the
digital system ground.
Evaluating the AD7664 Performance
A recommended layout for the AD7664 is outlined in the
evaluation board for the AD7664. The evaluation board pack-
age includes a fully assembled and tested evaluation board,
documentation, and software for controlling the board from a
PC via the Eval-Control Board.
REV. 0
AD7664
19
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead Quad Flatpack (LQFP)
(ST-48)
0.039 (1.00)
REF
TOP VIEW
(PINS DOWN)
1
12
13
25
24
36
37
48
0.280 (7.1)
0.276 (7.0) SQ
0.272 (6.9)
0.362 (9.19)
0.354 (9.00) SQ
0.346 (8.79)
0.010 (0.26)
0.007 (0.18)
0.006 (0.15)
0.023 (0.58)
0.020 (0.50)
0.017 (0.42)
SEATING
PLANE
0
MIN
0.007 (0.177)
0.005 (0.127)
0.004 (0.107)
0.006 (0.15)
0.004 (0.10)
0.002 (0.05)
0.028 (0.7)
0.020 (0.5)
0.012 (0.3)
0.067 (1.70)
0.059 (1.50)
0.055 (1.40)
7
3.5
0
0.057 (1.45)
0.055 (1.40)
0.053 (1.35)
C020467.57/00 (rev. 0)
PRINTED IN U.S.A.
PDF 
ZIP