REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

AD7545A

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 2000

CMOS 12-Bit

Buffered Multiplying DAC

FUNCTIONAL BLOCK DIAGRAM

FEATURES
Improved Version of AD7545
Fast Interface Timing
All Grades 12-Bit Accurate
20-Lead DIP and Surface Mount Packages
Low Cost

PIN CONFIGURATIONS

DIP/SOIC

LCCC

PLCC

GENERAL DESCRIPTION

The AD7545A, a 12-bit CMOS multiplying DAC with internal
data latches, is an improved version of the industry standard
AD7545. This new design features a

WR pulse width of 100 ns,

which allows interfacing to a much wider range of fast 8-bit and
16-bit microprocessors. It is loaded by a single 12-bit-wide word
under the control of the

CS and WR inputs; tying these control

inputs low makes the input latches transparent, allowing unbuf-
fered operation of the DAC.

REV. C

AD7545ASPECIFICATIONS

= +5 V

= +15 V

Limits

Parameter

Version

= + 25 C

MIN

MAX

= + 25 C

MIN

MAX

Units

Test Conditions/Comments

STATIC PERFORMANCE

Resolution

All

Bits

Relative Accuracy

K, B, T

±1/2

LSB max

L, C, U

±1/2

LSB max

Endpoint Measurement

Differential Nonlinearity

All

±1

LSB max

All Grades Guaranteed 12-Bit
Monotonic Over Temperature

Gain Error

K, B, T

±3

±4

±3

±4

LSB max

Measured Using Internal R

L, C, U

±1

±2

±1

±2

LSB max

DAC Register Loaded with All 1s.

Gain Temperature Coefficient

All

±5

ppm/

°C max

Gain/Temperature

All

±2

ppm/

°C typ

DC Supply Rejection

Gain/V

All

0.002

0.004

0.002

0.004

% per % max

±5%

Output Leakage Current at OUT1

K, L

nA max

DB0DB11 = 0 V;

WR, CS = 0 V

B, C

nA max

T, U

200

nA max

DYNAMIC PERFORMANCE

Current Settling Time

All

µs max

To 1/2 LSB. OUT1 Load = 100

EXT

= 13 pF. DAC Output Measured

from Falling Edge of

WR, CS = 0 V.

Propagation Delay

(from Digital

Input Change to 90%
of Final Analog Output)

All

200

150

ns max

OUT1 Load = 100

, C

EXT

= 13 pF

Digital-to-Analog Glitch Impulse

All

nV sec typ

REF

= AGND. OUT1 Load = 100

Alternately Loaded with All 0s and 1s.

AC Feedthrough

2, 4

At OUT1

All

mV p-p typ

REF

±10 V, 10 kHz Sine Wave

REFERENCE INPUT

Input Resistance

All

min

Input Resistance TC = 300 ppm/

°C typ

(Pin 19 to GND)

max

Typical Input Resistance = 15 k

ANALOG OUTPUTS

Output Capacitance

OUT1

All

pF max

DB0DB11 = 0 V,

WR, CS = 0 V

OUT1

150

pF max

DB0DB11 = V

WR, CS = 0 V

DIGITAL INPUTS

Input High Voltage

All

2.4

13.5

V min

Input Low Voltage

All

0.8

1.5

V max

Input Current

All

±1

±10

±1

±10

µA max

= 0 or V

Input Capacitance

DB0DB11,

WR, CS

All

pF max

SWITCHING CHARACTERISTICS

Chip Select to Write Setup Time

K, B, L, C

100

130

ns min

See Timing Diagram

T, U

100

170

ns min

Chip Select to Write Hold Time

All

ns min

Write Pulse Width

K, B, L, C

100

130

ns min

, T

T, U

100

170

ns min

Data Setup Time

All

100

150

ns min

Data Hold Time

All

ns min

POWER SUPPLY

All

±5% For Specified Performance

All

mA max

All Digital Inputs V

or V

100

µA max

All Digital Inputs 0 V or V

µA typ

All Digital Inputs 0 V or V

NOTES

Temperature range as follows: K, L Versions = 0

°C to +70°C; B, C Versions = 25°C to +85°C; T, U Versions = 55°C to +125°C.

Sample tested to ensure compliance.

DB0DB11 = 0 V to V

or V

to 0 V.

Feedthrough can be further reduced by connecting the metal lid on the ceramic package to DGND.

Logic inputs are MOS gates. Typical input current (+25

°C) is less than 1 nA.

Specifications subject to change without notice.

REF

= 10 V, V

OUT1

= O V, AGND = DGND unless otherwise noted)

AD7545A

REV. C

ABSOLUTE MAXIMUM RATINGS*

= + 25

°C unless otherwise noted)

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, +17 V

Digital Input Voltage to DGND . . . . . . . 0.3 V, V

+0.3 V

RFB

, V

REF

to DGND . . . . . . . . . . . . . . . . . . . . . . . . .

±25 V

PIN1

to DGND . . . . . . . . . . . . . . . . . . . . 0.3 V, V

+0.3 V

AGND to DGND . . . . . . . . . . . . . . . . . . 0.3 V, V

+0.3 V

Power Dissipation (Any Package) to 75

°C . . . . . . . . . 450 mW

Derates above 75

°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C

Operating Temperature Range

Commercial (KN, LN, KP, LP) Grades . . . 0

°C to +70°C

Industrial (BQ, CQ, BE, CE) Grades . . . . 25

°C to +85°C

Extended (TQ, UQ, TE, UE) Grades . . . 55

°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . 65

°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300

°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-
static fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are removed.

ORDERING GUIDE

Relative

Gain

Temperature

Accuracy

Error

Package

Model

Range

MIN

MAX

MIN

MAX

Options

AD7545AKN

°C to +70°C

±1/2

±4

N-20

AD7545ALN

°C to +70°C

±1/2

±2

N-20

AD7545AKR

°C to +70°C

±1/2

±4

R-20

AD7545AKP

°C to +70°C

±1/2

±4

P-20A

AD7545ALP

°C to +70°C

±1/2

±2

P-20A

AD7545ABQ

°C to +85°C

±1/2

±4

Q-20

AD7545ACQ

°C to +85°C

±1/2

±2

Q-20

AD7545ABE

°C to +85°C

±1/2

±4

E-20A

AD7545ACE

°C to +85°C

±1/2

±2

E-20A

AD7545ATQ

°C to +125°C ±1/2

±4

Q-20

AD7545AUQ

°C to +125°C ±1/2

±2

Q-20

AD7545ATE

°C to +125°C ±1/2

±4

E-20A

AD7545AUE

°C to +125°C ±1/2

±2

E-20A

NOTES

To order MIL-STD-883, Class B process parts, add /883B to part number.

Contact local sales office for military data sheet.

E = Leadless Ceramic Chip Carrier (LCCC); N = Plastic DIP; P = Plastic

Leaded Chip Carrier (PLCC); Q = Cerdip; R = Small Outline IC.

WRITE CYCLE TIMING DIAGRAM

WARNING!

ESD SENSITIVE DEVICE

AD7545A

REV. C

CIRCUIT INFORMATION--D/A CONVERTER SECTION

Figure 1 shows a simplified circuit of the D/A converter section
of the AD7545A, and Figure 2 gives an approximate equivalent
circuit. Note that the ladder termination resistor is connected to
AGND. R is typically 15 k

The binary weighted currents are switched between the OUT1
bus line and AGND by N-channel switches, thus maintaining a
constant current in each ladder leg independent of the switch
state.

Figure 1. Simplified D/A Circuit of AD7545A

The capacitance at the OUT1 bus line, C

OUT1

, is code-

dependent and varies from 70 pF (all switches to AGND) to
150 pF (all switches to OUT1).

One of the current switches is shown in Figure 2. The input
resistance at V

REF

(Figure 1) is always equal to R. Since R

the V

REF

pin is constant, the reference terminal can be driven by

a reference voltage or a reference current, ac or dc, of positive or
negative polarity. (If a current source is used, a low temperature
coefficient external R

is recommended to define scale factor.)

Figure 2. N-Channel Current Steering Switch

CIRCUIT INFORMATION--DIGITAL SECTION

Figure 3 shows the digital structure for one bit.

The digital signals CONTROL and

CONTROL are generated

from

CS and WR.

Figure 3. Digital Input Structure

The input buffers are simple CMOS inverters designed such
that when the AD7545A is operated with V

= 5 V, the buffers

convert TTL input levels (2.4 V and 0.8 V) into CMOS logic
levels. When V

is in the region of 2.0 volts to 3.5 volts, the

input buffers operate in their linear region and draw current
from the power supply. To minimize power supply currents it is
recommended that the digital input voltages be as close to the
supply rails (V

and DGND) as is practically possible.

The AD7545A may be operated with any supply voltage in the
range 5

15 volts. With V

= +15 V the input logic

levels are CMOS compatible only, i.e., 1.5 V and 13.5 V.

BASIC APPLICATIONS

Figures 4 and 5 show simple unipolar and bipolar circuits using
the AD7545A. Resistor R1 is used to trim for full scale. The L,
C, U grades have a guaranteed maximum gain error of

±1 LSB

at +25

°C, and in many applications it should be possible to

dispense with gain trim resistors altogether. Capacitor C1 pro-
vides phase compensation and helps prevent overshoot and
ringing when using high speed op amps. Note that all the cir-
cuits of Figures 4, 5 and 6 have constant input impedance at the
V

REF

terminal.

The circuit of Figure 4 can either be used as a fixed reference
D/A converter so that it provides an analog output voltage in the
range 0 to V

(note the inversion introduced by the op amp)

or V

can be an ac signal in which case the circuit behaves as

an attenuator (2-Quadrant Multiplier). V

can be any voltage

in the range 20

+20 volts (provided the op amp can

handle such voltages) since V

REF

is permitted to exceed V

Table II shows the code relationship for the circuit of Figure 4.

Figure 4. Unipolar Binary Operation

Table I. Recommended Trim Resistor Values vs. Grades

Trim Resistor

K/B/T

L/C/U

200

100

Table II. Unipolar Binary Code Table for Circuit of Figure 4

Binary Number in
DAC Register

Analog Output

1 1 1 1

4095

4096

1 0 0 0

0 0 0 0

2048

4096

= 1/2 V

0 0 0 0

0 0 0 1

4096

0 0 0 0

0 Volts

AD7545A

REV. C

Figure 5 and Table III illustrate the recommended circuit and
code relationship for bipolar operation. The D/A function itself
uses offset binary code and inverter U

on the MSB line con-

verts twos complement input code to offset binary code. If ap-
propriate, inversion of the MSB may be done in software using
an exclusive OR instruction and the inverter omitted. R3, R4
and R5 must be selected to match within 0.01%, and they
should be the same type of resistor (preferably wire-wound or
metal foil), so that their temperature coefficients match. Mis-
match of R3 value to R4 causes both offset and full-scale error.
Mismatch of R5 to R4 and R3 causes full-scale error.

Figure 5. Bipolar Operation (Twos Complement Code)

Table III. Twos Complement Code Table for Circuit of
Figure 5

Data Input

Analog Output

0 1 1 1

1 1 1 1

2047

2048

0 0 0 0

0 0 0 1

2048

0 0 0 0

0 Volts

1 1 1 1

2048

1 0 0 0

0 0 0 0

2048

Figure 6 and Table IV show an alternative method of achieving
bipolar output. The circuit operates with sign plus magnitude
code and has the advantage that it gives 12-bit resolution in
each quadrant compared with 11-bit resolution per quadrant for
the circuit of Figure 5. The AD7592 is a fully protected CMOS
change-over switch with data latches. R4 and R5 should match
each other to 0.01% to maintain the accuracy of the D/A con-
verter. Mismatch between R4 and R5 introduces a gain error.
Refer to Reference 1 (supplemental application material) for
additional information on these circuits.

Figure 6. 12-Bit Plus Sign Magnitude Converter

Table IV. 12-Bit Plus Sign Magnitude Code Table for Circuit
of Figure 6

Sign

Binary Numbers in

Bit

DAC Register

Analog Output

1 1 1 1 1 1 1 1

1 1 1 1

+ V

4095

4096

0 0 0 0 0 0 0 0

0 0 0 0

0 Volts

0 0 0 0 0 0 0 0

0 0 0 0

0 Volts

1 1 1 1 1 1 1 1

1 1 1 1

4095

4096

Note: Sign bit of "0" connects R3 to GND.

APPLICATIONS HINTS

Output Offset: CMOS D/A converters such as Figures 4, 5
and 6 exhibit a code dependent output resistance which, in turn,
can cause a code dependent error voltage at the output of the
amplifier. The maximum amplitude of this error, which adds
to the D/A converter nonlinearity, depends on V

, where V

is the amplifier input offset voltage. To maintain specified accuracy
with V

REF

at 10 V, it is recommended that V

be no greater than

0.25 mV, or (25

× 10

) (V

REF

), over the temperature range of

operation. Suitable op amps are AD517 and AD711. The AD517
is best suited for fixed reference applications with low band-
width requirements: it has extremely low offset (150

µV max for

lowest grade) and in most applications will not require an offset
trim. The AD711 has a much wider bandwidth and higher slew
rate and is recommended for multiplying and other applications
requiring fast settling. An offset trim on the AD711 may be
necessary in some circuits.

General Ground Management: AC or transient voltages
between AGND and DGND can cause noise injection into the
analog output. The simplest method of ensuring that voltages at
AGND and DGND are equal is to tie AGND and DGND
together at the AD7545A. In more complex systems where the
AGND and DGND intertie is on the backplane, it is recom-
mended that two diodes be connected in inverse parallel between
the AD7545A AGND and DGND pins (1N914 or equivalent).

AD7545A

REV. C

Invalid Data: When

WR and CS are both low, the latches are

transparent and the D/A converter inputs follow the data inputs.
In some bus systems, data on the data bus is not always valid for
the whole period during which

WR is low, and as a result invalid

data can briefly occur at the D/A converter inputs during a write
cycle. Such invalid data can cause unwanted signals or glitches
at the output of the D/A converter. The solution to this prob-
lem, if it occurs, is to retime the write pulse,

WR, so it only

occurs when data is valid.

Digital Glitches: Digital glitches result due to capacitive cou-
pling from the digital lines to the OUT1 and AGND terminals.
This should be minimized by screening the analog pins of the
AD7545A (Pins 1, 2, 19, 20) from the digital pins by a ground
track run between Pins 2 and 3 and between Pins 18 and 19 of
the AD7545A.

Note how the analog pins are at one end (DIP) or side (LCC
and PLCC) of the package and separated from the digital pins
by V

and DGND to aid screening at the board level. On-chip

capacitive coupling can also give rise to crosstalk from the digital-
to-analog sections of the AD7545A, particularly in circuits with
high currents and fast rise and fall times. This type of crosstalk is
minimized by using V

= +5 volts. However, great care should

be taken to ensure that the +5 V used to power the AD7545A is
free from digitally induced noise.

Temperature Coefficients: The gain temperature coefficient
of the AD7545A has a maximum value of 5 ppm/

°C and a typi-

cal value of 2 ppm/

°C. This corresponds to worst case gain shifts

of 2 LSBs and 0.8 LSBs respectively over a 100

°C temperature

range. When trim resistors R1 and R2 (such as in Figure 4) are
used to adjust full-scale range, the temperature coefficient of R1
and R2 should also be taken into account. The reader is referred
to Analog Devices Application Note "Gain Error and Gain
Temperature Coefficient to CMOS Multiplying DACs," Publi-
cation Number E630c53/86.

SINGLE SUPPLY OPERATION
The ladder termination resistor of the AD7545A (Figure 1) is
connected to AGND. This arrangement is particularly suitable
for single supply operation because OUT1 and AGND may be
biased at any voltage between DGND and V

. OUT1 and

AGND should never go more than 0.3 volts less than DGND or
an internal diode will be turned on and a heavy current may
flow that will damage the device. (The AD7545A is, however,
protected from the SCR latchup phenomenon prevalent in many
CMOS devices.)

Figure 7 shows the AD7545A connected in a voltage switching
mode. OUT1 is connected to the reference voltage and AGND
is connected to DGND. The D/A converter output voltage is
available at the V

REF

pin and has a constant output impedance

equal to R. R

is not used in this circuit and should be tied to

OUT1 to minimize stray capacitance effects.

Figure 7. Single Supply Operation Using Voltage Switch-
ing Mode

The loading on the reference voltage source is code-dependent
and the response time of the circuit is often determined by the
behavior of the reference voltage with changing load conditions.
To maintain linearity, the voltages at OUT1 and AGND should
remain within 2.5 volts of each other, for a V

of 15 volts. If

is reduced from 15 V, or the differential voltage between

OUT1 and AGND is increased to more than 2.5 V, the differ-
ential nonlinearity of the DAC will increase and the linearity of
the DAC will be degraded. Figures 8 and 9 show typical curves
illustrating this effect for various values of reference voltage and
V

. If the output voltage is required to be offset from ground

by some value, then OUT1 and AGND may be biased up. The
effect on linearity and differential nonlinearity will be the same
as reducing V

by the amount of the offset.

Figure 8. Differential Nonlinearity vs. V

for Figure 7

Circuit. Reference Voltage = 2.5 Volts. Shaded Area Shows
Range of Values of Differential Nonlinearity that Typically
Occur for all Grades.

Figure 9. Differential Nonlinearity vs. Reference Voltage
for Figure 7 Circuit. V

= 15 Volts. Shaded Area Shows

Range of Values of Differential Nonlinearity that Typically
Occur for all Grades.

AD7545A

REV. C

The circuits of Figures 4, 5 and 6 can all be converted to single
supply operation by biasing AGND to some voltage between
V

and DGND. Figure 10 shows the 2s Complement Bipolar

circuit of Figure 5 modified to give a range from +2 V to +8 V
about a "pseudo-analog ground" of 5 V. This voltage range
would allow operation from a single V

of +10 V to +15 V.

The AD584 pin-programmable reference fixes AGND at +5 V.
V

is set at +2 V by means of the series resistors R1 and R2.

There is no need to buffer the V

REF

input to the AD7545A with

an amplifier because the input impedance of the D/A converter
is constant. Note, however, that since the temperature coefficient
of the D/A reference input resistance is typically 300 ppm/

°C,

applications which experience wide temperature variations may
require a buffer amplifier to generate the +2.0 V at the AD7545A
V

REF

pin. Other output voltage ranges can be obtained by changing

R4 to shift the zero point and (R1 + R2) to change the slope, or
gain of the D/A transfer function. V

must be kept at least 5 V

above OUT1 to ensure that linearity is preserved.

Figure 10. Single Supply "Bipolar" 2s Complement D/A
Converter

MICROPROCESSOR INTERFACING OF THE AD7545A
The AD7545A can interface directly to both 8- and 16-bit
microprocessors via its 12-bit wide data latch using standard

and

WR control signals.

A typical interface circuit for an 8-bit processor is shown in
Figure 11. This arrangement uses two memory addresses, one
for the lower 8 bits of data to the DAC and one for the upper 4
bits of data into the DAC via the latch.

Figure 11. 8-Bit Processor to AD7545 Interface

Figure 12 shows an alternative approach for use with 8-bit pro-
cessors which have a full 16-bit wide address bus such as 6800,
8080, Z80. This technique uses the 12 lower address lines of the
processor address bus to supply data to the DAC, thus each
AD7545A connected in this way uses 4k bytes of address loca-
tions. Data is written to the DAC using a single memory write
instruction. The address field of the instruction is organized so
that the lower 12 bits contain the data for the DAC and the
upper 4 bits contain the address of the 4k block at which the
DAC resides.

Figure 12. Connecting the AD7545A to 8-Bit Processors
via the Address Bus

SUPPLEMENTAL APPLICATION MATERIAL

For further information on CMOS multiplying D/A converters
the reader is referred to the following texts:

Reference 1
CMOS DAC Application Guide available from Analog Devices,
Publication Number G872a-15-4/86.

Reference 2
Gain Error and Gain Temperature Coefficient of CMOS
Multiplying DACs Application Note, Publication Number
E630c53/86.

Reference 3
Analog-Digital Conversion Handbook (Third Edition) available
from Prentice-Hall.

Part Number AD7545A