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Part Number AD7396

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REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD7396/AD7397
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
3 V, Parallel Input
Dual 12-Bit /10-Bit DACs
FUNCTIONAL BLOCK DIAGRAM
DACA
REGISTER
12
INPUTA
REGISTER
DACB
REGISTER
12
INPUTB
REGISTER
AD7396
12-BIT
DACA
12-BIT
DACB
1
DATA
LDA
CS
A/
B
DGND
RS
SHDN
V
DD
V
OUTA
V
REF
V
OUTB
AGND
LDB
12
FEATURES
Micropower: 100 A/DAC
0.1 A Typical Power Shutdown
Single Supply +2.7 V to +5.5 V Operation
Compact 1.1 mm Height TSSOP 24-Lead Package
AD7396: 12-Bit Resolution
AD7397: 10-Bit Resolution
0.9 LSB Differential Nonlinearity Error
APPLICATIONS
Automotive Output Span Voltage
Portable Communications
Digitally Controlled Calibration
PC Peripherals
GENERAL DESCRIPTION
The AD7396/AD7397 series of dual, 12-bit and 10-bit voltage-
output digital-to-analog converters are designed to operate from
a single +3 V supply. Built using a CBCMOS process, these
monolithic DACs offer the user low cost and ease of use in
single supply +3 V systems. Operation is guaranteed over the
supply voltage range of +2.7 V to +5.5 V, making this device
ideal for battery operated applications.
A 12-bit wide data latch loads with a 45 ns write time allowing
interface to fast processors without wait states. The double
buffered input structure allows the user to load the input
registers one at a time, then a single load strobe tied to both
LDA+LDB inputs will simultaneously update both DAC out-
puts.
LDA and LDB can also be independently activated to
immediately update their respective DAC registers. An address
input (A/
B) decodes DACA or DACB when the chip select CS
input is strobed. Additionally, an asynchronous
RS input sets
the output to zero-scale at power on or upon user demand.
Power shutdown to submicroamp levels is directly controlled by
the active low
SHDN pin. While in the power shutdown state
register data can still be changed even though the output buffer
is in an open circuit state. Upon return to the normal operating
state the latest data loaded in the DAC register will establish the
output voltage.
Both parts are offered in the same pinout, allowing users to
select the amount of resolution appropriate for their applications
without circuit card changes.
The AD7396/AD7397 are specified for operation over the ex-
tended industrial (­40
°
C to +85
°
C) temperature range. The
AD7397AR is specified for the ­40
°
C to +125
°
C automotive
temperature range. AD7396/AD7397s are available in plastic
DIP, and 24-lead SOIC packages. The AD7397ARU is avail-
able for ultracompact applications in a thin 1.1 mm height
TSSOP 24-lead package.
CODE ­ Decimal
1.0
0
DNL ­ LSB
0.8
0.6
0.4
0.2
0.0
­0.2
­0.4
­0.6
­0.8
­1.0
512
1024
1536
2048
2560
3072
3584
4096
V
DD
= +3V
V
REF
= +2.5V
T
A
= +25 C, +85 C, ­55 C
SUPERIMPOSED
Figure 1. DNL vs. Digital Code at Temperature
­2­
REV. 0
AD7396/AD7397­SPECIFICATIONS
Parameter
Symbol
Conditions
+3 V 10% +5 V 10% Units
STATIC PERFORMANCE
Resolution
1
N
12
12
Bits
Relative Accuracy
2
INL
T
A
= +25
°
C
±
1.75
±
1.75
LSB max
Relative Accuracy
2
INL
T
A
= ­40
°
C, +85
°
C
±
2.0
±
2.0
LSB max
Differential Nonlinearity
2
DNL
T
A
= +25
°
C, Monotonic
±
0.9
±
0.9
LSB max
Differential Nonlinearity
2
DNL
Monotonic
±
1
±
1
LSB max
Zero-Scale Error
V
ZSE
Data = 000
H
, T
A
= +25
°
C, +85
°
C
4.0
4.0
mV max
Zero-Scale Error
V
ZSE
Data = 000
H
, T
A
= ­40
°
C
8.0
8.0
mV max
Full-Scale Voltage Error
V
FSE
T
A
= +25
°
C, +85
°
C, Data = FFF
H
±
8
±
8
mV max
Full-Scale Voltage Error
V
FSE
T
A
= ­40
°
C, Data = FFF
H
±
20
±
20
mV max
Full-Scale Tempco
3
TCV
FS
­45
­45
ppm/
°
C typ
REFERENCE INPUT
V
REF
Range
V
REF
0/V
DD
0/V
DD
V min/max
Input Resistance
R
REF
2.5
2.5
M
typ
4
Input Capacitance
3
C
REF
5
5
pF typ
ANALOG OUTPUT
Output Current (Source)
I
OUT
Data = 800
H
,
V
OUT
= 5 LSB
1
1
mA typ
Output Current (Sink)
I
OUT
Data = 800
H
,
V
OUT
= 5 LSB
3
3
mA typ
Capacitive Load
3
C
L
No Oscillation
100
100
pF typ
LOGIC INPUTS
Logic Input Low Voltage
V
IL
0.5
0.8
V max
Logic Input High Voltage
V
IH
V
DD
­ 0.6
4.0
V min
Input Leakage Current
I
IL
10
10
µ
A max
Input Capacitance
3
C
IL
10
10
pF max
INTERFACE TIMING
3, 5
Chip Select Write Width
t
CS
45
35
ns min
DAC Select Setup
t
AS
30
15
ns min
DAC Select Hold
t
AH
0
0
ns min
Data Setup
t
DS
30
15
ns min
Data Hold
t
DH
20
10
ns min
Load Setup
t
LS
20
20
ns min
Load Hold
t
LH
10
10
ns min
Load Pulsewidth
t
LDW
30
30
ns min
Reset Pulsewidth
t
RSW
40
30
ns min
AC CHARACTERISTICS
Output Slew Rate
SR
Data = 000
H
to FFF
H
to 000
H
0.05
0.05
V/
µ
s typ
Settling Time
6
t
S
To
±
0.1% of Full Scale
70
60
µ
s typ
Shutdown Recovery Time
t
SDR
90
80
µ
s typ
DAC Glitch
Q
Code 7FF
H
to 800
H
to 7FF
H
65
65
nV/s typ
Digital Feedthrough
Q
15
15
nV/s typ
Feedthrough
V
OUT
/V
REF
V
REF
= 1.5 V
DC
+1 V p-p
,
Data = 000
H
, f = 100 kHz
­63
­63
dB typ
SUPPLY CHARACTERISTICS
Power Supply Range
V
DD RANGE
DNL <
±
1 LSB
2.7/5.5
2.7/5.5
V min/max
Positive Supply Current
I
DD
V
IL
= 0 V, No Load
125/200
125/200
µ
A typ/max
Shutdown Supply Current
I
DD_SD
SHDN = 0, V
IL
= 0 V, No Load
0.1/1.5
0.1/1.5
µ
A typ/max
Power Dissipation
P
DISS
V
IL
= 0 V, No Load
600
1000
µ
W max
Power Supply Sensitivity
PSS
V
DD
=
±
5%
0.006
0.006
%/% max
NOTES
1
One LSB = V
REF
/4096 V for the 12-bit AD7396.
2
The first two codes (000
H
, 001
H
) are excluded from the linearity error measurement.
3
These parameters are guaranteed by design and not subject to production testing.
4
Typicals represent average readings measured at +25
°
C.
5
All input control signals are specified with t
R
= t
F
= 2 ns (10% to 90% of +3 V) and timed from a voltage level of +1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
AD7396 12-BIT
ELECTRICAL CHARACTERISTICS
(@ V
REF IN
= +2.5 V, ­40 C < T
A
< +85 C, unless otherwise noted)
­3­
REV. 0
AD7396/AD7397
Parameter
Symbol
Conditions
+3 V 10% +5 V 10%
Units
STATIC PERFORMANCE
Resolution
1
N
10
10
Bits
Relative Accuracy
2
INL
T
A
= +25
°
C
±
1.75
±
1.75
LSB max
Relative Accuracy
2
INL
T
A
= ­40
°
C, +85
°
C, +125
°
C
±
2.0
±
2.0
LSB max
Differential Nonlinearity
2
DNL
Monotonic
±
1
±
1
LSB max
Zero-Scale Error
V
ZSE
Data = 000
H
9.0
9.0
mV max
Full-Scale Voltage Error
V
FSE
T
A
= +25
°
C, +85
°
C, +125
°
C, Data = 3FF
H
±
42
±
42
mV max
Full-Scale Voltage Error
V
FSE
T
A
= ­40
°
C, Data = 3FF
H
±
48
±
48
mV max
Full-Scale Tempco
3
TCV
FS
­45
­45
ppm/
°
C typ
REFERENCE INPUT
V
REF
Range
V
REF
0/V
DD
0/V
DD
V min/max
Input Resistance
R
REF
2.5
2.5
M
typ
4
Input Capacitance
3
C
REF
5
5
pF typ
ANALOG OUTPUT
Output Current (Source)
I
OUT
Data = 200
H
,
V
OUT
= 5 LSB
1
1
mA typ
Output Current (Sink)
I
OUT
Data = 200
H
,
V
OUT
= 5 LSB
3
3
mA typ
Capacitive Load
3
C
L
No Oscillation
100
100
pF typ
LOGIC INPUTS
Logic Input Low Voltage
V
IL
0.5
0.8
V max
Logic Input High Voltage
V
IH
V
DD
­ 0.6
4.0
V min
Input Leakage Current
I
IL
10
10
µ
A max
Input Capacitance
3
C
IL
10
10
pF max
INTERFACE TIMING
3, 5
Chip Select Write Width
t
CS
45
35
ns min
DAC Select Setup
t
AS
30
15
ns min
DAC Select Hold
t
AH
0
0
ns min
Data Setup
t
DS
30
15
ns min
Data Hold
t
DH
20
10
ns min
Load Setup
t
LS
20
20
ns min
Load Hold
t
LH
10
10
ns min
Load Pulsewidth
t
LDW
30
30
ns min
Reset Pulsewidth
t
RSW
40
30
ns min
AC CHARACTERISTICS
Output Slew Rate
SR
Data = 000
H
to 3FF
H
to 000
H
0.05
0.05
V/
µ
s typ
Settling Time
6
t
S
To
±
0.1% of Full Scale
70
60
µ
s typ
Shutdown Recovery Time
t
SDR
90
80
µ
s typ
DAC Glitch
Q
Code 7FF
H
to 800
H
to 7FF
H
65
65
nV/s typ
Digital Feedthrough
Q
15
15
nV/s typ
Feedthrough
V
OUT
/V
REF
V
REF
= 1.5 V
DC
+1 V p-p
,
Data = 000
H
, f = 100 kHz
­63
­63
dB typ
SUPPLY CHARACTERISTICS
Power Supply Range
V
DD RANGE
DNL <
±
1 LSB
2.7/5.5
2.7/5.5
V min/max
Positive Supply Current
I
DD
V
IL
= 0 V, No Load
125/200
125/200
µ
A typ/max
Shutdown Supply Current
I
DD_SD
SHDN = 0, V
IL
= 0 V, No Load
0.1/1.5
0.1/1.5
µ
A typ/max
Power Dissipation
P
DISS
V
IL
= 0 V, No Load
600
1000
µ
W max
Power Supply Sensitivity
PSS
V
DD
=
±
5%
0.006
0.006
%/% max
NOTES
1
One LSB = V
REF
/4096 V for the 10-bit AD7397.
2
The first two codes (000
H
, 001
H
) are excluded from the linearity error measurement.
3
These parameters are guaranteed by design and not subject to production testing.
4
Typicals represent average readings measured at +25
°
C.
5
All input control signals are specified with t
R
= t
F
= 2 ns (10% to 90% of +3 V) and timed from a voltage level of +1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
AD7397 10-BIT
ELECTRICAL CHARACTERISTICS
(@ V
REF IN
= +2.5 V, ­40 C < T
A
< +85 C, unless otherwise noted)
AD7396/AD7397
­4­
REV. 0
Table I. Control Logic Truth
CS
A/
B
LDA
LDB
RS
SHDN
Input Register
DAC Register
L
L
H
H
H
X
Write to B
Latched with Previous Data
L
H
H
H
H
X
Write to A
Latched with Previous Data
L
L
H
L
H
X
Write to B
B Transparent
L
H
L
H
H
X
Write to A
A Transparent
H
X
L
L
H
X
Latched
A and B Transparent
H
X
^
^
H
X
Latched
Latched with New Data from Input REG
X
X
X
X
L
X
Reset to Zero Scale
Reset to Zero Scale
H
X
X
X
^
X
Latched to Zero
Latched to Zero
^Denotes positive edge. The
SHDN pin has no effect on the digital interface data loading; however, while in the SHDN state (SHDN = 0) the output amplifiers V
OUTA
and V
OUTB
exhibit an open circuit condition. Note, the
LDx inputs are level-sensitive, the respective DAC registers are in a transparent state when LDx = "0."
t
CSW
1 LSB
ERROR BAND
t
AS
t
AH
CS
A/
B
t
DH
t
DS
t
LS
t
LH
t
LDW
t
RSW
t
S
t
S
LDA
,
LDB
RS
V
OUT
D0­D11
Figure 2. Timing Diagram
B REGISTER
1 OF 12
LATCHES
OF THE 2 INPUT
REGISTERS
TO DAC
REGISTERS
DBx
CS
A/
B
RS
Figure 3. Digital Control Logic
AD7396/AD7397
­5­
REV. 0
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7396/AD7397 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.3 V, +8 V
V
REF
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.3 V, V
DD
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . . ­0.3 V, +8 V
V
OUT
to GND . . . . . . . . . . . . . . . . . . . . . ­0.3 V, V
DD
+ 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . ­0.3 V, +2 V
I
OUT
Short Circuit to GND . . . . . . . . . . . . . . . . . . . . +50 mA
Package Power Dissipation . . . . . . . . . . . . . (T
J
max ­ T
A
)/
JA
Thermal Resistance
JA
24-Lead Plastic DIP Package (N-24) . . . . . . . . . . +63
°
C/W
24-Lead SOIC Package (R-24) . . . . . . . . . . . . . . . +70
°
C/W
24-Lead Thin Shrink Surface Mount (RU-24) . . +143
°
C/W
ORDERING GUIDE
Res
Temperature
Package
Package
Model
(LSB)
Ranges
Descriptions
Options
AD7396AN
12
­40
°
C to +85
°
C
24-Lead P-DIP
N-24
AD7396AR
12
­40
°
C to +85
°
C
24-Lead SOIC
R-24
AD7397AN
10
­40
°
C to +125
°
C
24-Lead P-DIP
N-24
AD7397AR
10
­40
°
C to +125
°
C
24-Lead SOIC
R-24
AD7397ARU
10
­40
°
C to +85
°
C
24-Lead Thin Shrink Small Outline Package (TSSOP)
RU-24
The AD7396/AD7397 contains 1365 transistors. The die size measures 89 mil
×
106 mil = 9434 sq mil.
Maximum Junction Temperature (T
J
max) . . . . . . . . . +150
°
C
Operating Temperature Range . . . . . . . . . . . ­40
°
C to +85
°
C
AD7397AN, AD7397AR Only . . . . . . . . ­40
°
C to +125
°
C
Storage Temperature Range . . . . . . . . . . . . ­65
°
C to +150
°
C
Lead Temperature
N-24 (Soldering, 10 sec) . . . . . . . . . . . . . . . . . . . . . . +300
°
C
R-24 (Vapor Phase, 60 sec) . . . . . . . . . . . . . . . . . . . . +215
°
C
RU-24 (Infrared, 15 sec) . . . . . . . . . . . . . . . . . . . . . . +224
°
C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
AD7396/AD7397
­6­
REV. 0
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
1
V
OUTA
DAC A Voltage Output.
2
AGND
Analog Ground.
3
DGND
Digital Ground.
4
LDA
Load DAC A Register Strobe. Transfers input register data to the DAC A register. Active
low inputs, Level sensitive latch. May be connected together with
LDB to double-buffer load
both DAC registers simultaneously.
5
SHDN
Power Shutdown Active Low Input. DAC register contents are saved as long as power stays
on the V
DD
pin.
6
RS
Resets Input and DAC Register to Zero Condition. Asynchronous active low input.
7­18
D0­D11
Twelve Parallel Input Data Bits. D11 = MSB Pin 18, D0 = LSB Pin 7, AD7396.
7, 8
NC
No Connect Pins 7 and 8 On the AD7397 Only.
9­18
D0­D9
Ten Parallel Input Data Bits. D9 = MSB Pin 18, D0 = LSB Pin 9, AD7397 Only.
19
CS
Chip Select Latch Enable, Active Low.
20
A/
B
DAC Input Register Address Select DACA = 1 or DACB = 0.
21
LDB
Load DAC B Register Strobe. Transfers input register data to the DAC B register. Active low
inputs, Level sensitive latch. May be connected together with
LDA to double-buffer load
both DAC registers simultaneously.
22
V
DD
Positive Power Supply Input. Specified range of operation +2.7 V to +5.5 V.
23
V
REF
DAC Reference Input Pin. Establishes DAC full-scale voltage.
24
V
OUTB
DAC B Voltage Output.
PIN CONFIGURATIONS
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD7396
D5
D4
D3
D2
D1
V
OUTA
AGND
DGND
LDA
D0
RS
SHDN
D6
D7
D8
D9
D10
V
OUTB
V
REF
V
DD
LDB
D11
CS
A/
B
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD7397
D3
D2
D1
D0
NC
V
OUTA
AGND
DGND
LDA
NC
RS
SHDN
D4
D5
D6
D7
D8
V
OUTB
V
REF
V
DD
LDB
D9
CS
A/
B
NC = NO CONNECT
AD7396/AD7397
­7­
REV. 0
CODE ­ Decimal
1.5
0
INL ­ LSB
1.0
0.5
0.0
­0.5
­1.0
­1.5
512 1024 1536 2048 2560 3072 3584 4096
V
DD
= +3V
V
REF
= +2.5V
T
A
= +25 C, +85 C
T
A
= ­55 C
AD7396
Figure 4. AD7396 INL vs. Code and
Temperature
CODE ­ Decimal
1.0
0
DNL ­ LSB
0.8
0.6
0.4
0.2
0.0
­0.2
­0.4
­0.6
­0.8
­1.0
128
256
384 512
640
768
896 1024
V
DD
= +2.7V
V
REF
= +2.5V
T
A
= +25 C, +85 C, ­55 C
SUPERIMPOSED
AD7397
Figure 7. AD7397 DNL vs. Code and
Temperature
V
REF
­ Volts
INL ­ LSB
1.5
0
1.0
0.5
0
­0.5
­1.0
­1.5
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
V
DD
= +5V
T
A
= +25 C
CODE = HALF SCALE
Figure 10. INL Error vs. Reference
Voltage
Typical Performance Characteristics­
CODE ­ Decimal
1.0
0
INL ­ LSB
0.8
0.6
0.4
0.2
0.0
­0.2
­0.4
­0.6
­0.8
­1.0
128
256
384
512
640
768
896 1024
T
A
= +25 C, +85 C
T
A
= ­55 C
V
DD
= +2.7V
V
REF
= +2.5V
AD7397
Figure 5. AD7397 INL vs. Code and
Temperature
FULL-SCALE OUTPUT TEMPCO
HISTOGRAM ­ ppm/ C
60
­55
FREQUENCY
­50
­45
­40
40
20
0
­35
­30
SS = 200 UNITS
V
DD
= +2.7V
V
REF
= +2.5V
T
A
= ­40 C TO +85 C
AD7396
Figure 8. AD7396 Full-Scale Tempco
Histogram
V
REF
­ V
FSE ­ mV
40
20
­40
0
1
5
2
3
4
0
­20
40
20
0
­20
­40
FSE ­ LSB
V
DD
= +5V
T
A
= +25 C
FSE (LSB) = FSE (V) 4096/V
REF
(V)
AD7396
Figure 11. Full-Scale Error vs. Refer-
ence Voltage
TOTAL UNADJUSTED ERROR
HISTOGRAM ­ LSB
30
­5
FREQUENCY
0
5
10
20
10
0
SS = 200 UNITS
T
A
= +25 C
V
DD
= +2.7V
V
REF
= +2.5V
AD7397
Figure 6. AD7397 TUE Histogram
SS = 200 UNITS
V
DD
= +2.7V
V
REF
= +2.5V
T
A
= ­40 C TO +85 C
FULL-SCALE TEMPCO ­ ppm/ C
FREQUENCY
100
40
20
0
­70
­60
­50
­40
­30
AD7397
60
80
Figure 9. AD7397 Full-Scale Tempco
Histogram
FREQUENCY ­ Hz
OUTPUT NOISE DENSITY ­
V/ Hz
10
1
8
6
4
2
0
10
100
1k
10k
100k
V
DD
= +5V
V
REF
= +2.5V
T
A
= +25 C
Figure 12. Output Noise Voltage
Density vs. Frequency
AD7396/AD7397
­8­
REV. 0
FREQUENCY ­ Hz
GAIN ­ dB
0
­10
­20
­30
­40
­50
100
1k
10k
100k
1M
­5
­15
­25
­35
­45
V
DD
= +3V
CODE = FULL SCALE
Figure 13. Reference Multiplying
Gain vs. Frequency
V
DD
­ V
2
LOGIC THRESHOLD ­ V
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
3
4
5
6
7
T
A
= +25 C
V
LOGIC
FROM
LOW TO HIGH
V
LOGIC
FROM
HIGH TO LOW
Figure 16. Logic Threshold Voltage
vs. V
DD
TEMPERATURE ­ C
­40
I
DD
­
A
170
160
150
140
130
120
110
100
­20
0
20
40
60
V
REF
= +2.5V
80
90
80
100 120 140
V
DD
= +3.6V, V
LOGIC
= +2.4V
V
DD
= +3V, V
LOGIC
= +3V
V
DD
= +5V, V
LOGIC
= +5V
Figure 19. I
DD
vs. Temperature
TIME ­ 2 s/DIV
V
OUT
­ Volts
1.262
1.257
1.252
1.247
1.242
1.237
V
DD
= +5V
V
REF
= +2.5V
T
A
= +25 C
CODE = 800
H
TO 7FF
H
5mV/DIV
Figure 14. Midscale Transition
Performance
V
OUT
­ mV
­120
I
OUT
CURRENT SOURCING ­ mA
35
30
25
20
15
10
5
0
­100
­80
­60
­40
­20
V
REF
= +2.5V
T
A
= +25 C
0
V
DD
= +5V
V
DD
= +3V
Figure 17. I
OUT
Source Current vs.
V
OUT
V
REF
­ Volts
0
I
DD
­
A
200
180
160
140
120
100
80
60
1
2
3
4
5
T
A
= +25 C
40
20
0
V
DD
= +3V
V
DD
= +5V
Figure 20. I
DD
vs. Reference Voltage
LOGIC INPUT ­ V
IN
(Volts)
0
I
DD
­
A
145
140
135
130
125
120
115
110
105
100
0.5
1
1.5
2
2.5
3
V
DD
= +3V
T
A
= +25 C
V
IN
= +3V TO 0V
V
IN
= 0V TO +3V
Figure 15. I
DD
vs. Logic Input Voltage
V
OUT
­ mV
0
I
OUT
CURRENT SINKING ­ mA
45
40
35
30
25
20
15
10
2
4
6
8
10
V
REF
= +2.5V
T
A
= +25 C
12
5
0
V
DD
= +5V
V
DD
= +3V
Figure 18. I
OUT
Sink Current vs.
V
OUT
TEMPERATURE ­ C
I
DD
_
SD
SHUTDOWN CURRENT ­ nA
1000
10
­40
100
1
­20
0
20
40
60
80
100 120 140
V
REF
= +2.5V
V
DD
= +5V
SHDN = 0V
Figure 21. Shutdown Current vs.
Temperature
AD7396/AD7397
­9­
REV. 0
DIGITAL INPUT FREQUENCY ­ Hz
I
DD
­
A
1400
1k
10M
10k
100k
1M
1200
1000
800
600
400
200
0
AD7396
A: V
DD
= +2.7V, CODE = 555
H
B: V
DD
= +2.7V, CODE = 3FF
H
C: V
DD
= +5.5V, CODE = 155
H
D: V
DD
= +5.5V, CODE = 3FF
H
D
C
B
A
Figure 22. I
DD
vs. Digital Input
Frequency
OPERATION
The AD7396 and AD7397 are a set of pin compatible, 12-bit
and 10-bit digital-to-analog converters. These single-supply
operation devices consume less than 200
µ
A of current while
operating from power supplies in the +2.7 V to +5.5 V range,
making them ideal for battery operated applications. They
contain a voltage-switched, 12-bit/10-bit, digital-to-analog
converter, rail-to-rail output op amps, and a parallel-input
DAC register. The external reference input has constant
2.5 M
input resistance independent of the digital code
setting of the DAC. In addition, the reference input can be tied
to the same supply voltage as V
DD
resulting in a maximum
output voltage span of 0 to V
DD
. The parallel data interface
consists of 12 data bits, DB0­DB11, for the AD7396, 10 data
bits, DB0­DB9, for the AD7397, and a
CS write strobe. An RS
pin is available to reset the DAC register to zero scale. This
function is useful for power-on reset or system failure recovery
to a known state. Additional power savings are accomplished by
activating the
SHDN pin resulting in a 1.5
µ
A maximum con-
sumption sleep mode. As long as the supply voltage, remains
data will be retained in the DAC and input register to supply
the DAC output when the part is taken out of shutdown.
DACA
REGISTER
12
INPUTA
REGISTER
DACB
REGISTER
12
INPUTB
REGISTER
AD7396
12-BIT
DACA
12-BIT
DACB
1
DATA
LDA
CS
A/
B
DGND
RS
SHDN
V
DD
V
OUTA
V
REF
V
OUTB
AGND
LDB
12
Figure 25. Functional Block Diagram
D/A CONVERTER SECTION
The voltage switched R-2R DAC generates an output voltage
dependent on the external reference voltage connected to the
REF pin according to the following equation:
V
OUT
= V
REF
×
D/2
N
(1)
where D is the decimal data word loaded into the DAC register,
and N is the number of bits of DAC resolution. In the case of
the 10-bit AD7397 using a 2.5 V reference, Equation 1 simpli-
fies to:
V
OUT
= 2.5
×
D/1024
(2)
Using Equation 2, the nominal midscale voltage at V
OUT
is
1.25 V for D = 512; full-scale voltage is 2.497 V. The LSB step
size is = 2.5
×
1/1024 = 0.0024 V.
For the 12-bit AD7396 operating from a 5.0 V reference equa-
tion [1] becomes:
V
OUT
= 5.0
×
D/4096
(3)
Using Equation 3, the AD7396 provides a nominal midscale
voltage of 2.50 V for D = 2048, and a full-scale output of
4.998 V. The LSB step size is = 5.0
×
1/4096 = 0.0012 V.
AMPLIFIER SECTION
The internal DAC's output is buffered by a low power con-
sumption precision amplifier. The op amp has a 60
µ
s typical
settling time to 0.1% of full scale. There are slight differences in
settling time for negative slewing signals versus positive. Also,
negative transition settling time to within the last 6 LSBs of zero
volts has an extended settling time. The rail-to-rail output stage
of this amplifier has been designed to provide precision perfor-
mance while operating near either power supply. Figure 26
shows an equivalent output schematic of the rail-to-rail-ampli-
fier with its N-channel pull-down FETs that will pull an output
load directly to GND. The output sourcing current is provided
by a P-channel pull-up device that can source current to GND
terminated loads.
P-ch
N-ch
V
DD
V
OUT
AGND
Figure 26. Equivalent Analog Output Circuit
FREQUENCY ­ Hz
PSRR ­ dB
80
1
10k
10
100
1k
70
60
50
40
30
20
0
10
V
DD
= +5V, 5%
V
DD
= +3V, 5%
Figure 23. PSRR vs. Frequency
HOURS OF OPERATION AT +150 C
NOMINAL CHANGE IN VOLTAGE ­ mV
1.0
0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
100
200
300
400
500
600
AD7396
SAMPLE SIZE = 77
V
REF
= +2.5V
CODE = FFF
H
CODE = 000
H
Figure 24. Long-Term Drift Acceler-
ated by Burn-In
AD7396/AD7397
­10­
REV. 0
The rail-to-rail output stage provides
±
1 mA of output current.
The N-channel output pull-down MOSFET shown in Figure 26
has a 35
ON resistance, which sets the sink current capability
near ground. In addition to resistive load driving capability, the
amplifier has also been carefully designed and characterized for
up to 100 pF capacitive load driving capability.
REFERENCE INPUT
The reference input terminal has a constant input resistance
independent of digital code, which results in reduced glitches on
the external reference voltage source. The high 2.5 M
input
resistance minimizes power dissipation within the AD7396/
AD7397 D/A converters. The V
REF
input accepts input voltages
ranging from ground to the positive-supply voltage V
DD
. One of
the simplest applications, which saves an external reference voltage
source, is connection of the V
REF
terminal to the positive V
DD
supply. This connection results in a rail-to-rail voltage output
span maximizing the programmed range. The reference input
will accept AC signals as long as they are kept within the supply
voltage range, 0 < V
REF IN
< V
DD
. The reference bandwidth
and integral nonlinearity error performance are plotted in the
Typical Performance Characteristics section, see Figures 10 and
13. The ratiometric reference feature makes the AD7396/AD7397
an ideal companion to ratiometric analog-to-digital converters
such as the AD7896.
POWER SUPPLY
The very low power consumption of the AD7396/AD7397 is a
direct result of a circuit design optimizing the use of a CBCMOS
process. By using the low power characteristics of CMOS for
the logic, and the low noise, tight matching of the complemen-
tary bipolar transistors, excellent analog accuracy is achieved.
One advantage of the rail-to-rail output amplifiers used in the
AD7396/AD7397 is the wide range of usable supply voltage.
The part is fully specified and tested for operation from +2.7 V
to +5.5 V.
POWER SUPPLY BYPASSING AND GROUNDING
Precision analog products such as the AD7396/AD7397 require
a well filtered power source. Since the AD7396/AD7397 oper-
ates from a single +3 V to +5 V supply, it seems convenient to
simply tap into the digital logic power supply. Unfortunately,
the logic supply is often a switch-mode design, which generates
noise in the 20 kHz to 1 MHz range. In addition, fast logic gates
can generate glitches, hundred of millivolts in amplitude, due to
wiring resistance and inductance. The power supply noise gen-
erated thereby means that special care must be taken to assure
that the inherent precision of the DAC is maintained. Good
engineering judgment should be exercised when addressing the
power supply grounding and bypassing of the 12-bit AD7396.
The AD7396 should be powered directly from the system power
supply. Whether or not a separate power supply trace is avail-
able generous supply bypassing will reduce supply line-induced
errors. Local supply bypassing consisting of a 10
µ
F tantalum
electrolytic in parallel with a 0.1
µ
F ceramic capacitor is recom-
mended in all applications (Figure 27).
AD7396
OR
AD7397
REF
V
DD
DGND
AGND
C
*
DATA
CS
A/
B
LDA
LDB
*
OPTIONAL EXTERNAL
REFERENCE BYPASS
0.1 F
10 F
+
V
OUTA
V
OUTB
+2.7V TO +5.5V
Figure 27. Recommended Supply Bypassing
INPUT LOGIC LEVELS
All digital inputs are protected with a Zener-type ESD protec-
tion structure (Figure 28) that allows logic input voltages to
exceed the V
DD
supply voltage. This feature can be useful if the
user is driving one or more of the digital inputs with a 5 V CMOS
logic input-voltage level while operating the AD7396/AD7397
on a +3 V power supply. If this mode of interface is used, make
sure that the V
OL
of the 5 V CMOS meets the V
IL
input require-
ment of the AD7396/AD7397 operating at 3 V. See Figure 16
for a graph for digital logic input threshold versus operating V
DD
supply voltage.
V
DD
LOGIC
IN
GND
Figure 28. Equivalent Digital Input ESD Protection
In order to minimize power dissipation from input-logic levels
that are near the V
IH
and V
IL
logic input voltage specifications, a
Schmitt trigger design was used that minimizes the input-buffer
current consumption compared to traditional CMOS input
stages. Figure 15 shows a plot of incremental input voltage
versus supply current showing that negligible current consump-
tion takes place when logic levels are in their quiescent state.
The normal crossover current still occurs during logic transi-
tions. A secondary advantage of this Schmitt trigger is the pre-
vention of false triggers that would occur with slow moving logic
transitions when a standard CMOS logic interface or opto-
isolators are used. The logic inputs DB11­DB0, A/
B CS, RS,
SHDN all contain Schmitt trigger circuits.
DIGITAL INTERFACE
The AD7396/AD7397 has a double-buffered, parallel-data
input. A functional block diagram of the digital section is shown
in Figure 25, while Table I contains the truth table for the logic
control inputs. The chip select (
CS) and A/B pins control load-
ing of data from the data inputs on pins DB11­DB0 into the
internal Input Register. The
CS active low input places data
into the decoded A/
B input register. When CS returns to logic
high within the data setup-and-hold time specifications the new
value of data in the input register will be latched. See Truth
Table for complete set of conditions. New data can only be
transferred to the corresponding DAC register when its LDx pin
is strobed active low. The LDx inputs are level-sensitive (DAC
Registers are transparent latches) and can be tied active low
AD7396/AD7397
­11­
REV. 0
allowing any new Input Register data updates to directly control
the DAC output voltages for single-buffered applications. For
doubled-buffered applications where both DAC outputs, V
OUTA
and V
OUTB
, need to be changed simultaneously to a new value,
the two inputs,
LDA and LDB, can be tied together and pulsed
active low in a synchronous manner.
RESET (
RS) PIN
Forcing the asynchronous
RS pin low will set the Input and
DAC registers to all zeros and the DAC output voltage will be
zero volts. The reset function is useful for setting the DAC
outputs to zero at power-up or after a power supply interrup-
tion. Test systems and motor controllers are two of many appli-
cations that benefit from powering up to a known state. The
external reset pulse can be generated by the microprocessor's
power-on RESET signal, from the microprocessor, or by an
external resistor and capacitor. RESET has a Schmitt trigger
input which results in a clean reset function when using external
resistor/capacitor generated pulses. See Table I, Control-Logic
Truth.
POWER SHUTDOWN (
SHDN)
Maximum power savings can be achieved by using the power
shutdown control function. This hardware-activated feature is
controlled by the active low input
SHDN pin. This pin has a
Schmitt trigger input which helps to desensitize it to slowly
changing inputs. By placing a logic low on this pin the internal
consumption of the AD7397 or AD7397 is reduced to nanoamp
levels, guaranteed to 1.5
µ
A maximum over the operating tem-
perature range. If power is present at all times on the V
DD
pin
while in the shutdown mode, the internal DAC register will
retain the last programmed data value. This data will be used
when the part is returned to the normal active state by placing
the DAC back to its programmed voltage setting. Shutdown
recovery time measures 80
µ
s. In the shutdown state the DAC
output amplifier exhibits an open-circuit high-resistance state.
Any load connected will stabilize at its termination voltage. If
the power shutdown feature is not needed then the user should
tie the
SHDN pin to the V
DD
voltage thereby disabling this
function.
UNIPOLAR OUTPUT OPERATION
This is the basic mode of operation for the AD7396. As shown
in Figure 29, the AD7396 has been designed to drive loads as
low as 5 k
in parallel with 100 pF. The code table for this
operation is shown in Table II.
DAC A
DAC B
V
REF
DIGITAL
V
DD
DGND
AGND
AD7396
EXT
REF
C
16/14
75k
75k
100pF
100pF
V
OUTA
V
OUTB
0.1 F
10 F
+2.7V TO +5.5V
R
0.01 F
DIGITAL INTERFACE
CIRCUITRY OMITTED
FOR CLARITY.
Figure 29. Unipolar Output Operation
Table II. Unipolar Code Table
Hexadecimal
Decimal
Output
Number
Number
Voltage (V)
In DAC Register
In DAC Register
(V
REF
= 2.5 V)
FFF
4095
2.4994
801
2049
1.2506
800
2048
1.2500
7FF
2047
1.2494
000
0
0
The circuit can be configured with an external reference plus
power supply, or powered from a single dedicated regulator or
reference, depending on the application performance requirements.
BIPOLAR OUTPUT OPERATION
Although the AD7397 has been designed for single supply op-
eration, the output can easily be configured for bipolar opera-
tion. A typical circuit is shown in Figure 30. This circuit uses a
clean regulated +5 V supply for power, which also provides
the circuit's reference voltage. Since the AD7397 output span
swings from ground to very near +5 V, it is necessary to choose
an external amplifier with a common-mode input voltage range
that extends to its positive supply rail. The micropower con-
sumption OP196 has been designed just for this purpose and
results in only 50
µ
A of maximum current consumption. Con-
nection of the equal-value 470 k
resistors results in a differen-
tial amplifier mode of operation with a voltage gain of two,
which produces a circuit output span of ten volts, that is,
­5 V to +5 V. As the AD7397 DAC is programmed from zero-
code 000
H
to midscale 200
H
to full-scale 3FF
H
, the circuit out-
put voltage V
O
is set at ­5 V, 0 V and +5 V (­1 LSB). The
output voltage V
O
is coded in offset binary according to
Equation 3.
V
OUT
= [(D/512)­1]
×
5
(4)
where D is the decimal code loaded in the AD7397 DAC regis-
ter. Note that the LSB step size is 10/1024 = 10 mV. This
circuit has been optimized for micropower consumption includ-
ing the 470 k
gain setting resistors, which should have low
temperature coefficients to maintain accuracy and matching
(preferably the same resistor material, such as metal film). If
better stability is required, the power supply could be substi-
tuted with a precision reference voltage such as the low dropout
REF195, which can easily supply the circuit's 262
µ
A of current
and still provide additional power for the load connected to V
O
.
The micropower REF195 is guaranteed to source 10 mA output
drive current, but consumes only 50
µ
A internally. If higher
resolution is required, the AD7396 can be used with the addi-
tion of two more bits of data inserted into the software coding,
which would result in a 2.5 mV LSB step size. Table III shows
examples of nominal output voltages, V
O
, provided by the bipo-
lar operation circuit application.
AD7396/AD7397
­12­
REV. 0
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C3425­8­10/98
PRINTED IN U.S.A.
24-Lead SOIC Package
(R-24)
24
13
12
1
0.6141 (15.60)
0.5985 (15.20)
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC
0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
8
0
0.0291 (0.74)
0.0098 (0.25)
45
AD7397
V
OUTA
V
DD
REF
GND
C
+5V
I
SY
< 262 A
200 A
470k
470k
OP196
­5V
< 50 A
V
O
+5V
­5V
BIPOLAR
OUTPUT
SWING
ONLY ONE CHANNEL SHOWN.
DIGITAL INTERFACE CIRCUITRY
OMITTED FOR CLARITY.
Figure 30. Bipolar Output Operation
Table III. Bipolar Code Table
Hexadecimal Number
Decimal Number
Analog Output
In DAC Register
In DAC Register
Voltage (V)
3FF
1023
4.9902
201
513
0.0097
200
512
0.0000
1FF
511
­0.0097
000
0
­5.0000
24-Lead Narrow Body Plastic DIP Package
(N-24)
24
1
12
13
0.280 (7.11)
0.240 (6.10)
PIN 1
1.275 (32.30)
1.125 (28.60)
0.150
(3.81)
MIN
0.200 (5.05)
0.125 (3.18)
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.070 (1.77)
0.045 (1.15)
0.100 (2.54)
BSC
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
24-Lead Thin Surface Mount TSSOP Package
(RU-24)
24
13
12
1
0.311 (7.90)
0.303 (7.70)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8
0