REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

AD6122

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 2000

CDMA 3 V Transmitter IF Subsystem

with Integrated Voltage Regulator

FUNCTIONAL BLOCK DIAGRAM

I INPUT

Q INPUT

LOCAL

OSCILLATOR

INPUT

ATTENUATOR

LOW

DROPOUT

REGULATOR

COMMON-MODE

REFERENCE

OUTPUT

VREG

POWER-

DOWN 1

1.23 V

REFERENCE

OUTPUT

VPOS

TEMPERATURE

COMPENSATION

GAIN

CONTROL

SCALE

FACTOR

GAIN CONTROL

VOLTAGE

INPUT

GAIN CONTROL

REFERENCE

VOLTAGE

INPUT

TRANSMIT
OUTPUT

IF AMPLIFIERS

QUADRATURE MODULATOR

POWER-

DOWN 2

IF AMPLIFIER
INPUT

QUADRATURE

MODULATOR

OUTPUT

AD6122

VCC

FEATURES
Fully Compliant with IS98A and PCS Specifications
Linear IF Amplifier

63 dB to +34 dB
Linear-in-dB Gain Control
Temperature-Compensated Gain Control

Quadrature Modulator

Modulates IFs from 50 MHz to 350 MHz

Integral Low Dropout Regulator

Accepts 2.9 V to 4.2 V Input from Battery

Low Power

10.4 mA at Midgain
<10 A Sleep Mode Operation

Companion Receiver IF Chip Available (AD6121)

APPLICATIONS
CDMA, W-CDMA, AMPS and TACS Operation
QPSK Transmitters

GENERAL DESCRIPTION

The AD6122 is a low power IF transmitter subsystem, specifi-
cally designed for CDMA applications. It consists of an I and Q
modulator, a divide-by-two quadrature generator, high dynamic

range IF amplifiers with voltage-controlled gain and a power-
down control input. An integral low dropout regulator allows
operation from battery voltages from 2.9 V to 4.2 V.

The gain control input accepts an external gain control voltage
input from a DAC. It provides 97 dB of gain control with a
nominal 75 dB/V scale factor. Either an internal or an external
reference may be used to set the gain-control scale factor.

The I and Q modulator accepts differential quadrature base-
band inputs from a CDMA baseband converter. The local oscil-
lator is injected at twice the IF frequency. A divide-by-two
quadrature generator followed by dual polyphase filters ensures
±1° quadrature accuracy.
The modulator provides a common-mode reference output to
bias the transmit DACs in the baseband converter to the same
common-mode voltage as the modulator inputs, allowing dc
coupling between the two ICs and thus eliminating the need to
charge and discharge coupling capacitors. This allows the fastest
power-up and power-down times for the AD6122 and CDMA
baseband ICs.

The AD6122 is fabricated using a 25 GHz f

silicon BiCMOS

process and is packaged in a 28-lead SSOP and a 32-leadless
LPCC chip scale package (5 mm

× 5 mm).

REV. B

AD6122SPECIFICATIONS

= +25 C, V

= +3.0 V, LO = 2 IF, REFIN = 1.23 V, LDO Enabled, unless otherwise

noted) NOTE: All powers shown in dBm are referred to 1 k

Specification

Conditions

Min

Typ

Max

Unit

MODULATOR

LO = 260.76 MHz (2

× IF), 100 mV p-p

500 mV p-p Differential I and Q Inputs;

Output Level

Output Level Referred to a 1 k

Differential Load

dBm

Output Third Order Harmonic

dBc

I/Q Inputs

Differential Input Voltage

Differential

500

mV p-p

Bandwidth

3 dB

MHz

Resistance

Quadrature Accuracy

± 1

Amplitude Balance

±0.1

Output Referred Noise

0.9 MHz to 5.0 MHz Offsets

169

dBm/Hz

Modulator Common-Mode Reference

1.408

LO Input Resistance

Differential Input at 260.38 MHz

1.2

LO Input Capacitance

Differential Input at 260.38 MHz

2.4

LO Carrier Leakage

Bias I/Q Using MODCMREF

dBc

IF AMPLIFIER

= 130.38 MHz

Noise Figure

VGAIN = 2.5 V, 1 k

Differential Load

Input 1 dB Compression Point

VGAIN = 2.5 V

dBm

Input Third-Order Intercept

VGAIN = 2.5 V

dBm

Gain Flatness

±630 kHz

±0.25

Input Capacitance

Shunt Equivalent Model at 130.38 MHz

2.3

Differential IF Input Resistance

Shunt Equivalent Model at 130.38 MHz

680

Differential IF Output Resistance

Per Pin at 130.38 MHz

4.2

Differential IF Output Capacitance

Per Pin at 130.38 MHz

2.0

GAIN CONTROL INTERFACE

Gain Scaling

Using Internal Reference

dB/V

Gain Scaling Linearity

For a Typical Dynamic Range of 92 dB

± 3

dB/V

Minimum Gain

VGAIN = 0.5 V

Maximum Gain

VGAIN = 2.5 V

+34

Gain Control Response Time

90 dB Gain Change, Min Gain to Max Gain

0.7

µs

Input Resistance at REFIN

Input Resistance at VGAIN

109

POWER-DOWN INTERFACE

Logic Threshold High

Power-Up on Logical High

1.34

Logic Threshold Low

1.30

Input Current for Logical High

0.1

µA

Turn-On Response Time

Measure to Settling of AGC from Standby Mode

µs

Turn-Off Response Time

To 200

µA Supply Current

187

LOW DROPOUT REGULATOR

External PNP Pass Transistor, VCE

SAT

= 0.4 V

Max, h

= 100/300 Min/Max

Input Range

2.94.2

Nominal Output

2.70

Dropout Voltage

200

Reference Output

1.23

POWER SUPPLY

Supply Range Bypassing Internal LDO

2.75.0

Supply Current

VGAIN = 1.5 V (Unity Gain)

10.4

Standby Current

7.8

µA

OPERATING TEMPERATURE

MIN

to T

MAX

+85

°C

Specifications subject to change without notice.

REV. B

AD6122

ABSOLUTE MAXIMUM RATINGS

Supply Voltage DVCC, IFVCC, TXVCC to DGND,

IFGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5 V

Internal Power Dissipation

. . . . . . . . . . . . . . . . . . . 600 mW

Operating Temperature Range . . . . . . . . . . . 40

°C to +85°C

Storage Temperature Range . . . . . . . . . . . . 65

°C to +150°C

Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300

°C

ORDERING GUIDE

Temperature

Package

Model

Range

Package Description

Option

AD6122ARS

°C to +85°C

Shrink Small Outline Package (SSOP)

RS-28

AD6122ARSRL

°C to +85°C

28-Lead SSOP on Tape-and-Reel

AD6122ACP

°C to +85°C

Chip Scale Package (LPCC)

CP-32

AD6122ACPRL

°C to +85°C

32-Leadless LPCC on Tape-and-Reel

PIN CONFIGURATIONS

LDOC

PD1

PD2

AD6122 Top View

(Not to Scale)

NC = NO CONNECT

LDOB

LDOGND

DGND

LOIPP

LOIPN

DVCC

MODOPP

QIPP

QIPN

MODCMREF

IIPN

IIPP

IFGND

TXOPP

TXOPN

TXVCC

IFGND

IFINN

IFINP

MODOPN

IFVCC

REFOUT

REFIN

VGAIN

LDOE

LPCC Package

TOP VIEW

(Not to Scale)

AD6122

IFGND

TXVCC

TXOPN

TXOPP

DVCC

LOIPN

LOIPP

PD1

PD2

LDOE

LDOB

DGND

LDOGND

LDOC

IFINN

IFINP

MODOPN

MODOPP

QIPP

QIPN

MODCMREF

VGAIN

REFIN

REFOUT

IFVCC

IIPN

IIPP

IFGND

SSOP Package

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6122 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

NOTES

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

Thermal Characteristics: 28-lead SSOP Package:

= 115.25

°C/W.

REV. B

AD6122

PIN FUNCTION DESCRIPTIONS

SSOP

LPCC

Pin #

Pin Label

Description

Function

PD1

Power-Down 1

IF Amplifier Power-Down Control Input; CMOS Com-
patible; HIGH = Entire IC Powers Down, LOW = IF
Amplifiers On.

PD2

Power-Down 2

Modulator Power-Down Control Input; CMOS Compat-
ible; HIGH = Modulator Off , LOW = Modulator On.

LDOE

Low Dropout Regulator Pass

Connects to Emitter of External PNP Pass Transistor

Transistor Emitter Connection

and VCC.

LDOB

Low Dropout Regulator Pass

Connects to Base of External PNP Pass Transistor.

Transistor Base

LDOC

Low Dropout Regulator Pass

Connects to Collector of External PNP Pass Transistor.

Transistor Collector

3, 4

LDOGND

Low Dropout Regulator Ground

Ground.

DGND

Digital Ground

Ground.

LOIPP

Local Oscillator "Positive" Input

Connects to Local Oscillator; AC Coupled.

LOIPN

Local Oscillator "Negative" Input

Connects to Ground via Decoupling Capacitor.

DVCC

Digital VCC

Connects to Digital Supply.

TXOPP

Transmit Output "Positive"

Connects to Output Filter; AC Coupled.

TXOPN

Transmit Output "Negative"

Connects to Output Filter; AC Coupled.

TXVCC

Transmit Output VCC

Connects to LDO Output via Decoupling Network.

12, 13

IFGND

IF Ground

Ground.

IFINN

IF Input "Negative"

IF "Negative" Input from LC Roofing Filter.

IFINP

IF Input "Positive"

IF "Positive" Input from LC Roofing Filter.

MODOPN

Modulator "Negative" If Output

Output Modulator Output to LC Roofing Filter.

MODOPP

Modulator "Positive" Output

Modulator Output to LC Roofing Filter.

QIPP

Q Input "Positive"

Connects to Q "Positive" Output of Baseband IC.

QIPN

Q Input "Negative"

Connects to Q "Negative" Output of Baseband IC.

MODCMREF

Modulator Common-Mode

Connects to CDMA Baseband Converter Tx DAC

Reference Out

Common-Mode Reference Input.

IIPN

I Input "Negative"

Connects to I "Negative" Output of Baseband IC.

IIPP

I Input "Positive"

Connects to I "Positive" Output of Baseband IC.

23, 24

IFGND

Ground

Connects to IF Ground.

No Connect

IFVCC

IF VCC

Connects to Decoupled Output of LDO Regulator.

REFOUT

Gain Control Reference Output

Provides 1.23 V Voltage Reference Output for DAC in
CDMA Baseband Converter and REFIN.

REFIN

Gain Control Reference Input

Accepts 1.23 V Reference Input from REFOUT or
External Reference.

VGAIN

Gain Control Voltage Input

Accepts Gain Control Input Voltage from External DAC.
Max Gain = 2.5 V; Min Gain = 0.5 V.

REV. B

AD6122

Test Figures

AD830

I DATA

15V

0.1 F

MODCMREF

A=1

V1

+15V

0.1 F

AD830

15V

0.1 F

MODCMREF

A=1

+15V

0.1 F

MUST BE EQUAL
LENGTHS

AD830

Q DATA

15V

0.1 F

MODCMREF

A=1

+15V

0.1 F

AD830

15V

0.1 F

MODCMREF

A=1

+15V

0.1 F

MUST BE EQUAL
LENGTHS

AD6122

IIPP

IIPN

QIPP

QIPN

LOIPP

LO INPUT

MODCMREF

10nF

0.1 F

MOD_OUT

VREG OUT

450

205

450

0.1 F

VREG OUT

MODOPP

MODOPN

OUT

V1

LOIPN

Figure 1. Quadrature Modulator's Characterization Input and Output Impedance Matches

Part Number AD6122