REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

Variable Resolution, Monolithic

Resolver-to-Digital Converters

AD2S81A/AD2S82A

An analog signal proportional to velocity is also available and
can be used to replace a tachogenerator.

PRODUCT HIGHLIGHTS

Monolithic. A one-chip solution reduces the package size re-
quired and increases the reliability.

Resolution Set by User. Two control pins are used to select
the resolution of the AD2S82A to be 10, 12, 14 or 16 bits al-
lowing the user to use the AD2S82A with the optimum resolu-
tion for each application.

Ratiometric Tracking Conversion. Conversion technique
provides continuous output position data without conversion
delay and is insensitive to absolute signal levels. It also provides
good noise immunity and tolerance to harmonic distortion on
the reference and input signals.

Dynamic Performance Set by the User. By selecting exter-
nal resistor and capacitor values the user can determine band-
width, maximum tracking rate and velocity scaling of the
converter to match the system requirements. The external com-
ponents required are all low cost, preferred value resistors and
capacitors, and the component values are easy to select using
the simple instructions given.

Velocity Output. An analog signal proportional to velocity is
available and is linear to typically one percent. This can be used
in place of a velocity transducer in many applications to provide
loop stabilization in servo controls and velocity feedback data.

Low Power Consumption. Typically only 300 mW.

MODELS AVAILABLE

Information on the models available is given in the Ordering
Guide.

GENERAL DESCRIPTION

The AD2S82A is a monolithic 10-, 12-, 14- or 16-bit tracking
resolver-to-digital converter contained in a 44-lead J leaded
PLCC package. Two extra functions are provided in the new
surface mount packageCOMPLEMENT and VCO output.

The AD2S81A is a monolithic 12-bit fixed resolution tracking
resolver-to-digital converter packaged in a 28-lead DIP.

The converters allow users to select their own dynamic performance
with external components. This allows the users great flexibility in
defining the converter that best suits their system requirements.
The AD2S82A allows users to select the resolution to be 10, 12,
14 or 16 bits and to track resolver signals rotating at up to 1040
revs per second (62,400 rpm) when set to 10-bit resolution.

The AD2S81A and AD2S82A convert resolver format input
signals into a parallel natural binary digital word using a ratio-
metric tracking conversion method. This ensures high-noise
immunity and tolerance of lead length when the converter is
remote from the resolver.

The output word is in a three-state digital logic form available in
two bytes on the 16 output data lines for the AD2S82A and on
eight output data lines for the AD2S81A. BYTE SELECT,
ENABLE and INHIBIT pins ensure easy data transfer to 8- and
16-bit data buses, and outputs are provided to allow for cycle or
pitch counting in external counters.

AD2S82A FUNCTIONAL BLOCK DIAGRAM

SIN I/P

SIGNAL

GND

COS I/P

ANALOG

GND

RIPPLE

CLK

+12V
12V

COMP

DATA

LOAD

SEGMENT

SWITCHING

SC1

SC2

16 DATA BITS

BYTE

SELECT

BUSY DIR

AC ERROR
O/P

VCO I/P

AD2S82A

VCO O/P

16-BIT

UP/DOWN COUNTER

VCO DATA

TRANSFER

LOGIC

+5V

DIGITAL
GND

R-2R

DAC

INTEGRATOR

I/P

PHASE

SENSITIVE

DETECTOR

DEMOD

I/P

DEMOD

O/P

OUTPUT DATA LATCH

INTEGRATOR
O/P

INHIBIT

ENABLE

FEATURES
Monolithic (BiMOS ll) Tracking R/D Converter
Ratiometric Conversion
Low Power Consumption: 300 mW Typ
Dynamic Performance Set by User
Velocity Output
ESD Class 2 Protection (2,000 V Min)

AD2S81A
28-Lead DIP Package
Low Cost

AD2S82A
44-Lead PLCC Package
10-, 12-, 14- and 16-Bit Resolution Set by User
High Max Tracking Rate 1040 RPS (10 Bits)
VCO Output (Inter LSB Output)
Data Complement Facility
Industrial Temperature Range

APPLICATIONS
DC Brushless and AC Motor Control
Process Control
Numerical Control of Machine Tools
Robotics
Axis Control

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 1998

AD2S81A/AD2S82ASPECIFICATIONS

AD2S81A

AD2S82A

Parameter

Conditions

Min

Typ

Max

Min

Typ

Max

Units

SIGNAL INPUTS

Frequency

400

20,000

Voltage Level

1.8

2.0

2.2

1.8

2.0

2.2

V rms

Input Bias Current

150

Input Impedance

1.0

Maximum Voltage

V pk

REFERENCE INPUT

Frequency

400

20,000

Voltage Level

1.0

8.0

1.0

8.0

V pk

Input Bias Current

150

Input Impedance

1.0

CONTROL DYNAMICS

Repeatability

LSB

Allowable Phase Shift

(Signals to Reference)

+10

Degrees

Tracking Rate

10 Bits

1040

rps

12 Bits

260

rps

14 Bits

rps

16 Bits

16.25

rps

Bandwidth

User Selectable

ACCURACY

Angular Accuracy

22 + 1 LSB

arc min

30 + 1 LSB

8 + 1 LSB

arc min

4 + 1 LSB

arc min

2 + 1 LSB

arc min

Monotonicity

Guaranteed Monotonic

Missing Codes (16-Bit Resolution) J, K

Codes

Code

VELOCITY SIGNAL

Linearity

Over Full Range

% FSD

Reversion Error

% FSD

DC Zero Offset

DC Zero Offset Tempco

Gain Scaling Accuracy

% FSD

Output Voltage

1 mA Load

10.5

Dynamic Ripple

Mean Value

1.5

% rms O/P

Output Load

1.0

INPUT/OUTPUT PROTECTION

Analog Inputs

Overvoltage Protection

Analog Outputs

Short Circuit O/P Protection

5.6

10.4

5.6

10.4

DIGITAL POSITION

Resolution

10, 12, 14 and 16

Output Format

Bidirectional Natural Binary

Load

LSTTL

INHIBIT

Sense

Logic LO to Inhibit

Time to Stable Data

600

ENABLE

Logic LO Enables Position
Output. Logic HI Outputs in
High Impedance State

ENABLE/Disable Time

110

BYTE SELECT

Sense
Logic HI

MS Byte DB1DB8,
(LS Byte DB9DB16)

Logic LO

LS Byte DB1DB8,
(LS Byte DB9DB16)

Time to Data Available

140

SHORT CYCLE INPUTS

4, 5

Internally Pulled High
(100 k

) to +V

SC1 SC2
0 0

10 Bit

0 1

12 Bit

1 0

14 Bit

1 1

16 Bit

DATA LOAD

4, 5

Sense

Internally Pulled High (100 k

)

150

300

to +V

Logic LO Allows

Data to Be Loaded into the
Counters from the Data Lines

REV. B

(@ T

= +25 C, unless otherwise noted)

AD2S81A

AD2S82A

Parameter

Conditions

Min

Typ

Max

Min

Typ

Max

Units

COMPLEMENT

4, 5

Internally Pulled High (100 k

) to

; Logic LO to Activate; No

Connect for Normal Operation

BUSY

Sense

Logic HI When Position O/P Changing

Width

200

600

200

600

Load

Use Additional Pull-Up

LSTTL

DIRECTION

Sense

Logic HI Counting Up
Logic LO Counting Down

Max Load

LSTTL

RIPPLE CLOCK

Sense

Logic HI, All 1s to All 0s
All 0s to All 1s

Width

Dependent On Input Velocity

300

Reset

Before Next Busy

Load

LSTTL

DIGITAL INPUTS

High Voltage, V

INHIBIT, ENABLE

2.0

DB1DB16, Byte Select

10.8 V, V

= 5.0 V

Low Voltage, V

INHIBIT, ENABLE

0.8

DB1DB16, Byte Select

13.2 V, V

= 5.0 V

DIGITAL INPUTS

High Current, I

INHIBIT, ENABLE

100

DB1DB16

13.2 V, V

= 5.5 V

Low Current, I

INHIBIT, ENABLE

100

DB1DB16, Byte Select

13.2 V, V

= 5.5 V

DIGITAL INPUTS

Low Voltage, V

ENABLE = HI

1.0

SC1, SC2, Data Load

12.0 V, V

= 5.0 V

Low Current, I

ENABLE = HI

400

SC1, SC2, Data Load

12.0 V, V

= 5.0 V

DIGITAL OUTPUTS

High Voltage, V

DB1DB16; RIPPLE CLK, DIR

2.4

12.0 V, V

= 4.5 V

= 100

Low Voltage, V

DB1DB16, RIPPLE CLK, DIR

0.4

12.0 V, V

= 5.5 V

= 1.2 mA

THREE-STATE LEAKAGE

DB1DB16 Only

Current I

12.0 V, V

= 5.5 V

100

= 0 V

12.0 V, V

= 5.5 V

100

= 5.0 V

POWER SUPPLIES

Voltage Levels

+10.8

+13.2

+10.8

+13.2

10.8

13.2

10.8

13.2

+13.2

Current

12 V

13.2 V

5.0 V

0.5

1.5

0.5

1.5

NOTES

Refers to small signal bandwidth.

Output offset dependent on value for R6.

Refer to timing diagram.

AD2S82A only.

These pins are referenced to +V

(i.e., HI = +12 V, LO = 0 V).

Specifications subject to change without notice.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.

AD2S81A/AD2S82A

REV. B

AD2S81A

AD2S82A

Parameter

Conditions

Min

Typ

Max

Min

Typ

Max

Units

RATIO MULTIPLIER

AC Error Output Scaling

10 Bit

177.6

mV/Bit

12 Bit

44.4

mV/Bit

14 Bit

11.1

mV/Bit

16 Bit

2.775

mV/Bit

PHASE SENSITIVE DETECTOR

Output Offset Voltage

Gain

In Phase

w.r.t. REF

0.882

0.9

0.918

0.882

0.9

0.918

V rms/V dc

In Quadrature

w.r.t. REF

0.04

V rms/V dc

Input Bias Current

150

Input Impedance

Input Voltage

INTEGRATOR

Open-Loop Gain

At 10 kHz

Dead Zone Current (Hysteresis)

100

nA/LSB

Input Offset Voltage

Input Bias Current

150

Output Voltage Range

10.8 V dc

VCO

12 V dc

Maximum Rate

1.0

1.1

1.0

1.1

MHz

VCO Rate

Positive DIR

7.1

7.9

8.7

7.1

7.9

8.7

kHz/

Negative DIR

7.1

7.9

8.7

7.1

7.9

8.7

kHz/

VCO Power Supply Sensitivity

Increase

+0.5

%/V

8.0

%/V

Decrease

8.0

%/V

+2.0

%/V

Input Offset Voltage

Input Bias Current

380

Input Bias Current Tempco

1.22

nA/

Input Voltage Range

Linearity of Absolute Rate

Full Range

% FSD

Over 0% to 50% of Full Range

% FSD

Reversion Error

1.5

% FSD

Sensitivity of Reversion Error

%/V of

to Symmetry of Power Supplies

Asymmetry

VCO Output

1, 2

2.7

3.0

3.3

V/LSB

POWER SUPPLIES

Voltage Levels

+10.8

+13.2

+10.8

+13.2

10.8

13.2

10.8

13.2

+13.2

Current

12 V

13.2 V

5.0 V

0.5

1.5

0.5

1.5

NOTES

The VCO output swings between

3 V depending on the resolver direction.

AD2S82A only.

Specifications in boldface are tested on all production units at final electrical test.
Specifications subject to change without notice.

(typical @ +25 C unless otherwise noted)

AD2S81A/AD2S82ASPECIFICATIONS

ESD SENSITIVITY
The AD2S81A and AD2S82A features an input protection circuit consisting of large "distributed"
diodes and polysilicon series resistors to dissipate both high energy discharge (Human Body Model)
and fast, low energy pulses (Charges Device Model).

he AD2S81A and AD2S82A is ESD protection Class II (2000 V min). Proper ESD precautions are

strongly recommended to avoid functional damage or performance degradation. For further informa-
tion on ESD precautions, refer to Analog Devices ESD Prevention Manual.

REV. B

WARNING!

ESD SENSITIVE DEVICE

ORDERING GUIDE

Operating
Temperature

Package

Accuracy

Ranges

Options*

AD2S81AJD

30 arc min

C to +70

D-28

AD2S82AHP

22 arc min

C to +85

P-44A

AD2S82AJP

8 arc min

C to +85

P-44A

AD2S82AKP

4 arc min

C to +85

P-44A

AD2S82ALP

2 arc min

C to +85

P-44A

*D = Ceramic DIP Package; P = Plastic Leaded Chip Carrier (PLCC) Package.

AD2S81A/AD2S82A

REV. B

RECOMMENDED OPERATING CONDITIONS

Power Supply Voltage (+V

to V

) . . . . . . . . .

12 V dc

10%

Power Supply Voltage V

. . . . . . . . . . . . . . . . . . +5 V dc

10%

Analog Input Voltage (SIN and COS) . . . . . . . . 2 V rms

10%

Analog Input Voltage (REF) . . . . . . . . . . . . . . 1 V to 8 V peak
Signal and Reference Harmonic Distortion . . . . . . . 10% (max)
Phase Shift Between Signal and Reference .

10 Degrees (max)

Ambient Operating Temperature Range

Commercial (JD) . . . . . . . . . . . . . . . . . . . . . . 0

C to +70

Industrial (HP, JP, KP, LP) . . . . . . . . . . . . 40

C to +85

PIN FUNCTION DESCRIPTIONS

Mnemonic

Description

REFERENCE I/P

Reference Signal Input

DEMOD I/P

Demodulator Input

AC ERROR O/P

Ratio Multiplier Output

COS I/P

Cosine Input

ANALOG GND

Power Ground

SIGNAL GND

Resolver Signal Ground

SIN I/P

Sine Input

Positive Power Supply

DB1DB16

Parallel Output Data

Logic Power Supply

ENABLE

Logic Hi-Output Data in High Impedance
State Logic Lo Present Data to the Output Latches

BYTE SELECT

Logic Hi-Most Significant Byte to DB1DB8
Logic Lo-Most Significant Byte to DB1DB8

INHIBIT

Logic Lo Inhibits Data Transfer to Output Latches

DIGITAL GND

Digital Ground

SC1SC2*

Select Converter Resolution

DATA LOAD*

Logic Lo DB1DB16 Inputs
Logic Hi DB1DB16 Outputs

BUSY

Converter Busy, Data Not Valid While Busy Hi

DIR

Logic State Defines Direction of Input Signal Rotation

RIPPLE CLK

Positive Pulse when Converter Output Changes from
1s to All 0s or Vice Versa

Negative Power Supply

VCO I/P

VCO Input

INTEGRATOR I/P

Integrator Input

INTEGRATOR O/P Integrator Output
DEMOD O/P

Demodulator Output

COMPLEMENT*

Active Logic Lo

VCO O/P*

VCO Output

*AD2S82A Only.

Bit Weight Table

Binary

Resolution Degrees

Minutes

Seconds

Bits (N)

)

/Bit

360.0

21600.0

1296000.0

180.0

10800.0

648000.0

90.0

5400.0

324000.0

45.0

2700.0

162000.0

22.5

1350.0

81000.0

11.25

675.0

40500.0

5.625

337.5

20250.0

128

2.8125

168.75

10125.0

256

1.40625

84.375

5062.5

512

0.703125

42.1875

2531.25

1024

0.3515625

21.09375

1265.625

2048

0.1757813

10.546875

632.8125

4096

0.0878906

5.273438

316.40625

8192

0.0439453

2.636719

158.20313

16384

0.0219727

1.318359

79.10156

32768

0.0109836

0.659180

39.55078

65536

0.0054932

0.329590

19.77539

131072

0.0027466

0.164795

9.88770

262144

0.0013733

0.082397

4.94385

ABSOLUTE MAXIMUM RATINGS

(with respect to GND)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V dc

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V dc

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +V

Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to V

SIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to V

COS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to V

Any Logical Input . . . . . . . . . . . . . . . . . . . 0.4 V dc to +V

Demodulator Input . . . . . . . . . . . . . . . . . . . . . . . +14 V to V

Integrator Input . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to V

VCO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to V

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 mW
Operating Temperature

Commercial (JD) . . . . . . . . . . . . . . . . . . . . . . 0

C to +70

Industrial (HP, JP, KP, LP) . . . . . . . . . . . . . 40

C to +85

Storage Temperature (All Grades) . . . . . . . . . 65

C to +150

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300

CAUTION
1. Absolute Maximum Ratings are those values beyond which damage to the

device may occur.

2. Correct polarity voltages must be maintained on the +V

and V

pins.

AD2S81A/AD2S82A PIN CONFIGURATIONS

REFERENCE I/P

DEMOD I/P

DEMOD O/P

INTEGRATOR O/P

ANALOG GND

SIN I/P

RIPPLE CLK

DIR

AC ERROR O/P

COS I/P

INTEGRATOR I/P

VCO I/P

MSB DB1

BUSY

DB2

DIGITAL GND

DB3

DB4

BYTE SELECT

DB5

DB6

DB7

DB8 LSB

TOP VIEW

(Not to Scale)

AD2S81A

INHIBIT

ENABLE

44 43 42 41 40

18 19 20 21 22 23 24 25 26 27 28

PIN 1
IDENTIFIER

TOP VIEW

(Not to Scale)

NC = NO CONNECT

RIPPLE CLK

DIR

BUSY

DATA LOAD

COMPLEMENT

SC2

SC1

DIGITAL GND

INHIBIT

SIN O/P

MSB DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

DB10

DB11

DB12

DB14

DB15

LSB DB16

ENABLE

BYTE

SELECT

DB13

AD2S82A

SIGNAL GND

ANALOG GND

COS I/P

AC ERROR O/P

DEMOD I/P

REFERENCE I/P

DEMOD O/P

INTEGRATOR O/P

INTEGRATOR I/P

VCO O/P

VCO I/P

REV. B

AD2S81A/AD2S82A

CONNECTING THE CONVERTER

The power supply voltages connected to +V

and V

pins

should be +12 V dc and 12 V dc and must not be reversed.
The voltage applied to V

can be +5 V dc to +V

It is recommended that the decoupling capacitors are connected
in parallel between the power lines +V

, V

and ANALOG GND

adjacent to the converter. Recommended values are 100 nF
(ceramic) and 10

F (tantalum). Also capacitors of 100 nF and

F should be connected between +V

and DIGITAL GND

adjacent to the converter.

When more than one converter is used on a card, then separate
decoupling capacitors should be used for each converter.

The resolver connections should be made to the SIN and
COS inputs, REFERENCE I/P and SIGNAL GND as shown

in Figure 7 and described in the Connecting the Resolver
section.

The two signal ground wires from the resolver should be joined
at the SIGNAL GROUND pin of the resolver to minimize the
coupling between the sine and cosine signals. For this reason it
is also recommended that the resolver is connected using indi-
vidually screened twisted pair cables with the sine, cosine and
reference signals twisted separately.

SIGNAL GND and ANALOG GND are connected internally.
ANALOG GND and DIGITAL GND must be connected
externally.

The external components required should be connected as
shown in Figures 1a and 1b.

SIN I/P

SIGNAL GND

COS I/P

ANALOG GND

RIPPLE CLK

+12V

12V

COMP

DATA

LOAD

SC1

16 DATA BITS

BYTE

SELECT

BUSY

DIR

AC ERROR

O/P

VCO I/P

DEMOD
I/P

DEMOD
O/P

INTEGRATOR
O/P

AD2S82A

INTEGRATOR
I/P

DIGITAL

GND

SC2

16-BIT UP/DOWN COUNTER

OUTPUT DATA LATCH

+5V

VCO

O/P

VCO

DATA TRANSFER

LOGIC

HP FILTER

REFERENCE I/P

+12V

12V

OFFSET ADJUST

BANDWIDTH

SELECTION

VELOCITY
SIGNAL

TRACKING
RATE
SELECTION

SEGMENT

SWITCHING

ENABLE

INHIBIT

R-2R DAC

PHASE-SENSITIVE

DETECTOR

Figure 1a. AD2S82A Connection Diagram

SIN I/P

SIGNAL GND

COS I/P

RIPPLE CLK

+12V

12V

8 DATA BITS

BYTE

SELECT

BUSY

DIR

AC ERROR

O/P

VCO I/P

DEMOD
I/P

DEMOD
O/P

INTEGRATOR
O/P

AD2S81A

INTEGRATOR
I/P

DIGITAL

GND

+5V

VCO

DATA TRANSFER

LOGIC

HP FILTER

REFERENCE I/P

+12V

12V

OFFSET ADJUST

BANDWIDTH

SELECTION

VELOCITY
SIGNAL

TRACKING
RATE
SELECTION

SEGMENT

SWITCHING

ENABLE

INHIBIT

R-2R DAC

PHASE-SENSITIVE

DETECTOR

OUTPUT DATA LATCH

16-BIT UP/DOWN COUNTER

Figure 1b. AD2S81A Connection Diagram

AD2S81A/AD2S82A

REV. B

HARMONIC DISTORTION

The amount of harmonic distortion allowable on the signal and
reference lines is 10%.

Square waveforms can be used but the input levels should be
adjusted so that the average value is 1.9 V rms. (For example, a
square wave should be 1.9 V peak). Triangular and sawtooth
waveforms should have a amplitude of 2 V rms.

Note: The figure specified of 10% harmonic distortion is for
calibration convenience only.

POSITION OUTPUT

The resolver shaft position is represented at the converter out-
put by a natural binary parallel digital word.

As the digital position output of the converter passes through
the major carries, i.e., all "1s" to all "0s" or the converse, a
RIPPLE CLK logic output is initiated indicating that a revolu-
tion or a pitch of the input has been completed.

The direction of input rotation is indicated by the DIRECTION
(DIR) logic output. This direction data is always valid in ad-
vance of a RIPPLE CLK pulse and, as it is internally latched,
only changing state (1 LSB min change) with a corresponding
change in direction.

Both the RIPPLE CLK pulse and the DIR data are unaffected
by the application of the

INHIBIT.

The static positional accuracy quoted is the worst case error that
can occur over the full operating temperature excluding the
effects of offset signals at the INTEGRATOR I/P (which can be
trimmed outsee Figures 1a and 1b), and with the following
conditions: input signal amplitudes are within 10% of the
nominal; phase shift between signal and reference is less than
10 degrees.

These operating conditions are selected primarily to establish a
repeatable acceptance test procedure which can be traced to
national standards. In practice, the AD2S81A/AD2S82A can be
used well outside these operating conditions providing the above
points are observed.

VELOCITY SIGNAL

The tracking converter technique generates an internal signal at
the output of the integrator (the INTEGRATOR O/P pin) that
is proportional to the rate of change of the input angle. This is a
dc analog output referred to as the VELOCITY signal.

In many applications it is possible to use the velocity signal of
the AD2S81A/AD2S82A to replace a conventional
tachogenerator.

DC ERROR SIGNAL

The signal at the output of the phase-sensitive detector (DEMOD
O/P) is the signal to be nulled by the tracking loop and is, there-
fore, proportional to the error between the input angle and the
output digital angle. This is the dc error of the converter; and as
the converter is a type 2 servo loop, it will increase if the output
fails to track the input for any reason. It is an indication that the
input has exceeded the maximum tracking rate of the converter
or, due to some internal malfunction, the converter is unable to
reach a null. By connecting two external comparators, this volt-
age can be used as a "built-in test."

CONVERTER RESOLUTION (AD2S82A ONLY)

Two major areas of the AD2S82A specification can be selected
by the user to optimize the total system performance. The reso-
lution of the digital output is set by the logic state of the inputs
SC1 and SC2 to be 10, 12, 14 or 16 bits and the dynamic char-
acteristics of bandwidth and tracking rate are selected by the
choice of external components.

The choice of the resolution will affect the values of R4 and R6
which scale the inputs to the integrator and the VCO, respec-
tively (see the Component Selection section). If the resolution is
changed, then new values of R4 and R6 must be switched into
the circuit.

Note: When changing resolution under dynamic conditions, do
it when the BUSY is low, i.e., when Data is not changing.

CONVERTER OPERATION

When connected in a circuit such as shown in Figure 1, the
AD2S81A/AD2S82A operates as a tracking resolver-to-digital
converter and forms a type 2 closed loop system. The output
will automatically follow the input for speeds up to the selected
maximum tracking rate. No convert command is necessary as
the conversion is automatically initiated by each LSB increment,
or decrement, of the input. Each LSB change of the converter
initiates a BUSY pulse.

The AD2S81A/AD2S82A is remarkably tolerant of input ampli-
tude and frequency variation because the conversion depends
only on the ratio of the input signals. Consequently there is no
need for accurate, stable oscillator to produce the reference
signal. The inclusion of the phase sensitive detector in the con-
version loop ensures a high immunity to signals that are not
coherent or are in quadrature with the reference signal.

SIGNAL CONDITIONING

The amplitude of the SINE and COSINE signal inputs should
be maintained within 10% of the nominal values if full perfor-
mance is required from the velocity signal.

The digital position output is relatively insensitive to amplitude
variation. Increasing the input signal levels by more than 10%
will result in a loss in accuracy due to internal overload. Reduc-
ing levels will result in a steady decline in accuracy. With the
signal levels at 50% of the correct value, the angular error will
increase to an amount equivalent to 1.3 LSB. At this level the
repeatability will also degrade to 2 LSB and the dynamic re-
sponse will also change, since the dynamic characteristics are
proportional to the signal level.

The AD2S81A/AD2S82A will not be damaged if the signal
inputs are applied to the converter without the power supplies
and/or the reference.

REFERENCE INPUT

The amplitude of the reference signal applied to the converter's
input is not critical, but care should be taken to ensure it is kept
within the recommended operating limits.

The AD2S81A/AD2S82A will not be damaged if the reference
is supplied to the converter without the power supplies and/or
the signal inputs.

REV. B

AD2S81A/AD2S82A

COMPONENT SELECTION

The following instructions describe how to select the external
components for the converter in order to achieve the required
bandwidth and tracking rate. In all cases the nearest "preferred
value'' component should be used and a 5% tolerance will not
degrade the overall performance of the converter. Care should
be taken that the resistors and capacitors will function over the
required operating temperature range. The components should
be connected as shown in Figure 1.

PC compatible software is available to help users select the optimum
component values for the AD2S81A and AD2S82A, and display the
transfer gain, phase and small step response.

For more detailed information and explanation, see the Circuit
Functions and Dynamic Performance section.

1. HF Filter (R1, R2, C1, C2)

The function of the HF filter is to remove any dc offset and
to reduce the amount of noise present on the signal inputs
to the AD2S81A/AD2S82A, reaching the Phase Sensitive
Detector and affecting the outputs. R1 and C2 may be omit-
ted--in which case R2 = R3 and C1 = C3, calculated below--
but their use is particularly recommended if noise from
switch mode power supplies and brushless motor drive is
present.

Values should be chosen so that

15 k

56 k

R1 f

REF

and f

REF

= Reference Frequency

(Hz)

This filter gives an attenuation of three times at the input to
the phase sensitive detector.

2. Gain Scaling Resistor (R4)

If R1, C2 are fitted, then:

100

where 100

= current/LSB

If R1, C2 are not fitted, then:

100

where E

= 160

for 10 bits resolution

= 40

for 12 bits

= 10

for 14 bits

= 2.5

for 16 bits

= Scaling of the DC ERROR in volts

3. AC Coupling of Reference Input (R3, C3)

Select R3 and C3 so that there is no significant phase shift at
the reference frequency. That is,

R 3

100 k

C 3

R 3

REF

with R3 in

4. Maximum Tracking Rate (R6)

The VCO input resistor R6 sets the maximum tracking rate
of the converter, and hence the velocity scaling as at the max
tracking rate, the velocity output will be 8 V.

Decide on your maximum tracking rate, "T," in revolutions
per second. Note that "T" must not exceed the maximum
tracking rate or 1/16 of the reference frequency.

6. 32

where n = bits per revolution

= 1,024 for 10 bits resolution
= 4,096 for 12 bits
= 16,384 for 14 bits
= 65,536 for 16 bits

5. Closed-Loop Bandwidth Selection (C4, C5, R5)

a. Choose the closed-loop bandwidth (f

) required

ensuring that the ratio of reference frequency to band-
width does exceed the following guidelines:

Resolution

Ratio of Reference Frequency/Bandwidth

2.5 : 1

: 1

7.5 : 1

Typical values may be 100 Hz for a 400 Hz reference fre-
quency and 500 Hz to 1000 Hz for a 5 kHz reference
frequency.

b. Select C4 so that

with R6 in

and f

, in Hz selected above.

c. C5 is given by

C4 F

d. R5 is given by

× ×

6. VCO Phase Compensation

The following values of C6 and R7 should be fitted.

470 pF, R7

7. Offset Adjust

Offsets and bias currents at the integrator input can cause an
additional positional offset at the output of the converter of
1 arc minute typical, 5.3 arc minutes maximum. If this can be
tolerated, then R8 and R9 can be omitted from the circuit.

If fitted, the following values of R8 and R9 should be used:

4.7 M

, R9

1 M

potentiometer

To adjust the zero offset, ensure the resolver is disconnected
and all the external components are fitted. Connect the COS
pin to the REFERENCE I/P and the SIN pin to the SIGNAL
GND and with the power and reference applied, adjust the
potentiometer to give all "0s" on the digital output bits.

The potentiometer may be replaced with select on test resistors
if preferred.

AD2S81A/AD2S82A

REV. B

If the AD2S81A/AD2S82A is being used in a pitch and revolu-
tion counting application, the ripple and busy will need to be
gated to prevent false decrement or increment (see Figure 2).
RIPPLE CLK is unaffected by

INHIBIT.

RIPPLE

CLK

BUSY

1N4148

1N414
8

10k

TO COUNTER
(CLOCK)

2N3904

5k1

NOTE: DO NOT USE ABOVE CCT WHEN

INHIBIT

IS "LO."

+5V

Figure 2. Diode Transistor Logic Nand Gate

DIRECTION Output

The DIRECTION (DIR) logic output indicates the direction of
the input rotation. Any change in the state of DIR precedes the
corresponding BUSY, DATA, and RIPPLE CLK updates. DIR
can be considered as an asynchronous output and can make
multiple changes in state between two consecutive LSB update
cycles. This corresponds to a change in input rotation direction
but less than 1 LSB.

COMPLEMENT (AD2S82A Only)

The

COMPLEMENT input is internally pulled to +12 V in the

INACTIVE STATE. It is pulled down to DIGITAL GROUND
(100

A) to ACTIVATE.

When used in conjunction with DATA LOAD, strobing DATA
LOAD and

COMPLEMENT pins to logic LO, will set the logic

HIGH bits of the AD2S82A counter to a LO state. Those bits of
the applied data which are logic LO will not change the corre-
sponding bits in the AD2S82A counter:

For Example:

Initial Counter State

1 0 1 0 1

Applied Data Word

1 1 0 0 0

Counter State after Data Load

1 1 0 0 0

Initial Counter State

1 0 1 0 1

Applied Data Word

1 1 0 0 0

Counter State after Data Load and Complement

0 0 1 0 1

In order to read the output the following procedures should be
followed:

1. Place Outputs in high impedance (

ENABLE = HI).

2. Present data to pins.
3. Pull DATA LOAD and

COMPLEMENT pins to ground.

4. Wait 100 ns.
5. Remove data from pins.
6. Remove outputs from high impedance state (

ENABLE =

LO).

7. Read outputs.

DATA TRANSFER

To transfer data the

INHIBIT input should be used. The data

will be valid 600 ns after the application of a logic "LO" to the
INHIBIT. This is regardless of the time when the INHIBIT is
applied and allows time for an active BUSY to clear. By using
the

ENABLE input the two bytes of data can be transferred

after which the

INHIBIT should be returned to a logic "HI"

state to enable the output latches to be updated.

BUSY Output

The validity of the output data is indicated by the state of the
BUSY output. When the input to the converter is changing, the
signal appearing on the BUSY output is a series of pulses at
TTL level. A BUSY pulse is initiated each time the input moves
by the analog equivalent of one LSB and the internal counter is
incremented or decremented.

INHIBIT Input

The

INHIBIT logic input only inhibits the data transfer from

the up-down counter to the output latches and, therefore, does
not interrupt the operation of the tracking loop. Releasing the
INHIBIT automatically generates a BUSY pulse to refresh the
output data.

ENABLE Input

The

ENABLE input determines the state of the output data. A

logic "HI" maintains the output data pins in the high impedance
condition, and the application of a logic "LO" presents the data
in the latches to the output pins. The operation of the

ENABLE

has no effect on the conversion process.

BYTE SELECT Input

The BYTE SELECT input on the AD2S82A selects the byte of
the position data to be presented at the data output DB1 to
DB8. The least significant byte will be presented on data output
DB9 to DB16 (with the

ENABLE input taken to a logic "LO")

regardless of the state of the BYTE SELECT pin. Note that
when the AD2S82A is used with a resolution less than 16 bits,
the unused data lines are pulled to a logic "LO." A logic "HI"
on the BYTE SELECT input will present the eight most signifi-
cant data bits on data output DB1 and DB8. A logic "LO" will
present the least significant byte on data outputs 1 to 8, i.e.,
data outputs 1 to 8 will duplicate data outputs 9 to 16.

When the BYTE select pin is a logic "HI" on the AD2S81A, the
most significant byte is presented on Pins 8 to 15 (with the
ENABLE input taken to a logic "LO"). A logic "HI" presents
the 4 least significant bits on Pins 8 to 11 and places a logic
"LO" on Pins 12 to 15 (with the

ENABLE input taken to a

logic "LO").

The operation of the BYTE SELECT has no effect on the con-
version process of the converter.

RIPPLE CLOCK

As the output of the converter passes through the major carry,
i.e., all "1s" to all "0s" or the converse, a positive going edge on
the RIPPLE CLK output is initiated indicating that a revolu-
tion, or a pitch, of the input has been completed.

The minimum pulsewidth of the ripple clock is 300 ns. RIPPLE
CLK is normally set high before a BUSY pulse and resets before
the next positive going edge of the next consecutive pulse.

The only exception to this is when DIR changes while the
RIPPLE CLK is high. Resetting of the RIPPLE CLK will only
occur if the DIR remains stable for two consecutive positive
BUSY pulse edges.

REV. B

AD2S81A/AD2S82A

BUSY

RIPPLE

CLK

DATA

DIR

DATA

BYTE

SELECT

DATA

ENABLE

INHIBIT

PARAMETER

MIN

MAX

CONDITION

200

600

BUSY WIDTH V

RIPPLE CLOCK V

TO BUSY V

470

580

RIPPLE CLOCK V

TO NEXT BUSY V

BUSY V

TO DATA V

BUSY V

TO DATA V

140

INHIBIT V

TO BUSY V

485

625

MIN DIR V

TO BUSY V

515

670

MIN DIR V

TO BUSY V

600

INHIBIT V

TO DATA STABLE

110

ENABLE V

TO DATA V

110

ENABLE V

TO DATA V

140

BYTE SELECT V

TO DATA STABLE

125

BYTE SELECT V

TO DATA STABLE

Figure 3. Digital Timing

PHASE-

SENSITIVE

DEMODULATOR

AC ERROR

RATIO

MULTIPLIER

A1 sin (

 ) sin t

sin

sin t

cos

sin t

DIGITAL

VCO

VELOCITY

CLOCK

DIRECTION

INTEGRATOR

Figure 4. AD2S81A/AD2S82A Functional Diagram

CIRCUIT FUNCTIONS AND DYNAMIC
PERFORMANCE

The AD2S81A/AD2S82A allows the user greater flexibility in
choosing the dynamic characteristics of the resolver-to-digital
conversion to ensure the optimum system performance. The
characteristics are set by the external components shown in
Figure 1, and the Component Selection section explains how to
select desired maximum tracking rate and bandwidth values.
The following paragraphs explain in greater detail the circuit of
the AD2S81A/AD2S82A and the variations in the dynamic
performance available to the user.

Loop Compensation

The AD2S81A and AD2S82A (connected as shown in Figure
1a and 1b) operates as a type 2 tracking servo loop where the
VCO/counter combination and integrator perform the two inte-
gration functions inherent in a type 2 loop.

Additional compensation in the form of a pole/zero pair is re-
quired to stabilize any type 2 loop to avoid the loop gain charac-
teristic crossing the 0 dB axis with 180

of additional phase lag,

as shown in Figure 6. This compensation is implemented by the
integrator components (R4, C4, R5, C5).

The overall response of such a system is that of a unity gain
second order low pass filter, with the angle of the resolver as the
input and the digital position data as the output.

The AD2S81A/AD2S82A does not have to be connected as
tracking converter, parts of the circuit can be used indepen-
dently. This is particularly true of the Ratio Multiplier which
can be used as a control transformer (see Application Note).

A block diagram of the AD2S81A/AD2S82A is given in
Figure 4.

AD2S81A/AD2S82A

REV. B

Phase Sensitive Demodulator

The phase sensitive demodulator is effectively ideal and devel-
ops a mean dc output at the DEMODULATOR O/P pin of

2 2

(

)

DEMODULATOR I P rms voltage

for sinusoidal signals in phase or antiphase with the reference
(for a square wave the DEMODULATOR O/P voltage will
equal the DEMODULATOR I/P). This provides a signal at the
DEMODULATOR O/P which is a dc level proportional to the
positional error of the converter.

DC Error Scaling = 160 mV/bit (10-bits resolution)

= 40 mV/bit

(12-bits resolution)

= 10 mV/bit

(14-bits resolution)

= 2.5 mV/bit (16-bits resolution)

When the tracking loop is closed, this error is nulled to zero
unless the converter input angle is accelerating.

Integrator

The integrator components (R4, C4, R5, C5) are external to
the AD2S81A/AD2S82A to allow the user to determine the
optimum dynamic characteristics for any given application. The
Component Selection section explains how to select compo-
nents for a chosen bandwidth.

Since the output from the integrator is fed to the VCO INPUT,
it is proportional to velocity (rate of change of output angle)
and can be scaled by selection of R6, the VCO input resistor.
This is explained in the Voltage Controlled Oscillator (VCO)
section below.

To prevent the converter from "flickering" (i.e., continually
toggling by

1 bit when the quantized digital angle,

, is not an

exact representation of the input angle,

), feedback is internally

applied from the VCO to the integrator input to ensure that the
VCO will only update the counter when the error is greater than
or equal to 1 LSB. In order to ensure that this feedback "hyster-
esis" is set to 1 LSB the input current to the integrator must be
scaled to be 100 nA/bit. Therefore,

DC Error Scaling (mV /bit )

100 (nA /bit )

Any offset at the input of the integrator will affect the accuracy
of the conversion as it will be treated as an error signal and
offset the digital output. One LSB of extra error will be
added for each 100 nA of input bias current. The method of
adjusting out this offset is given in the Component Selection
section.

Voltage Controlled Oscillator (VCO)

The VCO is essentially a simple integrator feeding a pair of dc
level comparators. Whenever the integrator output reaches one
of the comparator threshold voltages, a fixed charge is injected
into the integrator input to balance the input current. At the
same time the counter is clocking either up or down, dependent
on the polarity of the input current. In this way the counter is
clocked at a rate proportional to the magnitude of the input
current of the VCO.

Ratio Multiplier

The ratio multiplier is the input section of the AD2S81A/
AD2S82A and compares the signal from the resolver input
angle,

, to the digital angle,

, held in the counter. Any differ-

ence between these two angles results in an analog voltage at
the AC ERROR OUTPUT. This circuit function has histori-
cally been called a "Control Transformer" as it was originally
performed by an electromechanical device known by that name.

The AC ERROR signal is given by

A1 sin (

) sin

where

= 2

REF

REF =

reference frequency

A1, the gain of the ratio multiplier stage is 14.5.

So for 2 V rms inputs signals
AC ERROR output in volts/(bit of error)

sin

360

Where n = bits per rev
= 1,024 for 10-bits resolution
= 4,096 for 12 bits
= 16,384 for 14 bits
= 65,536 for 16 bits

Giving an AC ERROR O/P
= 178 mV/bit @ 10-bits resolution
= 44.5 mV/bit @ 12 bits
= 11.125 mV/bit @ 14 bits
= 2.78 mV/bit @ 16 bits

The ratio multiplier will work in exactly the same way whether
the AD2S81A/AD2S82A is connected as a tracking converter or
as a control transformer, where data is preset into the counters
using the DATA LOAD pin.

HF Filter

The AC ERROR OUTPUT may be fed to the PSD via a simple
ac coupling network (R2, C1) to remove any dc offset at this
point. Note, however, that the PSD of the AD2S81A/AD2S82A
is a wideband demodulator and is capable of aliasing HF noise
down to within the loop bandwidth. This is most likely to hap-
pen where the resolver is situated in particularly noisy environ-
ments, and the user is advised to fit a simple HF filter R1, C2
prior to the phase sensitive demodulator.

The attenuation and frequency response of a filter will affect the
loop gain and must be taken into account in deriving the loop
transfer function. The suggested filter (R1, C1, R2, C2) is shown
in Figure 1 and gives an attenuation at the reference frequency
(f

REF

) of 3 times at the input to the phase sensitive demodulator.

Values of components used in the filter must be chosen to en-
sure that the phase shift at f

REF

is within the allowable signal to

reference phase shift of the converter.

REV. B

AD2S81A/AD2S82A

During the reset period the input continues to be integrated, the
reset period is constant at 400 ns.

The VCO rate is fixed for a given input current by the VCO
scaling factor:

7.9 kHz /

The tracking rate in rps per

A of VCO input current can be

found by dividing the VCO scaling factor by the number of LSB
changes per rev (i.e., 4096 for 12-bit resolution).

The input resistor R6 determines the scaling between the con-
verter velocity signal voltage at the INTEGRATOR O/P pin and
the VCO input current. Thus to achieve a 5 V output at 100 rps
(6000 rpm) and 12-bit resolution the VCO input current must
be:

(100

4096) / (7900)

51.8

Thus, R6 would be set to: 5/(51.8

-6

) = 96 k

The velocity offset voltage depends on the VCO input resistor,
R6, and the VCO bias current and is given by

Velocity Offset Voltage

(VCO bias current )

The temperature coefficient of this offset is given by

Velocity Offset Tempco

(VCO bias current tempco)

where the VCO bias current tempco is typically 1.22 nA/

The maximum recommended rate for the VCO is 1.1 MHz
which sets the maximum possible tracking rate.

Since the minimum voltage swing available at the integrator
output is

8 V, this implies that the minimum value for R6 is

57 k

. As

Max Current

1.1

7.9

139

Min Value R6

139

57 k

VCO OUTPUT

In order to overcome the "freeplay" inherent in a servo system
using digitized position feedback, an analog output voltage is
available representing the resolver shaft position within the least
significant bit of digital angle output.

The converter updates the output if the error is an LSB or
greater and the VCO output gives the positional error smaller
than 1 LSB.

INPUT

ANGLE

VCO

OUTPUT

+3V

3V

+LSB

LSB

DIGITAL COUNT OUTPUT

Figure 5.

Figure 5 illustrates how the VCO output compensates for in-
stances where, due to hysteresis, there is no change in the digital
count output for 1 LSB change in input angle. The sum of the
digital count output and VCO output equals the actual input
angle.

Transfer Function

By selecting components using the method outlined in the
Component Selection section, the converter will have a critically
damped time response and maximum phase margin. The
Closed-Loop Transfer Function is given by:

OUT

14 (1

)

2.4)(s

3.4 s

5.8)

where S

, the normalized frequency variable, is:

and f

is the closed loop 3 dB bandwidth (selected by the

choice of external components).

The acceleration constant, K

, is given approximately by

( f

)

sec

The normalized gain and phase diagrams are given in Figures
6 and 7.

12

0.02

0.04

0.1

0.2

0.4

FREQUENCY 

GAIN PLOT

Figure 6. AD2S81A/AD2S82A Gain Plot

180

45

90

135

180

0.02

0.04

0.1

0.2

0.4

FREQUENCY 

135

PHASE PLOT

Figure 7. AD2S81A/AD2S82A Phase Plot

AD2S81A/AD2S82A

REV. B

The small signal step response is shown in Figure 8. The time
from the step to the first peak is t

and the t

is the time from

the step until the converter is settled to 1 LSB. The times t

and

are given approximately by

where R = resolution, i.e., 10, 12, 14 or 16.

TIME

OUTPUT

POSITION

Figure 8. AD2S81A/AD2S82A Small Step Response

The large signal step response (for steps greater than 5 degrees)
applies when the error voltage exceeds the linear range of the
converter.

Typically the converter will take three times longer to reach the
first peak for a 179 degrees step.

In response to a velocity step, the velocity output will exhibit
the same time response characteristics as outlined above for the
position output.

ACCELERATION ERROR

A tracking converter employing a type 2 servo loop does not
suffer any velocity lag, however, there is an additional error due
to acceleration. This additional error can be defined using the
acceleration constant K

of the converter.

Input Acceleration

Error in Output Angle

The numerator and denominator must have consistent angular
units. For example, if K

is in sec

, then the input acceleration

may be specified in degrees/sec

and the error output in degrees.

Angular measurement may also be specified using radians, min-
utes of arc, LSBs, etc.

does not define maximum input acceleration, only the error due

to it's acceleration. The maximum acceleration allowable before
the converter loses track is dependent on the angular accuracy
requirements of the system.

Angular Accuracy

= degrees/sec

can be used to predict the output position error for a given

input acceleration. For example for an acceleration of 100 revs/
sec

, K

= 2.7

sec

and 12-bit resolution.

To determine the value of K

based on the passive components

used to define the dynamics of the converter, the following
should be used:

4.04

(C4

C5)

Where n = resolution of the converter

R4, R6 in ohms

C5, C4 in farads

SOURCES OF ERRORS
Integrator Offset

Additional inaccuracies in the conversion of the resolver signals
will result from an offset at the input to the integrator as it will
be treated as an error signal. This error will typically be 1 arc
minute over the operating temperature range.

A description of how to adjust from zero offset is given in the
Component Selection section and the circuit required is shown
in Figures 1a and 1b.

Differential Phase Shift

Phase shift between the sine and cosine signals from the resolver
is known as differential phase shift and can cause static error.
Some differential phase shift will be present on all resolvers as a
result of coupling. A small resolver residual voltage (quadrature
voltage) indicates a small differential phase shift. Additional
phase shift can be introduced if the sine channel wires and the
cosine channel wires are treated differently. For instance, differ-
ent cable lengths or different loads could cause differential
phase shift.

The additional error caused by differential phase shift on the
input signals approximates to

Error = 0.53 a

b arc minutes

where a = differential phase shift (degrees).

b = signal to reference phase shift (degrees).

This error can be minimized by choosing a resolver with a small
residual voltage, ensuring that the sine and cosine signals are
handled identically and removing the reference phase shift (see
Connecting the Resolver section). By taking these precautions
the extra error can be made insignificant.

Under static operating conditions phase shift between the refer-
ence and the signal lines alone will not theoretically affect the
converter's static accuracy.

However, most resolvers exhibit a phase shift between the signal
and the reference. This phase shift will give rise under dynamic
conditions to an additional error defined by:

Shaft Speed (rps)

Phase Shift (Degrees )

Reference Frequency

Error in LSBs

Input Acceleration LSB

rev

LSBs or

of arc

[

]

[

]

[

]

sec

seconds

100

2 7 10

0 15

47 5

REV. B

AD2S81A/AD2S82A

Following the preceding precautions will allow the user to use
the velocity signal in very noisy environments for example PWM
motor drive applications. Resolver/converter error curves may
exhibit apparent acceleration/deceleration at a constant velocity.
This results in ripple on the velocity signal of frequency twice
the input rotation.

CONNECTING THE RESOLVER

The recommended connection circuit is shown in Figure 9.

TWISTED PAIR

SCREENED

CABLE

POWER RETURN

RESOLVER

REF I/P

AD2S82A

COS I/P

ANALOG
GND

SIGNAL
GND

SIN I/P

DIGITAL

GND

OSCILLATOR

(e. g. OSC1758)

Figure 9. Connecting the AD2S82A to a Resolver

In cases where the reference phase relative to the input signals
from the resolver requires adjustment, this can be easily
achieved by varying the value of the resistor R2 of the HF filter
(see Figures 1a and 1b).

Assuming that R1 = R2 = R and C1 = C2 = C

and Reference Frequency =

by altering the value of R2, the phase of the reference relative to
the input signals will change in an approximately linear manner
for phase shifts of up to 10 degrees.

Increasing R2 by 10% introduces a phase lag of 2 degrees. De-
creasing R2 by 10% introduces a phase lead of 2 degrees.

PHASE LEAD = ARC TAN

fRC

PHASE LAG = ARC TAN 2

fRC

Figure 10. Phase Shift Circuits

For example, for a phase shift of 20 degrees, a shaft rotation of
22 rps and a reference frequency of 5 kHz, the converter will
exhibit an additional error of:

5000

0.088 degrees

This effect can be eliminated by putting a phase shift in the
reference to the converter equivalent to the phase shift in the
resolver (see Connecting the Resolver section).

Note: Capacitive and inductive crosstalk in the signal and reference
leads and wiring can cause similar problems.

VELOCITY ERRORS

The signal at the INTEGRATOR O/P pin relative to the ANA-
LOG GND pin is an analog voltage proportional to the rate of
change of the input angle. This signal can be used to stabilize
servo loops or in the place of a velocity transducer. Although the
conversion loop of the AD2S81A/AD2S82A includes a digital
section, there is an additional analog feedback loop around the
velocity signal. This ensures against flicker in the digital posi-
tional output in both dynamic and static states.

A better quality velocity signal will be achieved if the following
points are considered:

1. Protection.

The velocity signal should be buffered before use.

2. Reversion error*

The reversion error can be nulled by varying one supply rail
relative to the other.

3. Ripple and Noise.

Noise on the input signals to the converter is the major cause of
noise on the velocity signal. This can be reduced to a minimum
if the following precautions are taken:

The resolver is connected to the converter using separate
twisted pair cable for the sine, cosine and reference signals.

Care is taken to reduce the external noise wherever possible.

An HF filter is fitted before the Phase-Sensitive Demodulator
(as described in the section HF FILTER).

A resolver is chosen that has low residual voltage, i.e., a small
signal in quadrature with the reference.

Components are selected to operate the AD2S81A/AD2S82A
with the lowest acceptable bandwidth.

Feedthrough of the reference frequency should be removed
by a filter on the velocity signal.

Maintenance of the input signal voltages at 2 V rms will
prevent LSB flicker at the positional output. The analog
feedback or hysteresis employed around the VCO and the
integrator is a function of the input signal levels (see Integra-
tor section).

Reversion error, or side-to-side nonlinearity, is a result of differences in the up and

down rates of the VCO.

AD2S81A/AD2S82A

REV. B

For more information on resistive scaling of SIN, COS and
REFERENCE converter inputs, refer to the application note
"Circuit Applications of the 2S81 and 2S80 Resolver-to-Digital
Converters."

APPLICATIONS
Control Transformer

The ratio multiplier of the AD2S82A can be used independently
of the loop integrators as a control transformer. In this mode the
resolver inputs

are multiplied by a digital angle

, any differ-

ence between and

and

will be represented by the AC ERROR

output as SIN

sin (

) or the DEMOD output as sin (

To use the AD2S81A/AD2S82A in this mode refer to the
"Control Transformer" application note.

Dynamic Switching

In applications where the user requires wide band response from
the converter, for example 100 rpm to 6000 rpm, superior per-
formance is achieved if the converters control characteristics are
switched dynamically. This reduces velocity offset levels at low
tracking rates. For more information on the technique refer to
"Dynamic Resolution Switching Using the Variable Resolution
Monolithic Resolver-to-Digital Converters."

OTHER PRODUCTS

The AD2S80A is a monolithic resolver-to-digital converter
offering 1016 bits of resolution and user selectable dynamics.
The AD2S80A is also available in 40-lead ceramic DIP, 44-lead
LCC and is qualified to MIL-STD 883B Rev C.

The AD2S46 is a highly integrated hybrid resolver/synchro to
digital converter packaged in a 28-lead ceramic DIP. The part
offers the user 1.3 arc minutes of accuracy over the full military
temperature range.

The AD2S34 is a dual channel 14-bit hybrid resolver-to-digital
converter packaged in a 1 in

32-lead flatpack.

The 1740/41/42 are hybrid resolver/synchro to digital converters
which incorporate pico-transformer isolated input signal
conditioning.

TYPICAL CIRCUIT CONFIGURATION

Figure 11 shows a typical circuit configuration for the AD2S81A/
AD2S82A in a 12-bit resolution mode. Values of the external
components have been chosen for a reference frequency of 5 kHz
and a maximum tracking rate of 260 rps with a bandwidth of
520 Hz. Placing the values for R4, R6, C4 and C5 in the equa-
tion for K

gives a value of 2.7

. The resistors are 0.125 W,

5% tolerance preferred values. The capacitors are 100 V ceramic,
10% tolerance components.

For signal and reference voltages greater than 2 V rms a simple
voltage divider circuit of resistors can be used to generate the
correct signal level at the converter. Care should be taken to
ensure that the ratios of the resistors between the sine signal line
and ground and the cosine signal line and ground are the same.
Any difference will result in an additional position error.

TIME ms

360

ANGLE Degrees

315

180

135

270

225

Figure 12. Large Step Response Curves for Typical Circuit
Shown in Figure 11

RIPPLE CLK

DIRECTION

BUSY

DATA LOAD

BYTE SELECT

12V

MSB

LSB

VELOCITY
O/P

+5V

15k

22nF

PIN 1
IDENTIFIER

18 19 20 21 22 23 24 25 26 27 28

44 43 42 41 40

AD2S82A

TOP VIEW

(Not to scale)

COS HIGH

REF LOW

COS LOW

SIN LOW

COMPLEMENT

SC2

15k

22nF

100k

100nF

+12V

SIN HIGH

REFERENCE

INPUT

470pF

39k

110k

180k

1.5nF

6.8nF

100nF

4.7M

INHIBIT

ENABLE

DATA OUTPUT

RESOLVER

SIGNAL

DATA

OUTPUT

Figure 11. Typical Circuit Configuration

Part Number AD2S81A