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AD1991

Class D/1-Bit Audio Power Output Stage

FUNCTIONAL BLOCK DIAGRAMS

2-Channel Mode

INA

INB

LEFT

INPUT

LEVEL SHIFTER

AND

SWITCH CONTROL

H-BRIDGE

AGND DGND

TEST

CONTROL

PGND

OUTA

OUTB

OUTC

OUTD

INC

IND

RIGHT

INPUT

CLK

RST/PDN

MUTE

CURRENT OVERLOAD
THERMAL SHUTDOWN
THERMAL WARNING
DATA LOSS

THERMAL PROTECTION
SHORT-CIRCUIT PROTECTION
MUTE CONTROL

4-Channel Mode

INA

INB

LEVEL SHIFTER

AND

SWITCH CONTROL

H-BRIDGE

AGND DGND

TEST

CONTROL

PGND

INC

IND

CLK

RST/PDN

MUTE

CURRENT OVERLOAD
THERMAL SHUTDOWN
THERMAL WARNING
DATA LOSS

THERMAL PROTECTION
SHORT-CIRCUIT PROTECTION
MUTE CONTROL

OUTA

LOAD
REQUIRING
DC VOLTAGE
SUPPLY

OUTD

LOAD
REQUIRING
DC VOLTAGE
SUPPLY

OUTB

OUTC

FEATURES
Class D/1-Bit Audio Power Output Stage
5 V Analog and Digital Supply Voltages
Power Stage Power Supply 8 V to 20 V
Output Power @ 0.1% THD + N

Stereo Mode

2 20 W @ 4 @ 14.4 V
2 20 W @ 8 @ 20 V

Mono Mode

1 40 W @ 4 @ 20 V

< 320 m (per Transistor)

Efficiency > 85% @ Full Power/8
Clickless Mute Function
Turn-On and Turn-Off Pop Suppression
Short-Circuit Protection
Overtemperature Protection
Data Loss Protection
2-Channel BTL Outputs or

4-Channel Single-Ended Outputs

52-Lead Exposed Pad TQFP Package
Low Cost DMOS Process

APPLICATIONS
PC Audio Systems
Minicomponents
Automotive Amplifiers
Home Theater Systems
Televisions

GENERAL DESCRIPTION

The AD1991 is a 2-channel BTL or 4-channel single-ended
class D audio power output stage. The part is configured during
reset to be in either 2-channel mode or 4-channel mode.

To protect the IC as well as the connected speakers, the AD1991
provides turn-on and turn-off pop suppression, short-circuit
protection, and overtemperature shutdown. To control the IC,
a power-down/reset input and a mute pin are available.

The output stage can be operated over a power supply range
from 8 V to 20 V.

In 2-channel mode, Transistors A1, B2, C1, and D2 are turned
on by a Logic 1 on inputs INA and INC, and Transistors A2,
B1, C2, and D1 are turned on by a Logic 0 on inputs INA and
INC. In 4-channel mode, Transistors A1, B1, C1, and D1 are
turned on by a Logic 1 on the four inputs, and Transistors A2,
B2, C2, and D2 are turned on by a Logic 0 on the four inputs
(see the Functional Block Diagrams).

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AD1991SPECIFICATIONS

Parameter

Min

Typ

Max

Unit

Test Conditions

OUTPUT POWER P

(f = 1 kHz SINE WAVE)

= 4

, PV

DDX

= 14 V

= 8

, PV

DDX

= 20 V

EFFICIENCY

f = 1 kHz, P

= 20 W, R

= 8

Per High-Side Transistor

260

320

@ 1 A

Per Low-Side Transistor

190

235

@ 1 A

Temperature Coefficient

0.7

/°C

THERMAL WARNING ACTIVE

135

°C

Die temperature

THERMAL SHUTDOWN ACTIVE

150

°C

Die temperature

OVERCURRENT SHUTDOWN ACTIVE

3.8

6.75

POWER SUPPLIES

Supply Voltage AV

4.5

5.0

5.5

Supply Voltage DV

4.5

5.0

5.5

Supply Voltage PV

DDX

6.5

8 to 20

22.5

Power-Down Current

µA

RST/PDN held low

µA

RST/PDN held low

DDX

µA

RST/PDN held low

Operating Current

1.8

2.75

5.2

DDX

50:50 384 kHz square wave on
INA and INC

DIGITAL I/O

Input Voltage High

2.0

Input Voltage Low

1.2

Output Voltage High

0.8

@ 2 mA

Output Voltage Low

0.4

@ 2 mA

Leakage Current on Digital Inputs

µA

NOTES

Performance of both channels is identical.

Measurement requires PWM modulator.

Specifications subject to change without notice.

DIGITAL TIMING CHARACTERISTICS

Symbol

Parameter

Min

Typ

Max

Unit

PDL

Input transition to output initial response

PST

Power transistor switching time

3.5

NOL

Nonoverlap time

25 to 40

PDRP

RST/PDN minimum low pulsewidth

MSU

Mode pin setup time before

RST/PDN going high

Mode pin hold time after

RST/PDN going high

MPDL

MUTE asserted to output initial response

Specifications subject to change without notice.

(Guaranteed over 40 C to +85 C, AV

= DV

= 5 V

10%, PV

DDX

= 20 V

10%,

Edge Speed = Slowest, Nonoverlap Time = Shortest.)

(AV

= 5 V, DV

= 5 V, PV

DDX

= 20 V, Ambient Temperature = 25 C,

Load Impedance = 8

, unless otherwise noted.)

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AD1991

ABSOLUTE MAXIMUM RATINGS

= 25

°C, unless otherwise noted.)

, DV

to AGND, DGND . . . . . . . . . . 0.3 V to +6.5 V

DDX

to PGNDx

. . . . . . . . . . . . . . . . . . . 0.3 V to +30.0 V

AGND to DGND to PGNDx . . . . . . . . . . . . 0.3 V to +0.3 V
AV

to DV

. . . . . . . . . . . . . . . . . . . . . . . 0.5 V to +0.5 V

Operating Temperature Range (Ambient)

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . 40

°C to +85°C

Storage Temperature Range . . . . . . . . . . . . 65

°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150

°C

Thermal Resistance

. . . . . . . . . . . . . . . . . . . . . . . 1

°C/W

Lead Temperature

Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

°C

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215

°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

°C

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD1991 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

NOTES

Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.

Including any induced voltage due to inductive load.

With respect to the temperature of the exposed pad.

ORDERING GUIDE

Temperature

Package

Model

Range

Description

Option

AD1991ASV

°C to +85°C

Thin Quad Flat Pack [TQFP]

SV-52

AD1991ASVRL

°C to +85°C

Thin Quad Flat Pack [TQFP]

SV-52

EVAL-AD1991EB

Evaluation Board

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AD1991

PIN CONFIGURATION

52 51 50 49 48

43 42 41 40

47 46 45 44

14 15 16 17 18 19 20 21 22 23 24 25 26

PIN 1
IDENTIFIER

TOP VIEW

(Not to Scale)

AD1991

PGND1

OUTA

PGND1

PGND2

OUTA

OUTB

DD1

OUTC

OUTD

DD2

PGND1

AGND

PGND2

MODE1

MODE0

DGND

ERR3

ERR2

ERR1

ERR0

INA

INB

MUTE

RST

/
PDN

CLK

IND

INC

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic In/Out

Description

PGND1

Negative power supply for high power Transistors A2 and B2.

2, 3, 4

OUTA

Output of transistor pair A1 and A2.

5, 6, 7

DD1

Positive power supply for high power Transistors A1 and B1.

8, 9, 10

OUTB

Output of transistor pair B1 and B2.

11, 12, 13

PGND1

Negative power supply for high power Transistors A2 and B2.

ERR3

I/O

Edge speed setting MSB during RESET/active low thermal shutdown error output during
normal operation.

ERR2

I/O

Edge speed setting Bit 1 during RESET/active low thermal warning error output during
normal operation.

ERR1

I/O

Nonoverlap time setting MSB during RESET/active thermal low shutdown error output
during normal operation.

ERR0

I/O

Nonoverlap time setting Bit 1 during RESET/active low data-loss error output or low-side
transistor disable input during normal operation.

INA

Control pin for Transistors A1 and A2 always; also control pin for B1 and B2 in 2-channel mode.

INB

Edge speed setting LSB during RESET/during normal operation, control pin for Transistors
B1 and B2 in 4-channel mode; no function in 2-channel mode.

Positive power supply for low power digital circuitry.

DGND

Negative power supply for low power digital circuitry.

MUTE

Active low clickless mute input.

INC

Control pin for Transistors C1 and C2 always; also control pin for D1 and D2 in 2-channel mode.

IND

Nonoverlap time setting LSB during RESET/during normal operation, control pin for Transis-
tors D1 and D2 in 4-channel mode; no function in 2-channel mode.

RST/PDN

Active low RESET/power-down input.

CLK

External clock input in external clock mode.

27, 28, 29

PGND2

Negative power supply for high power Transistors C2 and D2.

30, 31, 32

OUTD

Output of transistor pair D1 and D2.

33, 34, 35

DD2

Positive power supply for high power Transistors C1 and D1.

36, 37, 38

OUTC

Output of transistor pair C1 and C2.

39, 40, 41, 42

PGND2

Negative power supply for high power Transistors C2 and D2.

43, 45, 48, 49

AGND

Negative power supply for low power analog circuitry.

MODE0

Clock source select (referenced to AGND); normally connected to AGND.

Positive power supply for low power analog circuitry.

MODE1

Channel mode select (referenced to AGND).

50, 51, 52

PGND1

Negative power supply for high power Transistors A2 and B2.

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AD1991

FUNCTIONAL DESCRIPTION
Device Architecture

The AD1991 is an 8-transistor, audio, power output stage. The
AD1991 is arranged internally as four transistor pairs that can
be used as two H-bridge outputs (2-channel mode) or as four
single-ended outputs (4-channel mode), using either two or four
TTL compatible inputs to control the transistors. A dead time
is automatically provided between the switching of the high-
side transistor and low-side transistor when the control inputs
change level, to ensure that both the high-side transistor and
low-side transistor are never on at the same time.

Clock Source and Channel Mode Selection

When the AD1991 is brought out of reset, the logic levels on
MODE0 and MODE1 are latched internally. MODE0 determines
the internal state machine clock source. MODE1 determines the
channel mode and the function of

ERR0 (see Tables I and II.)

When the internal clock is used, the CLK pin should not be
connected.

Table I. Clock Source Selection

MODE0

CLK Source

Internal

External

Table II. Channel Mode Selection

MODE1

Channel Mode

ERR0 Function

2-Channel Mode

Data Loss Detection Output

4-Channel Mode

Low-Side Disable Input

2-Channel Mode

Two loads are connected differentially--across OUTA and OUTB
and across OUTC and OUTD. Inputs INB and IND are unused
and should be tied to an appropriate dc voltage (see the Edge
Speed and Nonoverlap Settings section). In this mode,

ERR0 is

an error output used to indicate data loss, which occurs when
there are no transitions on INA or INC for more than 50 ms.
This signal condition is hazardous in 2-channel mode because it
can cause a potentially large and harmful dc voltage across the
differential loads. Table III shows the input/output relationship.

Table III. Input/Output Relationship in 2-Channel Mode

Input

Controlled Output

INA

OUTA, OUTB

INC

OUTC, OUTD

4-Channel Mode

The 4-channel mode has two types of configuration: audio and
power supply. Neither of these configurations require data loss
detection. In the audio configuration, each single-ended load is
connected to the output through a blocking capacitor, which
prevents dc from reaching the load, thereby negating the need
for data loss detection. While in the power supply configuration,
it is desired to maintain a dc voltage on the load, also negating
the need for data loss detection. When used in the power supply
configuration, the four low-side transistors can also be disabled
and left permanently open if desired. This allows the loads to be
driven by switching only the high-side transistor on and off.
ERR0 is an input in 4-channel mode and is used to select
whether the four low-side transistors are enabled or disabled,
with 0 selecting disabled and 1 selecting enabled. Table IV
summarizes the function of

ERR0 in this mode. Table V shows

the input/output relationship.

Table IV.

ERR0 Function in 4-Channel Mode

ERR0

Low-Side Transistor Status

Disabled

Enabled

Table V. Input/Output Relationship in 4-Channel Mode

Input

Controlled Output

INA

OUTA

INB

OUTB

INC

OUTC

IND

OUTD

1-Channel Mode

One load is connected differentially--across OUTA and OUTC,
and OUTB and OUTD. This mono operation is established
by configuring the part for 2-channel mode and externally
connecting INA to INC, OUTA to OUTC, and OUTB to
OUTD (see Figure 4).

Thermal Protection

The AD1991 features thermal protection. When the die tempera-
ture exceeds approximately 135

°C, the thermal warning error

output (

ERR2) is asserted. If the die temperature exceeds

approximately 150

°C, the thermal shutdown error output (ERR3)

is asserted. If this occurs, the part shuts down to prevent damage
to the part. When the die temperature drops below approximately
120

°C, both error outputs de-assert and the part returns to nor-

mal operation.

Overcurrent Protection

The AD1991 features overcurrent or short-circuit protection. If
the current through any power transistors exceeds 5 A, the part
is muted and the overcurrent error output (

ERR1) is asserted.

This is a latched error and does not clear automatically. To clear
the error condition and restore normal operation, the part must
be reset or

MUTE must be asserted and de-asserted.

REV. 0

AD1991

INA

INB

LEVEL SHIFTER

AND

SWITCH CONTROL

H-BRIDGE

AGND DGND

INPUT

TEST

CONTROL

PGND

INC

IND

CLK

RST/PDN

MUTE

CURRENT OVERLOAD
THERMAL SHUTDOWN
THERMAL WARNING
DATA LOSS

THERMAL PROTECTION
SHORT-CIRCUIT PROTECTION
MUTE CONTROL

OUTA

OUTB

OUTC

OUTD

Figure 4. Functional Block Diagram (1-Channel Mode)

EDGE SPEED AND NONOVERLAP SETTINGS

The AD1991 allows the user to select from one of eight different
edge speeds and from one of eight different nonoverlap times.
This allows the user to make a trade-off between distortion,
efficiency, overshooting at the outputs, and EMI. The following
sections describe the method used to program the settings.

Edge Speed

The edge speed is set by using the three pins,

ERR3, ERR2, and

INB, when

RST/PDN is low. The levels on the three pins are

latched by the rising edge of

RST/PDN. The latched value deter-

mines the edge speed thereafter, until

RST/PDN is brought low.

Table VI shows the appropriate logic levels for the corresponding
edge speeds. Note that INB is internally inverted, resulting in
the nonmonotonic sequence in Table VI.

Table VI. Edge Speed Settings

ERR3

ERR2

INB

Edge Speed

1 (Slowest Edge Speed)

8 (Fastest Edge Speed)

Nonoverlap Time

The nonoverlap time is set by using the three pins,

ERR1, ERR0,

and IND, when

RST/PDN is low. The levels on the three pins

are latched by the rising edge of

RST/PDN. The latched value

determines the nonoverlap time thereafter, until

RST/PDN is

brought low. Table VII shows the appropriate logic levels for
the corresponding nonoverlap times. Note that IND is internally
inverted, resulting in the nonmonotonic sequence in Table VII.

Note that

ERR3, ERR2, ERR1, and ERR0 are driven outputs

under normal operation and, therefore, should never be tied to a
dc voltage. The part contains internal 300 k

pull-up resistors

to pull these pins high during reset. If it is desired to set them
low to achieve a particular edge speed or nonoverlap time, this
should be done by pulling them low through resistors between
10 k

and 50 k.

Table VII. Nonoverlap Time Settings

ERR1

ERR0

IND

Nonoverlap Time

1 (Shortest Nonoverlap Time)

8 (Longest Nonoverlap Time)

REV. 0

AD1991

APPLICATION CONSIDERATIONS

Good board layout and decoupling are vital for correct operation
of the AD1991. Due to the fact that the part switches high currents,
there is the potential for large PV

bounce each time a transis-

tor transitions. This can cause unpredictable operation of the part.
To avoid this potential problem, close chip decoupling is essen-
tial. It is also recommended that the decoupling capacitors be
placed on the same side of the board as the AD1991 and connected
directly to the PV

and PGND pins. By placing the decoupling

capacitors on the other side of the board and decoupling through
vias, the effectiveness of the decoupling is reduced. This is
because vias have inductive properties and, therefore, prevent
very fast discharge of the decoupling capacitors. Best operation
is achieved with at least one decoupling capacitor on each side of
the AD1991 or optionally two capacitors per side can be used to
further reduce the series resistance of the capacitor. If these
decoupling recommendations cannot be followed and decoupling
through vias is the only option, the vias should be made as large
as possible to increase surface area, thereby reducing inductance
and resistance.

Figures 5 and 6 show two possible layouts to provide close chip
decoupling. In both cases, the PV

to PGND decoupling is as

close as possible to the pins of the AD1991. One solution uses
surface-mount capacitors that offer low inductance; however, each
output (OUTA, OUTB, OUTC, and OUTD) must be brought
through vias to another layer of the board to be brought to the
LC filter. The other solution uses through-hole capacitors that
have higher inductance but allow the outputs to connect directly
to the LC filter. In this solution, the inductor for OUTA and
OUTC would span the PV

trace. These diagrams show four

decoupling capacitors from PV

to PGND; however, this may

not be necessary if capacitors with low series resistance are
used. Another close chip capacitor is used for AV

to AGND

decoupling, with the actual power connections to the capacitors
being done through vias. This is quite acceptable since AV

a low current stable supply. Finally, a close chip capacitor is used
to decouple DV

to DGND. This is quite important since DV

is a digital supply whose current will change dynamically and,
therefore, requires good decoupling. For both PV

and DV

additional reservoir capacitors should be used to augment the
close chip decoupling, especially for PV

, which usually has very

large transients.

THERMAL CONSIDERATIONS

Careful consideration must be given to heat sinking the AD1991,
particularly in applications where the ambient temperature can
be much higher than normal room temperature. The three
thermal resistances of

, and

should be known in

order to correctly heat sink the part. These values specify the
temperature difference between two points, per unit power
dissipation.

specifies the temperature difference between the

junction (die) and the case (package) for each watt of power
dissipated in the die. The AD1991 is specified with a

°C/W, which means that for each watt of power dissipated in

the part, the junction (or die) temperature will be 1ºC higher
than the case (or package) temperature.

The value of

, the difference between the case and ambient

temperatures, is entirely dependent on the size of heat sink
attached to the case, the material used, the method of attach-
ment, and the airflow over the heat sink. The value of

specified as 26

°C/W for no heat sink and no airflow over the device.

Finally,

is the sum of the

and

values, and will be

between 1

°C/W and 27°C/W depending on the heat sink used.

This is the temperature difference between the junction (die) and
ambient temperature around the case (package) for each watt
dissipated in the part.

The AD1991 is specified to have a thermal shutdown of typically
150

°C die temperature. Good design procedures allow for a

margin, so the system should be designed such that the AD1991
die never goes above 140

°C. Knowing the maximum desirable

die temperature, the efficiency of the AD1991, the maximum
ambient temperature, and the maximum power that will be
delivered to the load, the necessary

can be calculated. For an

load, the AD1991 has a typical efficiency of 87%, which

can be reduced slightly to be conservative. For this example,
assume an 85% efficiency. If the power delivered to the loads is
to be 2

20 W rms continuous power, the power dissipated in

the AD1991 can be calculated as follows:

Power Supplied to Loads = 40 W rms

Total Power Supplied to the AD1991 = (40/85

100) = 47 W rms

Power Dissipated in the AD1991 = 7 W rms

If the ambient temperature can reach 85

°C maximum, the allowable

difference between the die temperature and ambient temperature
is (140 85) = 55

°C. This gives a

requirement of (55/7) =

7.9

°C/W. This requires a heat sink that gives a

of 6.9

°C/W.

The size and type of heat sink required can now be calculated.

If adequate heat sinking is not applied to the AD1991, the system
will suffer from the AD1991 going into thermal shutdown. It is
advisable to also use the thermal warning output on the AD1991
to attenuate the power being delivered to help prevent thermal
shutdown.

POWER-UP CONSIDERATIONS

Careful power-up is necessary when using the AD1991 to
ensure correct operation and to avoid possible latch-up issues.
The AD1991 should be held in RESET with MUTEB asserted
until all three power supplies have stabilized. Once the supplies
have stabilized, the part can be brought out of RESET, and
following this, MUTEB can be negated.

Part Number AD1991

Document Outline