REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

AD1852*

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

Š Analog Devices, Inc., 2000

Stereo, 24-Bit, 192 kHz

Multibit

DAC

FEATURES
5 V Stereo Audio DAC System
Accepts 16-Bit/18-Bit/20-Bit/24-Bit Data
Supports 24 Bits, 192 kHz Sample Rate
Accepts a Wide Range of Sample Rates Including:

32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and
192 kHz

Multibit Sigma-Delta Modulator with "Perfect

Differential Linearity Restoration" for Reduced Idle
Tones and Noise Floor

Data-Directed Scrambling DAC--Least Sensitive to

Jitter

Differential Output for Optimum Performance
117 dB Signal-to-Noise (Not Muted) at 48 kHz Sample

Rate (A-Weighted Mono)

114 dB Signal-to-Noise (Not Muted) at 48 kHz Sample

Rate (A-Weighted Stereo)

117 dB Dynamic Range (Not Muted) at 48 kHz Sample

Rate (A-Weighted Mono)

114 dB Dynamic Range (Not Muted) at 48 kHz Sample

Rate (A-Weighted Stereo)

105 dB THD+N (Mono Application Circuit)
102 dB THD+N (Stereo)
115 dB Stopband Attenuation
On-Chip Clickless Volume Control
Hardware and Software Controllable Clickless Mute
Serial (SPI) Control for: Serial Mode, Number of Bits,

Sample Rate, Volume, Mute, De-Emp

Digital De-Emphasis Processing for 32 kHz, 44.1 kHz,

48 kHz Sample Rates

Clock Autodivide Circuit Supports Five Master-Clock

Frequencies

*Patents Pending

FUNCTIONAL BLOCK DIAGRAM

SERIAL

DATA

INTERFACE

INTERPOLATOR

SERIAL CONTROL

INTERFACE

AUTO-CLOCK

DIVIDE CIRCUIT

VOLUME

MUTE

CONTROL DATA

INPUT

DIGITAL
SUPPLY

CLOCK

ANALOG
OUTPUTS

ZERO
FLAG

ANALOG

SUPPLY

DE-EMPHASIS

MUTE

RESET

SERIAL

MODE

16-/18-/20-/24-BIT

DIGITAL

DATA INPUT

AD1852

MULTIBIT SIGMA-

DELTA MODULATOR

ATTEN/

MUTE

DAC

MULTIBIT SIGMA-

DELTA MODULATOR

INTERPOLATION

ATTEN/

MUTE

VOLTAGE

REFERENCE

DAC

Flexible Serial Data Port with Right-Justified, Left-

Justified, I

S-Compatible and DSP Serial Port Modes

28-Lead SSOP Plastic Package

APPLICATIONS
Hi End: DVD, CD, Home Theater Systems, Automotive

Audio Systems, Sampling Musical Keyboards, Digital
Mixing Consoles, Digital Audio Effects Processors

PRODUCT OVERVIEW

The AD1852 is a complete high performance single-chip stereo
digital audio playback system. It is comprised of a multibit sigma-
delta modulator, digital interpolation filters, and analog output
drive circuitry. Other features include an on-chip stereo attenuator
and mute, programmed through an SPI-compatible serial control
port. The AD1852 is fully compatible with all known DVD
formats including 192 kHz as well as 96 kHz sample frequen-
cies and 24 bits. It also is backwards compatible by supporting
50

s/15

s digital de-emphasis intended for "Redbook" compact

discs, as well as de-emphasis at 32 kHz and 48 kHz sample rate.

The AD1852 has a very simple but very flexible serial data input
port that allows for glueless interconnection to a variety of ADCs,
DSP chips, AES/EBU receivers and sample rate converters. The
AD1852 can be configured in left-justified, I

S, right-justified,

or DSP serial port compatible modes. It can support 16, 18, 20,
and 24 bits in all modes. The AD1852 accepts serial audio data
in MSB first, twos-complement format. The AD1852 oper-
ates from a single 5 V power supply. It is fabricated on a single
monolithic integrated circuit and is housed in a 28-lead SSOP
package for operation over the temperature range 0

C to 70

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AD1852SPECIFICATIONS

TEST CONDITIONS UNLESS OTHERWISE NOTED

Supply Voltages (AV

, DV

)

5.0 V

Ambient Temperature

Input Clock

24.576 MHz (512

Mode)

Input Signal

996.11 Hz
0.5 dB Full Scale

Input Sample Rate

48 kHz

Measurement Bandwidth

20 Hz to 20 kHz

Word Width

20 Bits

Load Capacitance

100 pF

Load Impedance

47 k

Input Voltage HI

2.4 V

Input Voltage LO

0.8 V

ANALOG PERFORMANCE (See Figures)

Min

Typ

Max

Unit

Resolution

Bits

Signal-to-Noise Ratio (20 Hz to 20 kHz)

No Filter (Stereo)

112

No Filter

(Mono--See Figure 29)

115

With A-Weighted Filter (Stereo)

114

With A-Weighted Filter

(Mono--See Figure 29)

117

Dynamic Range (20 Hz to 20 kHz, 60 dB Input)

No Filter (Stereo)

107

112

No Filter

(Mono--See Figure 29)

115

With A-Weighted Filter (Stereo)

110

114

With A-Weighted Filter

(Mono--See Figure 29)

117

Total Harmonic Distortion + Noise (Stereo)

102

0.00079

Total Harmonic Distortion + Noise (Mono--See Figure 29)

105

0.00056

Total Harmonic Distortion + Noise (Stereo) V

= 20 dB

Total Harmonic Distortion + Noise (Stereo) V

= 60 dB

Analog Outputs

Differential Output Range (

Full Scale)

5.6

V p-p

Output Capacitance at Each Output Pin

Out-of-Band Energy (0.5

to 100 kHz)

CMOUT

2.37

DC Accuracy

Gain Error

2.0

+10

Interchannel Gain Mismatch

0.15

0.015

+0.15

Gain Drift

150

250

ppm/

DC Offset

Interchannel Crosstalk (EIAJ Method)

120

Interchannel Phase Deviation

0.1

Degrees

Mute Attenuation

100

De-Emphasis Gain Error

0.1

Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Specifications subject to change without notice.

DIGITAL I/O (0 C TO 70 C)

Min

Typ

Max

Unit

Input Voltage HI (V

)

2.2

Input Voltage LO (V

)

0.8

Input Leakage (I

@ V

= 2.4 V)

Input Leakage (I

@ V

= 0.8 V)

High Level Output Voltage (V

) I

= 1 mA

2.0

Low Level Output Voltage (V

) I

= 1 mA

0.4

Input Capacitance

Specifications subject to change without notice.

REV. 0

AD1852

TEMPERATURE RANGE

Min

Typ

Max

Unit

Specifications Guaranteed

Functionality Guaranteed

Storage

+150

Specifications subject to change without notice.

POWER

Min

Typ

Max

Unit

Supplies

Voltage, Analog and Digital

4.50

5.50

Analog Current

Analog Current--

RESET

Digital Current

Digital Current--

RESET

Dissipation

Operation--Both Supplies

265

Operation--Analog Supply

165

Operation--Digital Supply

100

Power Supply Rejection Ratio

1 kHz 300 mV p-p Signal at Analog Supply Pins

20 kHz 300 mV p-p Signal at Analog Supply Pins

Specifications subject to change without notice.

DIGITAL FILTER CHARACTERISTICS

Sample Rate (kHz)

Passband (kHz)

Stopband (kHz)

Stopband Attenuation (dB)

Passband Ripple (dB)

44.1

DC20

24.1328.7

110

0.0002

DC21.8

26.23358.28

110

0.0002

DC39.95

56.9327.65

115

0.0005

192

DC87.2

117327.65

+0/0.04 (DC21.8 kHz)
+0/0.5 (DC65.4 kHz)
+0/1.5 (DC87.2 kHz)

Specifications subject to change without notice.

GROUP DELAY

Chip Mode

Group Delay Calculation

Group Delay

Unit

INT8x Mode

5553/(128

)

48 kHz

903.8

INT4x Mode

5601/(64

)

96 kHz

911.6

INT2x Mode

5659/(32

)

192 kHz

921

Specifications subject to change without notice.

DIGITAL TIMING (Guaranteed Over 0 C to 70 C, AVDD = DVDD = +5.0 V 10%)

Min

Unit

DMP

MCLK Period (FMCLK = 256

FL/

RCLK)*

DML

MCLK LO Pulsewidth (All Modes)

0.4

DMP

DMH

MCLK HI Pulsewidth (All Modes)

0.4

DMP

DBH

BCLK HI Pulsewidth

DBL

BCLK LO Pulsewidth

DBP

BCLK Period

DLS

RCLK Setup

DLH

RCLK Hold (DSP Serial Port Mode Only)

DDS

SDATA Setup

DDH

SDATA Hold

RSTL

RST LO Pulsewidth

*Higher MCLK frequencies are allowable when using the on-chip Master Clock Autodivide Feature.
Specifications subject to change without notice.

AD1852

REV. 0

ABSOLUTE MAXIMUM RATINGS

Min

Max

Unit

to DGND

0.3

to AGND

0.3

Digital Inputs

DGND 0.3

+ 0.3

Analog Outputs

AGND 0.3

+ 0.3

AGND to DGND

0.3

Reference Voltage

(AV

+ 0.3)/2

Soldering

300

sec

*Stresses greater than those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

PACKAGE CHARACTERISTICS

Min

Typ

Max

Unit

(Thermal Resistance

109

C/W

[Junction-to-Ambient])

(Thermal Resistance

C/W

[Junction-to-Case])

ORDERING GUIDE

Model

Temperature

Package Description

Package Option

AD1852JRS

C to 70

28-Lead Shrink Small Outline Package (SSOP)

RS-28

AD1852JRSRL

C to 70

28-Lead Shrink Small Outline Package (SSOP)

RS-28 on 13" Reels

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1852 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

PIN CONFIGURATION

TOP VIEW

(Not to Scale)

AD1852

FILTR

OUTR

OUTR+

AGND

96/

DEEMP

ZEROR

DGND

MCLK

CLATCH

CCLK

192/

CDATA

AGND

OUTL

OUTL+

AVDD

FILTB

IDPM1

IDPM0

DVDD

SDATA

BCLK

LRCLK

ZEROL

MUTE

RESET

AD1852

REV. 0

PIN FUNCTION DESCRIPTIONS

Pin

Input/Output

Pin Name

Description

DGND

Digital Ground.

MCLK

Master Clock Input. Connect to an external clock source at either 256 F

, 384 F

512 F

, 768 F

, or 1024 F

CLATCH

Latch Input for Control Data. This input is rising-edge sensitive.

CCLK

Control Clock Input for Control Data. Control input data must be valid on the rising
edge of CCLK. CCLK may be continuous or gated.

CDATA

Serial Control Input, MSB first, containing 16 bits of unsigned data per channel. Used
for specifying channel-specific attenuation and mute.

No Connect.

192/

Selects 48 kHz (LO) or 192 kHz Sample Frequency.

ZEROR

Right Channel Zero Flag Output. This pin goes HI when Right Channel has no signal
input for more than 1024 LR Clock Cycles.

DEEMP

De-Emphasis. Digital de-emphasis is enabled when this input signal is HI. This is used
to impose a 50

s/15

s response characteristic on the output audio spectrum at an

assumed 44.1 kHz sample rate. Curves for 32 kHz and 48 kHz sample rates may be
selected via SPI control register.

96/

Selects 48 kHz (LO) or 96 kHz Sample Frequency.

11, 15

AGND

Analog Ground.

OUTR+

Right Channel Positive Line Level Analog Output.

OUTR

Right Channel Negative Line Level Analog Output.

FILTR

Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage refer-
ence with parallel 10

F and 0.1

F capacitors to the AGND.

OUTL

Left Channel Negative Line Level Analog Output.

OUTL+

Left Channel Positive Line Level Analog Output.

AVDD

Analog Power Supply. Connect to Analog 5 V Supply.

FILTB

Filter Capacitor Connection. Connect 10

F capacitor to AGND (Pin 15).

IDPM1

Input Serial Data Port Mode Control One. With IDPM0, defines 1 of 4 serial modes.

IDPM0

Input Serial Data Port Mode Control Zero. With IDPM1, defines 1 of 4 serial modes.

ZEROL

Left Channel Zero Flag Output. This pin goes HI when Left Channel has no signal
input for more than 1024 LR Clock Cycles.

MUTE

Mute. Assert HI to mute both stereo analog outputs. Deassert LO for normal operation.

RESET

Reset. The AD1852 is reset on the rising edge of this signal. The serial control port
registers are reset to the default values. Connect HI for normal operation.

RCLK

Left/

Right Clock Input for Input Data. Must run continuously.

BCLK

Bit Clock Input for Input Data. Need not run continuously; may be gated or used in a
burst fashion.

SDATA

Serial Input, MSB first, containing two channels of 16, 18, 20, and 24 bits of twos
complement data per channel.

DVDD

Digital Power Supply Connect to digital 5 V supply.

Table I. Serial Data Input Mode

IDPM1 (Pin 20)

IDPM0 (Pin 21)

Serial Data Input Format

Right-Justified

S-Compatible

Left-Justified

DSP

AD1852

REV. 0

SDATA

INPUT

LSB

MSB2

MSB1

LSB+2 LSB+1

MSB2

MSB1

MSB

LSB+2 LSB+1

LSB

BCLK

INPUT

CLK

INPUT

LEFT CHANNEL

RIGHT CHANNEL

MSB

LSB

Figure 1. Right-Justified Mode

LEFT CHANNEL

RIGHT CHANNEL

MSB2

MSB1

LSB+2

LSB+1

LSB

MSB2

MSB1

MSB

LSB+2

LSB+1

LSB

MSB

CLK

INPUT

BCLK

INPUT

SDATA

INPUT

MSB

Figure 2. I

S-Justified Mode

MSB2

MSB1

LSB+2

LSB+1

LSB

MSB2

MSB1

MSB

LSB+2

LSB+1

LSB

MSB1

MSB

CLK

INPUT

BCLK

INPUT

SDATA

INPUT

LEFT CHANNEL

RIGHT CHANNEL

MSB

Figure 3. Left-Justified Mode

SDATA

INPUT

MSB1

LSB+2

LSB+1

LSB

MSB1

LSB+2

LSB+1

LSB

MSB

MSB1

MSB

CLK

INPUT

LEFT CHANNEL

RIGHT CHANNEL

BCLK

INPUT

MSB

Figure 4. Left-Justified DSP Mode

CLK

INPUT

LEFT CHANNEL

RIGHT CHANNEL

BCLK

INPUT

SDATA

INPUT

LSB

MSB1

MSB2

LSB+2

LSB+1

LSB

MSB

MSB1

MSB2

LSB+2

LSB+1

LSB

MSB

MSB1

MSB

Figure 5. 32

Packed Mode

AD1852

REV. 0

OPERATING FEATURES
Serial Data Input Port

The AD1852's flexible serial data input port accepts data in
twos-complement, MSB-first format. The left channel data field
always precedes the right channel data field. The serial mode is
set by using either the external mode pins (IDPM0 Pin 21 and
IDPM1 Pin 20) or the mode select bits (Bits 4 and 5) in the SPI
control register. To control the serial mode using the external
mode pins, the SPI mode select bits should be set to zero (default
at power-up). To control the serial mode using the SPI mode
select bits, the external mode control pins should be grounded.

In all modes except for the right-justified mode, the serial port
will accept an arbitrary number of bits up to a limit of 24. Extra
bits will not cause an error, but they will be truncated internally.
In the right-justified mode, control register Bits 8 and 9 are used
to set the wordlength to 16 bits, 20 bits, or 24 bits. The default
on power- up is 24-bit mode. When the SPI Control Port is not
being used, the SPI pins (3, 4, and 5) should be tied LO.

Serial Data Input Mode

The AD1852 uses two multiplexed input pins to control the mode
configuration of the input data port mode. See Table I.

Figure 1 shows the right-justified mode (16 bits shown). L/

RCLK

is HI for the left channel, LO for the right channel. Data is valid
on the rising edge of BCLK.

In normal operation, there are 64-bit clocks per frame (or 32
per half-frame). When the SPI wordlength control bits (Bits 8
and 9 in the control register) are set to 24 bits (0:0), the serial

port will begin to accept data starting at the eighth bit clock
pulse after the L/

RCLK transition. When the wordlength con-

trol bits are set to 20-bit mode, data is accepted starting at
the twelfth-bit clock position. In 16-bit mode, data is accepted
starting at the sixteenth-bit clock position. These delays are
independent of the number of bit clocks per frame, and therefore
other data formats are possible using the delay values described
above. For detailed timing, see Figure 6.

Figure 2 shows the I

S mode. L/

RCLK is LO for the left chan-

nel and HI for the right channel. Data is valid on the rising edge
of BCLK. The MSB is left-justified to an L/

RCLK transition

but with a single BCLK period delay. The I

S mode can be used

to accept any number of bits up to 24.

Figure 3 shows the left-justified mode. L/

RCLK is HI for the

left channel, and LO for the right channel. Data is valid on the
rising edge of BCLK. The MSB is left-justified to an L/

RCLK

transition, with no MSB delay. The left-justified mode can
accept any wordlength up to 24 bits, and any number of bit clocks
from two times the word length to 64 bit clocks per frame.

Figure 4 shows the DSP serial port mode. L/

RCLK must pulse

HI for at least one bit clock period before the MSB of the left
channel is valid, and L/

RCLK must pulse HI again for at least

one bit clock period before the MSB of the right channel is valid.
Data is valid on the falling edge of BCLK. The DSP serial port
mode can be used with any wordlength up to 24 bits.

In this mode, it is the responsibility of the DSP to ensure that
the left data is transmitted with the first L/

RCLK pulse, and

that synchronism is maintained from that point forward.

DLS

BCLK

CLK

SDATA

LEFT-JUSTIFIED

MODE

SDATA

RIGHT-JUSTIFIED

MODE

LSB

SDATA

S-JUSTIFIED

MODE

DBH

DBP

DBL

DDS

MSB

MSB-1

DDH

DDS

MSB

DDH

DDS

DDH

MSB

8-BIT CLOCKS

(24-BIT DATA)

12-BIT CLOCKS

(20-BIT DATA)

16-BIT CLOCKS

(16-BIT DATA)

Figure 6. Serial Data Port Timing

AD1852

REV. 0

Note that the AD1852 is capable of a 32

BCLK frequency

"packed mode" where the MSB is left-justified to an L/

RCLK

transition, and the LSB is right-justified to the opposite L/

RCLK

transition. L/

RCLK is HI for the left channel, and LO for the

right channel. Data is valid on the rising edge of BLCK. Packed
mode can be used when the AD1852 is programmed in right-
justified or left-justified mode. Packed mode is shown is Figure 5.

Master Clock Autodivide Feature

The AD1852 has a circuit that autodetects the relationship
between master clock and the incoming serial data, and inter-
nally sets the correct divide ratio to run the interpolator and
modulator. The allowable frequencies for each mode are shown
above. Master clock should be synchronized with L/

RCLK but

phase relation between master clock and L/

RCLK is not critical.

D15

D14

CHD

CCH

CSU

CCL

CLL

CLH

CDATA

CCLK

CLATCH

CLSU

Figure 7. Serial Control Port Timing

Table II.

Nominal Input

Internal Sigma-

Chip Mode

Allowable Master Clock Frequencies

Sample Rate

Delta Clock Rate

INT8

Mode

256

, 384

, 512

, 768

, 1024

48 kHz

128

INT4

Mode

128

, 192

, 256

, 384

, 512

96 kHz

INT2

Mode

, 96

, 128

, 192

, 256

192 kHz

SPI REGISTER DEFINITIONS

The SPI port allows flexible control of many chip parameters. It is
organized around three registers; a LEFT-CHANNEL VOLUME
register, a RIGHT-CHANNEL VOLUME register, and a
CONTROL register. Each WRITE operation to the AD1852
SPI control port requires 16 bits of serial data in MSB-first format.
The bottom two bits are used to select one of three registers,
and the top 14 bits are then written to that register. This allows
a write to one of the three registers in a single 16-bit transaction.

The SPI CCLK signal is used to clock in the data. The incom-
ing data should change on the falling edge of this signal. At the
end of the 16 CCLK periods, the CLATCH signal should rise
to clock the data internally into the AD1852.

AD1852

REV. 0

Table III. SPI Digital Timing

Min

Unit

CCH

CCLK HI Pulsewidth

CCL

CCLK LOW Pulsewidth

CSU

CDATA Setup Time

CHD

CDATA Hold Time

CLL

CLATCH LOW Pulsewidth

CLH

CLATCH HI Pulsewidth

CLSU

CLATCH Setup Time

MCLK

Register Addresses

The lowest two bits of the 16-bit input word are decoded as fol-
lows to set the register that the upper 14 bits will written into.

VOLUME LEFT AND VOLUME RIGHT REGISTERS

A write operation to the left or right volume registers will acti-
vate the "autoramp" clickless volume control feature of the
AD1852. This feature works as follows. The upper 10 bits of the
volume control word will be incremented or decremented by 1 at
a rate equal to the input sample rate. The bottom four bits are
not fed into the autoramp circuit and thus take effect immediately.
This arrangement gives a worst-case ramp time of about 20 ms
for step changes of more than 60 dB, which has been deter-
mined by listening tests to be optimal in terms of preventing the
perception of a "click" sound on large volume changes. See Fig-
ure 8 for a graphical description of how the volume changes
as a function of time.

The 14-bit volume control word is used to multiply the signal,
and therefore the control characteristic is linear, not dB. A constant
dB/step characteristic can be obtained by using a lookup table
in the microprocessor that is writing to the SPI port.

The volume

word is unsigned (i.e., 0 dB is 11 1111 1111 1111).

Table IV.

Bit 1

Bit 0

Register

Volume Left

Volume Right

Control Register

20ms

TIME

60

LEVEL dB

VOLUME REQUEST REGISTER

ACTUAL VOLUME REGISTER

Figure 8. Smooth Volume Control

SPI Timing

The SPI port is a 3-wire interface with serial data (CDATA),
serial bit clock (CCLK), and data latch (CLATCH). The
data is clocked into an internal shift register on the rising
edge of CCLK. The serial data should change on the falling
edge of CCLK and be stable on the rising edge of CCLK.
The rising edge of CLATCH is used internally to latch the par-
allel data from the serial-to-parallel converter. This rising edge
should be aligned with the falling edge of the last CCLK pulse
in the 16-bit frame. The CCLK can run continuously between
transactions.

Note that the serial control port timing is asynchronous to the
serial data port timing. Changes made to the attenuator level
will be updated on the next edge of the L/

RCLK after the

CLATCH write pulse as shown in Figure 7.

Mute

The AD1852 offers two methods of muting the analog output.
By asserting the MUTE (Pin 23) signal HI, both the left and
right channel are muted. As an alternative, the user can assert
the mute bit in the serial control register (data11) HI. The
AD1852 has been designed to minimize pops and clicks when
muting and unmuting the device by automatically "ramping"
the gain up or down. When the device is unmuted, the volume
returns to the value set in the volume register.

AD1852

REV. 0

Control Register

Table V shows the functions of the control register. The control
register is addressed by having an `01' in the bottom two bits of
the 16-bit SPI word. The top 14 bits are then used for the con-
trol register.

De-Emphasis

The AD1852 has a built-in de-emphasis filter that can be used
to decode CDs that have been encoded with the standard
"redbook" 50

s/15

s emphasis response curve. Three curves

are available; one each for 32 kHz, 44.1 kHz, and 48 kHz sam-
pling rates. The external "DEEMP" pin (Pin 9) turns on the
44.1 kHz de-emphasis filter. The other filters may be selected by
writing to Control Bits 2 and 3 in the control register. If the SPI
port is used to control the de-emphasis filter, the external DEEMP
pin should be tied LO.

Output Impedance

The output impedance of the AD1852 is 65

30%.

Reset

The AD1852 may be reset either by a dedicated hardware pin
(

RESET, Pin 24) or by software, via the SPI control port. While

reset is active, normal operation of the AD1852 is suspended and

Table V.

Bit 11

Bit 10

Bit 9:8

Bit 7

Bit 6

Bit 5:4

Bit 3:2

INT2

Mode

INT4

Mode

Number of

Reset.

Soft Mute OR'd Serial Mode OR'd

De-Emphasis Filter

OR'd with Pin 7

OR'd with Pin 10

Bits in Right-

Default = 0

with Pin.

with Mode Pins.

Select.

(192/

48).

(96/

48).

Justified Serial

Default = 0

IDPM1:IDPM0

0:0 No Filter

Default = 0

Mode.

0:0 Right-Justified

0:1 44.1 kHz Filter

0:0 = 24

0:1 I

1:0 32 kHz Filter

0:1 = 20

1:0 Left-Justified

1:1 48 kHz Filter

1:0 = 16

1:1 DSP Mode

Default = 0:0

the outputs assume midscale values. The AD1852 should always
be reset at power up. The

RESET function should be active for

a minimum of 64 master clock periods. When the

RESET func-

tion becomes inactive, normal operation will continue after a
delay equal to the group delay plus three MCLK periods.

Using the

RESET pin, the internal registers will be set to their

default values, when the

RESET pin is active low. Default

operation will then be enabled when the

RESET pin is raised.

Alternatively, the internal registers can be reset to their default
values by setting Bit 7, of the internal control register, high.
When Bit 7 is reset low, default operation will continue. The
software reset differs from the hardware reset because the soft
reset does not affect the values stored in the SPI registers.

Control Signals
The IDPM0 and IDPM1 control inputs are normally connected
HI or LO to establish the operating state of the AD1852. They
can be changed dynamically (and asynchronously to L/

RCLK

and the master clock), but it is possible that a click or pop sound
may result during the transition from one serial mode to another.
If possible, the AD1852 should be placed in mute before such a
change is made.

AD1852

REV. 0

Figures 914 show the calculated frequency response of the
digital interpolation filters. Figures 1526 show the performance
of the AD1852 as measured by an Audio Precision System 2
Cascade. For the wideband plots, the noise floor shown in the
plots is higher than the actual noise floor of the AD1852. This is

FREQUENCY kHz

0.001

0.0008

0.0006

0.0004

0.0002

0.0004

0.0006

0.0008

0.001

Figure 9. Passband Response 8

Mode, 48 kHz Sample

Rate

FREQUENCY kHz

0.5

10

0.4

0.3

0.2

0.1

0.2

0.3

0.4

0.5

Figure 10. 44 kHz Passband Response 4

Mode, 96 kHz

Sample Rate

FREQUENCY kHz

2.0

1.5

1.0

0.5

1.0

2.0

1.5

0.5

Figure 11. 88 kHz Passband Response 2

Mode, 192 kHz

Sample Rate

caused by the higher noise floor of the "High Bandwidth" ADC
used in the Audio Precision measurement system. The two-tone
test shown in Figure 17 is per the SMPTE standard for measur-
ing Intermodulation Distortion.

Typical Performance Characteristics

FREQUENCY kHz

ATTENUATION dB

60

100

160

20

40

80

120

140

150

200

100

250

300

350

Figure 12. Complete Response, 8

Mode, 48 kHz

Sample Rate

150

200

60

100

250

20

40

80

120

140

300

FREQUENCY kHz

160

Figure 13. Complete Response, 4

Mode, 96 kHz

Sample Rate

FREQUENCY kHz

60

120

160

40

20

80

100

140

150

200

100

250

Figure 14. Complete Response, 2

Mode, 192 kHz

Sample Rate

AD1852

REV. 0

FREQUENCY Hz

dBr

120

100

10k

110

100

90

80

70

60

50

20k

Figure 15. THD vs. Frequency Input @ 3 dBFS, SR 48 kHz

FREQUENCY Hz

dBr

12

100

10k

10

20k

Figure 16. Normal De-Emphasis Frequency Response
Input @ 10 dBFS, SR 48 kHz

FREQUENCY kHz

dBr

90

110

130

150

70

50

30

10

Figure 17. SMPTE/DIN 4:1 IMD 60 Hz/7 kHz @ 0 dBFS

dBFS

80

90

100

110

70

60

50

40

30

20

10

120

100

80

60

40

20

Figure 18. THD + N Ratio vs. Amplitude Input 1 kHz,
SR 48 kS/s, 24-Bit

FREQUENCY kHz

dBr

130

140

150

160

120

110

100

90

Figure 19. Noise Floor for Zero Input, SR 48 kHz

FREQUENCY kHz

dBr

130

140

150

120

110

100

90

80

70

60

50

40

30

20

10

Figure 20. Input 0 dBFS @ 1 kHz, BW 10 Hz to 22 kHz,
SR 48 kHz

AD1852

REV. 0

dBFS

dBr

80

100

120

140

60

40

20

140

120

100

60

40

20

80

Figure 21. Linearity vs. Amplitude Input 200 Hz,
SR 48 kS/s, 24-Bit Word

FREQUENCY Hz

dBr

76

74

64

100

10k

70

72

68

66

20k

Figure 22. Power Supply Rejection vs. Frequency
AV

5 V DC + 100 mV p-p AC

FREQUENCY kHz

100

120

dBr

100

10

40

70

80

90

20

30

50

60

110

120

130

140

Figure 23. Wideband Plot, 15 kHz Input, 8

Interpolation,

SR 48 kHz

FREQUENCY kHz

dBr

130

140

150

120

110

100

90

80

70

60

50

160

Figure 24. Dynamic Range for 1 kHz @ 60 dBFS,
Triangular Dithered Input

FREQUENCY kHz

100

dBr

10 15 20 25

10

40

70

80

90

20

30

50

60

110

120

130

140

150

160

35 40 45

50 55 60 65 70 75

Figure 25. Wideband Plot, 75 kHz Input, 2

Interpolation,

SR 192 kHz

FREQUENCY kHz

100

120

dBr

100

10

40

70

80

90

20

30

50

60

110

120

130

140

Figure 26. Wideband Plot, 37 kHz Input, 4

Interpolation,

SR 96 kHz

AD1852

REV. 0

Figure 27. AD1852 DAC, Output Buffers, and LP Filters

AD1852JRS

96/

192/

SDATA

LRCLK

SCLK

MCLK

IDPM0

IDPM1

DEEMP

MUTE

CLATCH

CCLK

CDATA

ZEROR

ZEROL

RESET

DGND

AGND

OUTL+

OUTL

OUTR+

OUTR

FILTB

AVDD

DVDD

C9
220pF
NP0

1.96k

R11

1.96k

C10
220pF
NP0

R16

1.87k

R10

1.96k

R20

200

J11

LEFT
OUT

C15

10nF

NP0

U3B
SSM2135

1.96k

C14
1nF
NP0

R17

1.87k

C13
1nF
NP0

C11
220pF
NP0

R13

1.96k

R15

1.96k

C12
220pF
NP0

R18

1.87k

R14

1.96k

R21

200

J21

RIGHT
OUT

C18

10nF

NP0

U3A
SSM2135

R12

1.96k

C17
1nF
NP0

R19

1.87k

C16
1nF
NP0

100nF

+AV

AV

100nF

3RD ORDER LP BESSEL FILTER
CORNER FREQUENCY: 75kHz
GROUP DELAY: ~3.5 s

CLATCH

CCLK

CDATA

RESET

U2A

HC04

U2B

HC04

AGND

FB1

600Z

FILTR

C8
10 F

C1
100nF

C7
10 F

CR1
ZERO
LEFT

100nF

CR2
ZERO
RIGHT

R6
221

R7
221

100nF

DVDD

100nF

AVDD

MUTE

DEEMP

SCLK

MCLK

SDATA

LRCLK

10k

R5
10k

DVDD

I/F

MODE

JP21

I/F MODE IDPM1 IDPM0

RJ, 16-BIT

RJ, 20-BIT

RJ, 24-BIT

MCLK/SR SELECT

SELECT

RATE 2xMCLK

384/

256

96/

MCLK

SPDIF

44.1

11,2896

DIRECT

48.0

11,2880

DIRECT

96.0

12,2880

DGND

JP11

MCLK/SR SEL

10k

DVDD

AD1852 STEREO DAC

OUTPUT BUFFERS & LP FILTERS

AD1852

REV. 0

AD1852

3.01k

R13

1.00k

3.01k

R14

1.00k

3.01k

R6
3.01k

C2
270pF

R5
3.01k

C2
270pF

1.5nF

R17

549

C5
2.2nF

R19

53.6k

S LEFT/RIGHT

DATA SEPARATOR

AND INVERTER

AD797

AD1852

3.01k

R15

1.00k

3.01k

R16

1.00k

3.01k

R10

3.01k

R12
3.01k

C4
270pF

R11
3.01k

C3
270pF

1.5nF

R18

549

C6
2.2nF

R20

53.6k

AD797

SDATA
LRCLK
BCLK

L+

R+

L+

R+

180

MCLK

S INPUT TO

DATA SEPARATOR

OUTPUT

LRCLK

SDATA

LRCLK

LSDATA

RDATA

Ln+1

Rn+1

Ln+2

Rn+2

Ln+1

Ln+2

Rn+1

Rn+2

Ln+2

SDATA

LRCLK

BCLK

C10
1.5nF

C8
1.5nF

Figure 28. Mono Application Circuit

Part Number AD1852