AB180-20TM
8-bit OCA Processor
for General Purpose
and Protocol Engines
Combines High Performance and Low-Cost
AB180-20
Protocol
Engine
Processor
Product Specification
AB Semicon AB180-20TM
General Purpose and Protocol Engine Processor
Product Specification
For the latest information on the AB180-20, check the product specification on the AB Semicon web-site
at:
http://www.ab-semicon.com
Copyright
© Copyright 1999 AB Semicon Limited. All rights reserved. No part of this publication may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language or any computer
language, in any form or by any third party, without the prior written permission of AB Semicon Limited.
Disclaimer
AB Semicon Limited reserves the right to revise this publication and to make changes from time to time to
the contents hereof without obligation to notify any person or organization of such revision or changes. AB
Semicon Limited has endeavoured to ensure that the information in this publication is correct, but will not
accept liability for any error or omission.
AB180-20TM
General Purpose
and Protocol Engine
One Cycle Architecture Processor
The answer to every Z80, Z180, HD64180 user in the world - yes it has
the horsepower you were looking for, no you do not have to re-write
your code, you can use your existing Z80 Assemblers, Linkers and C-
compilers. Some minor differences do exist.
Features:
*
40 MHz
frequency synthesized 8 bit processor
*
Memory to Memory Block Transfer at 10 Mbytes/sec
*
Memory to I/O and I/O to Memory Block Transfer at 10 Mbytes/sec
*
8 bit Data bus
*
20 bit Address bus
*
Synchronous serial I/O suitable for Apple Local Talk up to 1Mbaud
*
100pin Quad Flat Pack packaging
*
Two 16bit Timers
*
Dual 3.3/5V operation or single 3.3V
*
Each Clock cycle (at 20 MHz) one instruction (for single byte instructions) or the
instruction is carried out at the end of the last byte fetch of a multi-byte instruction
- 4 -
rev 2.6
- 5 -
rev 2.6
Contents
Introduction ............................................................................................................ 7
Chip Structure ......................................................................................................................... 7
Applications ........................................................................................................................... 8
Programmer Guide ................................................................................................................... 9
Hardware Guide .................................................................................................................... 10
Device Details ...................................................................................................... 11
Package Information for AB180-20 ....................................................................................... 11
Packaging Information .......................................................................................................... 12
I/O Pin Assignment .............................................................................................................. 13
Current Consumption v Frequency for the AB180-20 IC ...................................................... 17
Overview .............................................................................................................. 18
AB180-20 Architecture ......................................................................................................... 18
Internal I/O Registers ............................................................................................................ 19
Table of Registers ................................................................................................................. 20
I/O Addressing Notes .......................................................................................................... 22
Dynamic RAM Refresh Control ............................................................................................ 22
Refresh Control and RESET .................................................................................................. 23
Dynamic RAM Refresh Operation Notes ............................................................................. 23
Logical Address Spaces ....................................................................................................... 24
Logical to Physical Address Translation .............................................................................. 24
Memory Management Unit (MMU) .................................................................. 25
Wait State Control ................................................................................................................ 25
MMU Block Diagram ............................................................................................................ 26
MMU Register ...................................................................................................................... 26
MMU Register Description .................................................................................................. 28
Physical Address Translation .............................................................................................. 28
MMU and RESET ................................................................................................................. 29
MMU Register Access Timing ............................................................................................. 29
Interrupt Control .................................................................................................. 30
Interrupt Control Registers and Flags .................................................................................. 30
INT/TRAP Control Register (ITC) ........................................................................................ 31
TRAP Interrupt ..................................................................................................................... 32
External Interrupts ................................................................................................................ 34
Internal Interrupts ................................................................................................................. 36
Interrupt Acknowledge Cycle Timing ................................................................................... 38
Interrupt Sources and RESET ............................................................................................... 38
I/O Functions ........................................................................................................ 39
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