A-Data

ADD8608A8A

Double Data Rate SDRAM

8M x 8 Bit x 4 Banks

General Description

The ADD8608A8A are four-bank Double Data
Rate(DDR) Synchronous DRAMs organized as
8,392,608 words x 8 bits x 4 banks,
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Data outputs occur at both rising edges of CK and
/CK.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications

Features

2.5V for VDDQ power supply

SSTL_2 interface

MRS Cycle with address key programs
-CAS Latency (2, 2.5)
-Burst Length (2,4 &8)
-Burst Type (sequential & Interleave)

4 banks operation

Differential clock input (CK, /CK) operation

Double data rate interface

Auto & Self refresh

8192 refresh cycle

DQM for masking

Package:66-pins 400 mil TSOP-Type II

Ordering Information.

Part No.

Frequency

Interface

Package

ADD8608A8A-75BA 133Mhz(7.5ns/CL=2)

ADD8608A8A-75B 133Mhz(7.5ns/CL=2.5)

SSTL_2 400mil

66pin

TSOPII

Pin Assignment

1
2
3
4
5
6
7
8
9

D D

D Q0

D D Q

N C

D Q 1

S S Q

N C

D Q 2

D D Q

62
61

5 9
5 8

S S

D Q 7

S SQ

N C

D Q 6

D D Q

N C

D Q 5

S SQ

10
11
12
13
14
15
16
17
18
19
20

N C

D Q 3

S S Q

N C

D D Q

N C

W E

C A S

R A S

C S

N C

D Q 4

D D Q

N C

S S Q

D Q S

N C

D M

A 6

A 5

S S

R E F

S S

21
22
23
24
25
26
27
28
29

B S 0

B S 1

A10/AP

A 0

A 1

A 2

D D

30
31
32
33

3 6

3 8

NC 1

A 3

N C

CKE

A12

A11

A 8

5 7
56

55
54

5 3
52
5 1
5 0
4 9

4 8

47
46

4 5
44

65
6

N C

D D

66-pin plastic TSOP II 400 mil

Rev 2 April, 2002

A-Data

ADD8608A8A

Pin Description

PIN NAME

FUNCTION

CK, /CK

System Clock

Differential clock input.

CKE Clock

Enable

Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby

/CS

Chip Select

Disables or Enables device operation by masking or enabling all input
except CK, CKE and DQ

A0~A12

Address

Row / Column address are multiplexed on the same pins.
Row address : A0~A12
Column address : A0~A9

BS0~BS1 Banks Select

Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.

DQ0~DQ7 Data

Data inputs / outputs are multiplexed on the same pins.

/RAS

Row Address Strobe

Latches row addresses on the positive edge of the CLK with /RAS low

/CAS

Column Address Strobe

Latches Column addresses on the positive edge of the CLK with /CAS
low

/WE

Write Enable

Enables write operation and row recharge.

VDD/VSS Power Supply/Ground

Power and Ground for the input buffers and the core logic.

DDQ

SSQ

Data Output Power/Ground Power supply for output buffers.

VREF

Reference Voltage

Reference voltage for inputs for SSTL interface.

No Connection

This pin is recommended to be left No Connection on the device.

Block Diagram

CKE

Clock
Generator

Address

/CS

/RAS

/CAS

/WE

DQM

Mode
Register

Command Decoder

Control Logic

w Decod

Address
Buffer
&
Refresh
Counter

Column
Address
Buffer
&
Refresh
Counter

Bank0

Bank2

Bank3

Bank1

Amplifier

Column Decoder

Data Control Circuit

ata Latch

DQ0~DQ7

DQS

Rev 2 April, 2002

A-Data

ADD8608A8A

Absolute Maximum Ratings

Parameter Symbol

Value

Unit

Voltage on any pin relative to Vss

, V

out

-0.5

3.6

Voltage on VDD supply relative to Vss

, V

DDQ

-1.0

3.6

Storage temperature

STG

-55 ~ +150

Power dissipation

1.5

Short circuit current

OUT

Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC Operating Condition

Voltage referenced to Vss = 0V, T

= 0 to 70

Parameter Symbol

Min

Max

Unit

Note

Supply voltage

2.3 2.7 V

Supply voltage

DDQ

2.3 2.7

Input logic high voltage

REF

+0.15

DDQ

+0.3 V

Input logic low voltage

-0.3

REF

-0.15

V 2

Differential Clock DC Input voltage

ICK

-0.3

DDQ

+0.3

Input Differential CLK&/CLK voltage

0.7

DDQ

+0.6-

Input leakage current

-5 5

uA 3

Output leakage current

-5 5 uA 4

Reference Voltage

REF

0.49*

DDQ

0.51* V

DDQ

Termination Voltage

REF

-0.04

REF

+0.04

Note : 1. V

DDQ

must not exceed the level of V

DDQ

2.V

(min)=-0.9V with a pulse width 5ns .

3.Any

input

3.6V, all other pins are not under test = 0V.

4.Dout is disabled, 0V V

OUT

2.7V.

REF

is expected to be equal to 0.5* V

DDQ

of the transmitting device, and to track variations in the DC level of

the same. Peak to peak noise on V

REF

may not exceed ±2% of the DC value.

Rev 2 April, 2002

A-Data

ADD8608A8A

AC Operating Condition

Voltage referenced to Vss = 0V, T

= 0 to 70

Parameter Symbol

Value

Unit

Note

AC input high / low level voltage

/ V

VREF+0.31/VREF-0.31 V

Input timing measurement reference level voltage

Vtrip

1.4

Input rise / fall time

TR / tF

Output timing measurement reference level

Voutfef

1.4

Output load capacitance for access time measurement

Note: 1. 3.15V V

3.6V is applied for VDD8608A4A5.

2. Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF). For details,

refer to AC/DC output load circuit.

Capacitance

TA=25, f-=1Mhz

Parameter Pin

Symbol

Min

Max

Unit

CK, /CK

Cl1

3.0

Input capacitance

A0~A12,BS0,BS1,CKE,/CS,/RAS,

/CAS,/WE,DQM

Cl2 2

3.0

Data input / output capacitance DQM

CI/O

Output load circuit

Output Load Circuit (SSTL_2)

Output

Z0=50

LOAD

=30pF

REF

=0.5*V

DDQ

=50

=0.5*V

DDQ

Rev 2 April, 2002

Part Number ADD8608A8A